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I found it. http://www.xilinx.com/xapp/xapp501.pdf Thank ^%#$@& for google. "steve synakowski" <srs@twcny.rr.com> wrote in message news:K30U8.78823$uk2.31236905@twister.nyroc.rr.com... > > "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message > news:afq12k$g6f76$1@ID-84877.news.dfncis.de... > > "steve synakowski" <srs@twcny.rr.com> schrieb im Newsbeitrag > > news:P%ZT8.78662$uk2.31093590@twister.nyroc.rr.com... > > > > > Hi, I'm having one heck of a time trying to find out if I can daisy > chain > > > coolrunner XPLA3 CPLD's. > > > > What do you mean with "daisy chained"? > > I mean programming multiple parts on a board with one cable connection. > Usually the data gets clocked through all of them in a big loop on the data > line. > I know about the requirement for the configuration memory for FPGA, and that > CPLD's don't need that. > I was thinking that maybe the 'slave-serial' might have to do something with > the programming af the CPLD also, maybe it has to do with only the FPGA > memory. > Thanks > > > > > > Using impact 4.2WP0.x > > > I found this statement in the help. > > > Also, if so, is there any information on the configuration? I guess > > TDO-TDI, > > > and the rest in parallel? > > > > The JTAG port is just a JTAG port, which can be handled as such one. > > > > > -> I found this in the iMpact programming software help. > > > Slave-Serial mode is supported by all Xilinx FPGA families, but not > Xilinx > > > CPLDs. It uses an external clock and allows for daisy-chain > > configurations. > > > > CPLDs need no Configuration interface, since they are FLASH/EEPROM based. > > Once programmed (via JTAG), they keep their configuration also after > > power-off. > > > > -- > > MfG > > Falk > > > > > > > > > >Article: 44801
Yes.
Connect the TDO to TDI of the next device in the chain. TCK and TMS of all
devices get wired in parallel.
steve synakowski wrote:
> Hi, I'm having one heck of a time trying to find out if I can daisy chain
> coolrunner XPLA3 CPLD's.
> Using impact 4.2WP0.x
> I found this statement in the help.
> Also, if so, is there any information on the configuration? I guess TDO-TDI,
> and the rest in parallel?
>
> -> I found this in the iMpact programming software help.
> Slave-Serial mode is supported by all Xilinx FPGA families, but not Xilinx
> CPLDs. It uses an external clock and allows for daisy-chain configurations.
>
> Thanks,
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 448022 board layouts: 1st layout is all 3.3v. 2nd layout has one bank of the Virtex-E at 2.5v. 2nd layout has the xilinx design obufs changed to LVCMOS2 in the bank that is powered by 2.5v. Question: If I loaded design #2's bit file into design #1 will I dammage the virtex chip? (because the 2.5v bank of LVCMOS2 obuf's is really powered by 3.3v). All signal inputs are 3.3v or less. Thanks DanArticle: 44803
Dan, No, you will not damage the chip. The IOB bits control the strength of the IO driver. So at 2.5V for a 8 mA fast driver, there are more transistors turned on than for the same 8 mA fast driver fro 3.3V. Thus, a board designed for 3.3V with programming for 2.5V buffers will have a weaker drive strength than the correct driver type, and for a board with 2.5V IO bank power, with 3.3V driver IOB types, the strength will be stronger than expected. No damage results in either case from the bitstream. Austin Dan Kuechle wrote: > 2 board layouts: 1st layout is all 3.3v. 2nd layout has one bank of the > Virtex-E at 2.5v. > 2nd layout has the xilinx design obufs changed to LVCMOS2 in the bank that > is powered by 2.5v. > Question: If I loaded design #2's bit file into design #1 will I dammage > the virtex chip? (because the > 2.5v bank of LVCMOS2 obuf's is really powered by 3.3v). All signal inputs > are 3.3v or less. > > Thanks > > DanArticle: 44804
Rick Filipkiewicz wrote: > > Kevin Neilson wrote: > > >>I know Xilinx says that they don't yet support XP, but I've been using it >>and have had no problems (other than those I would normally have). On the >>contrary, I'm much happier, because instead of rebooting ~6 times per day on >>ME I'm rebooting once every six days. >>-Kevin >> > > > You mean MS have got a third of the way back to where they were with NT4+SP6A ? > > It makes me want to scream derision every time I see ``Built on NT technology'' > in the Win2K banner. Well, what do you do with foundations ? You pound them into the ground until no-one knows they are there! SimonArticle: 44805
Austin Lesea wrote: > John, > > To emphasize Peter's point (below), > > How good are your simulation test vectors? > > Where we find inaccuracy, we find lack of vectors. > We (members of the XPower team at Xilinx) go round'n'round on this topic. I have often been asked "isn't there a simple answer to whether my simulation-generated VCD file will yield accurate results when used with XPower?" Like most things with engineering, there is a simple, elegant, and wrong answer ;-) Only the logic designer knows if the stimulus generated by this testfixture accurately reflects how the device will be stimulated in the real-world (and as a former logic designer, I know that even designers sometimes don't know the answer). In addition, it is important to run the simulation long enough that the I/O frequencies captured are reasonably accurate. In other words, if XPower says that your power-on-reset toggled at 1MHz, you didn't simulate long enough... The flip side is running too long of a simulation yields an excessive amount of data. Judgement call... My personal rule-of-thumb is to look at the clock frequency reported in XPower after loading a VCD file. If it is within 1% of the actual clock speed, I'm generally happy. -Dennis McCrohan Xilinx CPLD S/W > > Austin > > John Blaine wrote: > > > Steven > > > > No they are not worst case. > > > > John > > > > Steven Derrien wrote: > > > > > Matthias Neuroth wrote: > > > > > > > > Steven, > > > > > > > > the accuracy level is dependent on the qualifier status. For the > > > > upcoming software release (5.1i), you can expect the following levels > > > > > > > > * ±10% for Spartan-II, Virtex and Virtex-E parts > > > > * ±20% for Spartan-IIe and Virtex-II parts > > > > > > > > Please keep in mind that the accuracy of the tool depends on a number of > > > > important factors. Some of these, for example activity settings data, > > > > have to be supplied by the user (guess, simulation data, etc). > > > > > > Are these worst case numbers ? > > > > > > Thanks, > > > > > > Steven derrien > > > > > > > > > > > Matthias Neuroth > > > > > > > > Steven Derrien wrote: > > > > > > > > > Hi, > > > > > > > > > > Since my last post did not get any answer, and before I give up > > > > > I decided to try again .. > > > > > > > > > > Are there any benchmark/figure/data regarding the accuracy of the > > > > > Xpower tool ? > > > > > > > > > > Steven DerrienArticle: 44806
In XAPP622 in the verilog source file tx_sdr_16d_4to1.v there is the following line included with the familiar RLOC attributes:
// set_attribute w_LR2 ROUTE "{1;1;-5!-1;15264;2296;14;21;23;32;13!0;-2695;456;24!1;2368;-888;0!2;327;0;4;21;22;20!}" -type string
Where can I find info on this ROUTE attribute and where do I extract the route "numbers" like above?
Thanks, Doug
Article: 44807--------------D3537BF88239958FAB1EE040 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit If you are interested in related details, click on XAPP622 http://www.xilinx.com/xapp/xapp622.pdf Peter Alfke ================================ Peter Alfke wrote: > Here is an even better answer from one of the Xilinx experts ( who wants to remain > anonymous...) > > I think the best thing to do is : > > CLK--+--DCM-----BUFG---internal clock > | > +--DCM-----BUFG---to FDDRRSE primitive(s) > > The top DCM and BUFG are used for the internal clock. The bottom DCM > and BUFG are used to drive FDDRRSE primitives. Each BUFG feeds back > to it's own DCM. The bottom BUFG can also then be phase-adjusted to > move the clock where he needs it. By connecting the D0 and D1 inputs > to the FDDRRSE primitives to VCC and GND (or vice-versa), you will > get an exact copy of the clock, or it's inverse (180 degree phase > shift). Of course, there will be the clock-to-out delay of the IOB > DDR flop, but that can be adjusted/corrected with the phase shift > of the bottom DCM that drives these IOB flops. > > There will be a slightly better duty cycle if two BUFGs are used > with the bottom DCM -- one for CLK0 and one for CLK180 vs. the > single BUFG method that I described above. > > Peter Alfke wrote: > > > You don't need two DCMs, one is enough. It generates the two phases (0 and 180 ) with > > as good a precision as is possible ( 50 ps resolution). Then you can route these > > signals on two glabal clocks. > > Thiis more accurate than doing local inversion in ths I/O. > > > > Peter Alfke, Xilinx Applications > > ======================== > > JArticle: 44808
Hi Everyone,
I inherited a design from a previous engineer which was in an Altera
10KE part. The new board has a VirtexE part.
I have the Altera FPGA design, but when i try and replace the dual
port block RAM in Altera (namely altdpram) with the RAM generated by
Xilinx core generator, the design does not work on the new board.
I was wondering if there is a way to convert Altera's block RAM as a
functionally equivalent Xilinx block RAM.
An early reply would be highly appreciated.
Thanks,
Searcher of Knowledge
o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o
The parameters passed to MaxPlusII are the following
-----------------------------------------------------------------------
module dual_port_ram2 (data, rdaddress, wraddress, wren, inclock,
rden, outclock, aclr, q)
/* synthesis black_box
WIDTH = 16
WIDTHAD = 8
LPM_TYPE="altdpram" */;
-----------------------------------------------------------------------
Article: 44809As far as I know, the Altera 10K device has a "so-called" dual-port RAM, with one port being write, the other one being read. (Sufficient in many, but not all cases). The Xilinx Virtex families have a true dual-port RAM, where either port can be read or write, so you can even have two write or two read ports. Of course, you don't need this. Functionally, the Virtex BlockRAM is a superset of the Altera RAM ( although make sure that read is a synchronous, clocked operation. I don't know Altera well enough to compare). Maybe it's just a question of nomenclature... Peter Alfke, Xilnx Applications =================== Search for knowledge wrote: > Hi Everyone, > > I inherited a design from a previous engineer which was in an Altera > 10KE part. The new board has a VirtexE part. > > I have the Altera FPGA design, but when i try and replace the dual > port block RAM in Altera (namely altdpram) with the RAM generated by > Xilinx core generator, the design does not work on the new board. > > I was wondering if there is a way to convert Altera's block RAM as a > functionally equivalent Xilinx block RAM. > > An early reply would be highly appreciated. > > Thanks, > Searcher of Knowledge > > o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o > > The parameters passed to MaxPlusII are the following > ----------------------------------------------------------------------- > module dual_port_ram2 (data, rdaddress, wraddress, wren, inclock, > rden, outclock, aclr, q) > /* synthesis black_box > WIDTH = 16 > WIDTHAD = 8 > LPM_TYPE="altdpram" */; > > -----------------------------------------------------------------------Article: 44810
IIRC, the Xilinx RAM returns the data one clock earlier than the Altera stuff does. You can check the simulation models to see. If true, all you have to do is latch the output data. On 1 Jul 2002 19:59:48 -0700, hell_o_the_re@yahoo.com (Search for knowledge) wrote: >Hi Everyone, > >I inherited a design from a previous engineer which was in an Altera >10KE part. The new board has a VirtexE part. > >I have the Altera FPGA design, but when i try and replace the dual >port block RAM in Altera (namely altdpram) with the RAM generated by >Xilinx core generator, the design does not work on the new board. > >I was wondering if there is a way to convert Altera's block RAM as a >functionally equivalent Xilinx block RAM. > >An early reply would be highly appreciated. > >Thanks, >Searcher of Knowledge > >o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o > >The parameters passed to MaxPlusII are the following >----------------------------------------------------------------------- >module dual_port_ram2 (data, rdaddress, wraddress, wren, inclock, > rden, outclock, aclr, q) >/* synthesis black_box > WIDTH = 16 > WIDTHAD = 8 > LPM_TYPE="altdpram" */; > >-----------------------------------------------------------------------Article: 44811
Based on the responses you've gotten so far, there is a lot of
misinformation out there.
The Altera 10KE ESB is a 4K bit memory that can be configured as 256 x 16,
512 x 8, 1k x 4 or 2k x 2. It has separate read and write addresses so
that you can do dual port (one read, one write) access to two different
locations. The inputs and outputs may be registered or non-registered
The Xilinx BRAM is also 4K bits, but it is true dual port (both ports
independently support read and write, so you can simultaneously write both
ports, for example), it can be configured as 4Kx1 to 256x16, and it is
synchronous only.
If the Altera design is using the ESB memory with one of either the data
output or the read address registered, then it can be directly replaced
with the xilinx BRAM. If it is being used in an unregistered
configuration, then you will need to modify your design to accommodate the
1 clock latency inherent in the Xilinx BRAM read.
Search for knowledge wrote:
> Hi Everyone,
>
> I inherited a design from a previous engineer which was in an Altera
> 10KE part. The new board has a VirtexE part.
>
> I have the Altera FPGA design, but when i try and replace the dual
> port block RAM in Altera (namely altdpram) with the RAM generated by
> Xilinx core generator, the design does not work on the new board.
>
> I was wondering if there is a way to convert Altera's block RAM as a
> functionally equivalent Xilinx block RAM.
>
> An early reply would be highly appreciated.
>
> Thanks,
> Searcher of Knowledge
>
> o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o-o
>
> The parameters passed to MaxPlusII are the following
> -----------------------------------------------------------------------
> module dual_port_ram2 (data, rdaddress, wraddress, wren, inclock,
> rden, outclock, aclr, q)
> /* synthesis black_box
> WIDTH = 16
> WIDTHAD = 8
> LPM_TYPE="altdpram" */;
>
> -----------------------------------------------------------------------
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44812Hello! Has anyone done allready VHDL source to get PC's LPT (EPP,ECP) as a bidirectional control "bus" ? or has anyone seen that kind of link to web? thank you, esko finlandArticle: 44813
Hi, i am using the Synario 4.1 compiler for a target GAL chip in VHDL code. I am facing a rather strange problem. Synaio does not seem to recognise the std_logic_unsigned package. it keeps giving a 'the following variable has not been declared' compilation error. i ran the same code in Max Plus and it works well. Could anyone give any suggestions on this..? do the Synopsys libraries (of which std_logic_unsigned is a part of) need to be imported into Synario? if so how? any other suggestions please? Many thanks in advance Cheers, SandeepArticle: 44814
I think it's time for me to jump in and clear up misunderstandings and/or stupidities on our side. If anybody has to download 100 MB, that is a lousy proposition at any modem speed. And, yes, 56kbits/sec = 7kB/s, and it would take at best 20,000 seconds, which is six hours. I think most of us can do the math, but somebody must have been asleep at the wheel... Peter Alfke, Xilinx Applications ================================ Rick Filipkiewicz wrote: > rickman wrote: > > > 113 MB!!! That will take about 13 hours on my connection, assuming that > > it completes which it often won't with such a large file. The last time > > I did this it took nearly a week of trying to get it to download. > > > > Why the heck doesn't Xilinx make it available on CD for $10 or so. > > Netscape does it. What's the problem? Are they concerned that users > > will expect to get support for their $10? > > > > > > The WebPACK site has some interesting ideas about download times. As an example > they claim that a 142MB will take 56min over a 56K line. If anyone posseses such a > line please let me know the Telco's address, otherwise methinks someone should > take them aside and point out that in the strings "Kb/sec." and "KB/sec." the case > is significant ... once this difference is grasped CDs might become available. > > Its even worse on this benighted side of the pond where local calls aren't free.Article: 44815
Dennis McCrohan wrote: > Austin Lesea wrote: > > > John, > > > > To emphasize Peter's point (below), > > > > How good are your simulation test vectors? > > > > Where we find inaccuracy, we find lack of vectors. > > > > We (members of the XPower team at Xilinx) go round'n'round on this topic. I have > often been asked "isn't there a simple answer to whether my simulation-generated > VCD file will yield accurate results when used with XPower?" > > Like most things with engineering, there is a simple, elegant, and wrong answer > ;-) > > Only the logic designer knows if the stimulus generated by this testfixture > accurately reflects how the device will be stimulated in the real-world (and as a > former logic designer, I know that even designers sometimes don't know the > answer). In addition, it is important to run the simulation long enough that the > I/O frequencies captured are reasonably accurate. In other words, if XPower says > that your power-on-reset toggled at 1MHz, you didn't simulate long enough... The > flip side is running too long of a simulation yields an excessive amount of data. > Judgement call... My personal rule-of-thumb is to look at the clock frequency > reported in XPower after loading a VCD file. If it is within 1% of the actual > clock speed, I'm generally happy. > > -Dennis McCrohan > Xilinx CPLD S/W > Its all very well, and completely correct, to say that realistic sim runs are needed to provide enough raw data for Xpower to get an accurate estimate. The problem comes when realistic = long => **huge** VCD files. Hearing reports that Xpower takes forever to load these sometimes enormous VCD files, assuming it doesn't crash on the way, is basically putting me off using it. [Defn. humungous = size of VCD file produced by 2msec post-route sim of XCV600E @ 90%). While the antique VCD format has the clear merit of portability it is, IMV, clearly inappropriate in this contex since for power calc. purposes we need to dump all nodes and not just a small subset to pipe through a VCD waveform viewer. A patch solution might be a Perl script that extracts required info from the VCD and outputs a simple binary file (with a defined format) containing just the toggle count per node and node type. That way I could run the extractor on a machine with decent virtual memory performance - aka a Unix box [according to my O/S guru colleague even Linux isn't really good enough for this yet].Article: 44816
Hi, with this, leonardo does not remove equivalent DFF in my design : copy this line in the entity declaration : attribute preserve_driver :boolean; copy this line in your vhdl code beetween architecture and begin : attribute preserve_driver of YOUR_SIGNAL:signal is true ; "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> a écrit dans le message news: afpoml$121$1@newsreader.mailgate.org... > > > Nicolas Matringe wrote: > > > > > > Hi > > You can set the preserve_driver attribute > > I used it to prevent LS from removing intentionnally duplicated logic and it > > worked fine. > > Look in the manual for the exact syntax in VHDL or Verilog > > > > > I used the preserve_driver attribute, but LeonardoSpectrum still > merged equivalent (parallel) FFs into one FF which I don't want it to do > that. > Does LeonardoSpectrum even have a synthesis keyword that prevents > equivalent FF removal? > > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 44817
Hello, Is there any tool to calculate the dynamic power consumtion of FPGAs? I mean, something that would actually simulated the gate level, post place and route design AND calculate the power consumtion at each simulation step? If yes, does such a tool take into account the physical parameters of different packages and ultimately give an estimate of die(junction) and case trempreates? Actually I was thinking of such a tool, by inserting specific information about power consumtion to LUT and other primitives model into the VITAL models for them and then running the simulation and summing up the numbers in each simulation step and... Regards ArashArticle: 44818
I had to put these commands in my vhdl source (it 's working) : attribute preserve_signal : boolean; attribute preserve_signal of SIGNAL_NAME : signal is true; I don't know the equivalent for verilog. bye Kevin Brace wrote: Kevin Brace wrote: > Nicolas Matringe wrote: > > > > > > Hi > > You can set the preserve_driver attribute > > I used it to prevent LS from removing intentionnally duplicated logic and it > > worked fine. > > Look in the manual for the exact syntax in VHDL or Verilog > > > > I used the preserve_driver attribute, but LeonardoSpectrum still > merged equivalent (parallel) FFs into one FF which I don't want it to do > that. > Does LeonardoSpectrum even have a synthesis keyword that prevents > equivalent FF removal? > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.)Article: 44819
"Arash Salarian" <arash.salarian@epfl.ch> wrote in message news:3d216c7b$1@epflnews.epfl.ch... > Hello, > > Is there any tool to calculate the dynamic power consumtion of FPGAs? I > mean, something that would actually simulated the gate level, post place and > route design AND calculate the power consumtion at each simulation step? If > yes, does such a tool take into account the physical parameters of different > packages and ultimately give an estimate of die(junction) and case > trempreates? > > Actually I was thinking of such a tool, by inserting specific information > about power consumtion to LUT and other primitives model into the VITAL > models for them and then running the simulation and summing up the numbers > in each simulation step and... > > > Regards > Arash > Usually I don't answer my own posts... ;) just wanted to say by forgetting to run my spell checker, my last post has tremendous spelling errors :) sorry....Article: 44820
Dear Community! In my application I need to let the FPGA communicate with the PC. (I want to write a small C++ program where you can enter some values) The demo board I use offers an serial RS-232 port but only with TXin and RXout pins. So I suppose I must use some software handshake? And i have to implement a serial/parallel converter within the FPGA (vhdl code?). Does anyone have an idea how to match these requests? Thank you, ThomasArticle: 44821
Hello I have a problem. Is it possible to reconfigure VIRTEX, VITREXE or VIRTEX-II devices with bitstream which I got in earlier readback process? In other words I have to start my design working from the state, before cold power down (without power supply). Is it any way to restore known states of all registers of FPGA? Best regards, Christopher Szczepanski Alatek tel +48 58 3485484Article: 44822
I need to power a single Virtex-II device. Can anyone recommend a small footprint 1.5V DC to DC converter ? I would prefer 3.3V input voltage, although I could use 5V.Article: 44823
Hello Arash, the tool which functionality you describe is available. It's called XPower and takes in the implemented design and if you want a *.vcs-file (I think that's the extension) with simulation data from e.g. Modelsim. With that tool you can very accurately predict how much power your design is going to use. The tool comes as part of ISE and WebPack and you'll find it in the P&R section of the 'Implement Design' Part in the Project Navigator. MartinArticle: 44824
On Mon, 1 Jul 2002 15:56:17 -0700, "Doug Wilson" <doug_wilson@3mtsNOSPAM.com>
wrote:
>In XAPP622 in the verilog source file tx_sdr_16d_4to1.v there is the following line included with the familiar RLOC attributes:
>
>// set_attribute w_LR2 ROUTE "{1;1;-5!-1;15264;2296;14;21;23;32;13!0;-2695;456;24!1;2368;-888;0!2;327;0;4;21;22;20!}" -type string
>
>Where can I find info on this ROUTE attribute and where do I extract the route "numbers" like above?
>
>Thanks, Doug
The directed routing constraints are created in the FPGA editor.
Start the FPGA editor, and load a routed design.
Select tools -> Directed Route Cst
Select the net(s) with the filter, and the scroll box below it
Specify a constraint file (for the output)
Apply.
Go look at the constraint file you have written.
This stuff should be able to be pasted into a UCF file, or
embedded in your code as shown in XAPP 622.
I dont believe that this constraint is covered in the documentation.
You can also create an empty design in the FPGA editor, and then
create logic, and do hand placement and hand routing. You can then
in a similar way to the above description, write out the routing
constraint.
Philip Freidin
Philip Freidin
Fliptronics
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