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Frank wrote: > Hello, > > I am designing a very bare-bones development board using Altera ACEX > fpga's > (EP1K10, EP1K30, and EP1K50) and EPC2 configuration memory. There will > be a couple of push-buttons and LED's. I will use a 4-wire JTAG interface > to > program the memory and/or fpga. I am hoping to find a schematic design to > compare with my work. Before sending the PCB design out, I'd like to be > sure > that I've not overlooked any needed connections. Looking at another > design may > also alert me to features that could enhance the functionality of the > board without > materially increasing its complexity. > > I would appreciate links to such designs. I am NOT interested in designs > whose > developers would consider dissemination of such information as theft of > intellectual > property. > We use a development board designed in-house that is basically just the ACEX chip, an epc2, a byteblaster programming header, a couple of voltage regulators and a crystal, with the I/Os broken out to 0.1" headers. The board fits into a bread board, and is great for prototyping our designs. Of course, our design is very low speed (our usual clock frequency is 10MHz, one design is 40MHz); your requirements might be different. The circuit design was pretty much lifted straight off an earlier design we did using the flex10k parts, which I'm pretty sure was in turn lifted straight off an Altera app note. Email my work address (matt.vandewerken at csiro dot au) and I'll send you a pdf of the schematic with the EPLD on it. As I said, it's not terribly difficult, and I wouldn't even consider the schematic to be our own property (given it was taken straight from an Altera app note). Cheers, MvdWArticle: 43326
Tim wrote: > I theory this is very straightforward, so I knocked together > a quick Windows program with the MS TreeView control. Really > amusing timing. The program could read and (sort of) parse a > multi-megabyte EDIF file in a few seconds, but the TreeView > took absolutely ages to build and draw. > > I guess Micro$oft designed their control to display a few hundred > files, not a million or so EDIF nodes. Then they delegated the > programming of the control to someone who slept through the data > structures class. > > Good luck with the hunt. Pls post if you find something. > Hi Tim: If you could mail me the source code of what you've done, I could have a go at optimising the routine with some sort of double-buffering of the tree view and the actual data structure. My problem is that I don't know enough about EDIF to write a parser, but I don't think I'd have too much trouble with the viewing code. Cheers, MvdWArticle: 43327
Traveler wrote: > > In article <3CE46EE1.79BD05C@yahoo.com>, rickman > <spamgoeshere4@yahoo.com> wrote: > > >But the trick to it all is to define what you need in terms of > >arithmetic or logic functions. Can you do that, or will you need help? > > I appreciate your help but I don't see the relevance of going into > arithmetic or logic functions. What I really want to find out is > whether or not it is feasible to use FPGA to implement a cellular > system that can be programmed to make (or break) an indefinite number > of connections to multiple cells on the fly. I have already read > reports of FPGAs being used to implement neurons with a fixed number > of connections. My neurons do not have on-off states. They send a > 1-bit signal to other neurons when their input conditions are > satisfied. > > Temporal Intelligence: > http://home1.gte.net/res02khr/AI/Temporal_Intelligence.htm If you intend for the interconnect to be equivalent to an AND gate, then there are several ways to implement this. Implementing several hundred AND gates can be done using several hundred logic blocks or by time multiplexing a single AND gate with all the inputs. A large FPGA can implement a huge number of neurons each with a large number of inputs and yes, those inputs can be programmable. The trick is to map these operations to the logic in an efficient way. Efficient mapping in your application depends on the complexity of the interconnect functions (the AND gate, not very complex) and the neuron itself (no info on this since you don't feel we need to know that). Ignoring the issue of the neuron structure itself, the interconnect can be time multiplexed to prevent duplication of the AND gate. The block ram allows the controlling element of many neuron inputs to be held in a single element and selected through the address lines. Now the output will be time multiplexed and the only remaining feat is to time multiplex the input. If your neuron states are time multiplexed, they can be stored in a block ram as well. The neuron block ram can read out in the appropriate sequence to feed the neuron input selector. This is not a trivial design to tackle, even at a block diagram level, unless you understand how the various logic elements operate and how the various functional block operate. We understand how the logic element operate and you understand what your functional elements are. To architect this further we would need to understand better how the neurons operate. To give you an idea of the limitations of a block ram approach, each RAM has 16 kbits. This can implement about 80 sets of neuron inputs at 200 each. There are 168 block rams in the largest Virtex II for 13,440 maximum neurons if the block rams are only used for neuron inputs. Using an external memory will get around this limitation. So how do you plan to implement the neurons? This will make a big difference. It will help if you can describe the neurons in logic terms rather than functional terms that will need to be translated to logic. For example, I don't know what "input conditions are satisfied" means in terms of logic. Is this a count of inputs at a logic '1' being above a threshold? Or is it an AND gate for all inputs? Or is it a certain pattern on the inputs? Finally, what is the input and output from this neuron array? Also how do you plan to alter the interconnect "on the fly"? The nature of the alteration makes a BIG difference to how you implement it. Do the neuron outputs alter the interconnects? Or does some external process alter the interconnects? How much time can be used to make the changes. Can the neuron processing be stopped while the interconnects are changed? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43328
amolitor-at@visi-dot-com.com wrote: > > In article <3CE59DCF.6DEF0AB@ieee.org>, Jerry Avins <jya@ieee.org> wrote: > > [ re, rickman ] > >For the record, Andy, he _is_ his employer. > > Now that I actually look at the gentleman's signature, > I have a horrible suspicion he could teach me a thing or two about > winkling parts outta distribution. > > My apologies! Didn't mean to come off condescending. That's ok. I am not trying to find a few parts for prototypes since I would not sweat the cost on that. I am trying to make product decisions that will select the parts to be used in future production. I don't want to design in SDRAM that is still on the expensive side of the price curve, but I don't want to limit the memory size for the next four years either. I am finding that distribution is giving me prices that are rather high compared to what I expect to find given the current price of SDRAM modules for PCs. I am assuming that there are other avenues for buying SDRAM and I just don't know what they are. I am always willing to learn... :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43329
Herman Oosthuysen wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3CE57484.D9777F38@yahoo.com>... > > Matt H wrote: > > > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > > news:3CE54C57.E05567F8@yahoo.com... > > > > I am seeing the price of 256 Mbit SDRAM at about $20 to $25. This is > > > > about 8 times what it costs for the same amount of memory on DIMMs. I > > > > know that quantity makes a difference, but I can buy a single 256 MByte > > > > DIMM for $22 or I can buy 1k 32 MByte SDRAM chips at $20 each. This > > > > seems very excessive. > > > > > > > > Anyone getting better pricing on 16x16 SDRAM? > > > > > > > > > > > > -- > > > > > > > > Rick "rickman" Collins > > > > > > > > rick.collins@XYarius.com > > > > > > Hi Rick, > > > Check out this community: > > > http://www.dramexchange.com/default.asp > > > It looks like the current price for 16x16 is about $8. Perhaps you can find > > > a better price. > > > Good Luck, > > > Matt > > > > Interesting web site, but these prices are largely irrelevant. None of > > this is open to me to purchase. Even after I register, I don't see a > > way to buy. I expect these prices are for very large orders. > > Unless you are a large buyer, you are hooped. In my experience, an > Asian factory can get stuff at half the price we are quoted for 10,000 > quantities! > > Cheers, > > Herman > http://www.AerospaceSoftware.com I am finding that. I just strikes me as odd that I can buy exactly one memory module at a quarter or even an eighth of what the equivalent SDRAM chips will cost me if I buy 1000 of them. But then electronic purchasing has never been logical.. :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43330
In article <3CE71458.CB8FC6F5@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >I am finding that distribution is giving me prices that are rather high >compared to what I expect to find given the current price of SDRAM >modules for PCs. I am assuming that there are other avenues for buying >SDRAM and I just don't know what they are. I think we're finding that SDRAM is something like 2x the DIMM prices if you want bare chips, for 100ish quantities. We also find a lot of datasheet and very little silicon for ANYTHING except the stuff that goes on DIMMs (i.e. PC133). Our parts guy is a card carrying member of the parts mafia, too. He comes up with stuff I don't WANNA know how :) If you're way under 2x, I'd love to hear how you're doing it, and if you're way over 2x, I'd be happy to ask my guy where the heck he's getting the stuff. We might be way over 2x as well, but my impression is it's under.Article: 43331
Ray Andraka <ray@andraka.com> wrote in message news:<3CE676B1.824F699@andraka.com>... > My apologies if this does indeed work in 4.2... I got the .ucf text method to work on a hierarchy:) The syntax is a bit finicky.Article: 43332
Kevin Brace wrote: > Ray Andraka wrote: > > > > While I don't know if this the case here, a good reason for an encrypted netlist > > is to protect IP. The open format of the EDIF netlist with no means of > > encrypting it is a major hindrance to those wishing to sell IP. > > > > Because it is so easy to convert an EDIF netlist to an encrypted > .NGO file in Xilinx's software, I have been thinking of licensing > (selling) my PCI IP core as an encrypted netlist when it is done. > However, does anyone know how I can do something similar in Altera's > tools? > LeonardoSpectrum-Altera generates an EDIF file, which is fine, but it > will be nice if I can somehow encrypt it. > Speaking of protecting IP cores, even a .NGO file is probably > not terribly safe considering that someone who doesn't want to pay for > it can easily get a copy from someone else. > I suppose the only value of a .NGO file is to prevent an FPGA-to-ASIC > conversion by companies like Lightspeed Semiconductor or AMI > Semiconductor. > However, in Altera's IP core program, I believe the user has to buy > (license) a key to program their devices, so just getting a copy of an > encrypted netlist from someone will probably not do any good. > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) So in summary to protect IP o Xilinx's: Let CoreGen produce .ngc files. o One's own: Ship .ngo files for integration with customer's code and the obfuscated output of NGD2<VER | VHDL> for evaluation simulation. In neither case does this require XST to produce encrypted binary files in normal use.Article: 43333
Rick Filipkiewicz wrote:
>
>
> So in summary to protect IP
>
> o Xilinx's: Let CoreGen produce .ngc files.
>
> o One's own: Ship .ngo files for integration with customer's code and the obfuscated
> output of NGD2<VER | VHDL> for evaluation simulation.
>
> In neither case does this require XST to produce encrypted binary files in normal use.
I totally agree.
XST has nothing to do with IP cores, so I wish Xilinx will leave my
design alone.
It is none of their business to encrypt my design unless I want it to by
using EDIF2NGD.
Anyhow, probably Xilinx has a utility in-house that converts an NGC file
to an EDIF file, but I am sure they will never release such a utility.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 43334
cfk wrote:
> I have a board with a VirtexE on it and with amongst other things, a button
> (call it USER_IN) and three leds (call then LED[2:0]) controlled by a
> variable lstate. I want to create a modest state machine so that I
> initialize lstate to 3'b000, and then with each button push, I move to
> 3'b001..3'b111 and then back to 3'b000. I tried the following:
>
> always @(posedge clk and USER_IN)
> begin
> lstate = lstate + 1;
> end
>
> But what seems to happen is the states are cycling through at clk speed. The
> reason I could not use (posedge clk and posedge USER_IN) is then the Xilinx
> ISE wants to assign USER_IN to a clock pin and I cannot implement the
> design. Maybe this issue is my understanding of ISE and Verilog as I am
> officially a newbie at this time.
>
> Next I tried
>
> always @(posedge clk and USER_IN)
> begin: ledstater
> reg lstate_toggle;
> if(USER_IN & lstate)
> begin
> lstate_toggle = !lstate_toggle;
> lstate = lstate + 1;
> end
> end
>
> This one doesn't seem to do anything to the LED's (which are set with a
> seperate assign statement). So, any suggestions would be greatly
> appreciated.
>
> Charles
What Ray said about needing to debounce switches is dead right. I'd like to add
this though:
1. What synthesis tool are you using that accepts the construct:
always @(posedge clk and USER_IN)
...
!?? Its not legal Verilog and both Synplify (synth tool) and ModelSim
(simulator) barf over it.
[Maybe its a Verilog-2001ism ?]
2. When writing code that is supposed to synthesise to FFs you should always use
the non-blocking assign `<=' and not the blocking one `='. Its really important
that, as a self-confessed newbie, you understand the difference between these
i.e. how the simulator treats them.
3. Even if USER_IN didn't bounce all over the place and you were to re-write the
code as legal Verilog (it still wouldn't work but at least the tools wouldn't
complain):
wire gate_clk = clk & USER_IN;
always @(posedge gate_clk)
lstate <= lstate + 1;
what you would have is a gated clock. Its possible to get this right (I had to
do one many years ago in the PAL era, I had no choice, and there's a famous
Peter Alfke apps note on the Xilinx web site) but in general its considered a
big no-no.
Article: 43335rickman wrote: > > Traveler wrote: > > > > In article <3CE46EE1.79BD05C@yahoo.com>, rickman > > <spamgoeshere4@yahoo.com> wrote: > > > > >But the trick to it all is to define what you need in terms of > > >arithmetic or logic functions. Can you do that, or will you need help? > > > > I appreciate your help but I don't see the relevance of going into > > arithmetic or logic functions. What I really want to find out is > > whether or not it is feasible to use FPGA to implement a cellular > > system that can be programmed to make (or break) an indefinite number > > of connections to multiple cells on the fly. I have already read > > reports of FPGAs being used to implement neurons with a fixed number > > of connections. My neurons do not have on-off states. They send a > > 1-bit signal to other neurons when their input conditions are > > satisfied. > > > > Temporal Intelligence: > > http://home1.gte.net/res02khr/AI/Temporal_Intelligence.htm > > If you intend for the interconnect to be equivalent to an AND gate, then > there are several ways to implement this. Implementing several hundred > AND gates can be done using several hundred logic blocks or by time > multiplexing a single AND gate with all the inputs. ... > Ignoring the issue of the neuron structure itself, the interconnect can > be time multiplexed to prevent duplication of the AND gate. The block > ram allows the controlling element of many neuron inputs to be held in a > single element and selected through the address lines. Now the output > will be time multiplexed and the only remaining feat is to time > multiplex the input. If your neuron states are time multiplexed, they > can be stored in a block ram as well. The neuron block ram can read out > in the appropriate sequence to feed the neuron input selector. This is > not a trivial design to tackle, even at a block diagram level, unless > you understand how the various logic elements operate and how the > various functional block operate. We understand how the logic element > operate and you understand what your functional elements are. To > architect this further we would need to understand better how the > neurons operate. > > To give you an idea of the limitations of a block ram approach, each RAM > has 16 kbits. This can implement about 80 sets of neuron inputs at 200 > each. There are 168 block rams in the largest Virtex II for 13,440 > maximum neurons if the block rams are only used for neuron inputs. > Using an external memory will get around this limitation. > > So how do you plan to implement the neurons? This will make a big > difference. It will help if you can describe the neurons in logic terms > rather than functional terms that will need to be translated to logic. > For example, I don't know what "input conditions are satisfied" means in > terms of logic. Is this a count of inputs at a logic '1' being above a > threshold? Or is it an AND gate for all inputs? Or is it a certain > pattern on the inputs? It sounds like he's trying to model a biological-style neural network where it's not so much an 'AND' gate as how many pulses are received within a given time frame, or what the pattern of the pulses are as they arrive. This is supposed to be more like how the brain works - information can stored in the temporal nature of the signal. If this is the case, he's going to need RAM (to store a count or pattern), and an adder or (shifter & comparator) accessible by each neuron. He also needs a way to map the connectivity between neurons - treating them as an address gives you the problem of storing 200 18-bit numbers per neuron (treat an address of '0' as 'no-signal-out'), as well as the current state of each neuron. I think he'll need a chunk of external RAM, maybe using the blockram as cache, or he'll saturate even the fastest RAM. Maybe it would be best to set up several banks of external RAM - there's enough pins coming out of these FPGA's :-) If he wants to store the state in RAM, and have a single node time-multiplex the process, I think he'd find it slow. Worst case would be 200,000[neurons] * 200[connections]* 2[read/write] updates to RAM. Even with single-cycle RAM that makes it 80 million cycles, probably do-able in ~ 1sec (assuming an 80MHz clock). He has a 1ms timebase. This ignores reading info to and from the FPGA to the host because we're doing all the processing on the FPGA. So, you need ~1000 neurons within the FPGA. I don't know how big "the largest Virtex-2" device is (pretty bloody huge, probably :-) but I would have thought you'd be able to get 1000 fairly-simple logic circuits into it. On the other hand, it's going to be a pretty expensive system to design (tool-cost or consultancy), buy (big FPGA's don't come cheap!), and make (God alone knows what the footprint of the larger FPGAs are, but it's bound to be BGA, yuck :-( One thing you won't get easily is 'an indefinate amount' of connections. Going from the software to the hardware (firmware? :-) world almost always results in choosing your compromises. There are hard limits on what you can stick into an FPGA, and you can't just 'add some RAM'... Oh yeah, one other thing I should mention: Rick knows a lot more about FPGA's than I do, so listen to him, not me :-) The only reason I'm responding is that I did a PhD in Neural Networks :-) SimonArticle: 43336
UCF will work on a hierarchy, but the UCF itself is flat. That means that everything in
the UCF has to have full hierarchical names. Ideally, there would be a hierarchical UCF
so that any components that are repeated in there only need the placement described
once. The UCF uses LOCs and RLOC_ORIGINs to absolutely place anything that is placed
within the UCF. There is no relative placement in a UCF.
russell wrote:
> Ray Andraka <ray@andraka.com> wrote in message news:<3CE676B1.824F699@andraka.com>...
> > My apologies if this does indeed work in 4.2...
>
> I got the .ucf text method to work on a hierarchy:)
> The syntax is a bit finicky.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43337
You can put the ROC in as an instantiated black box. For simulation it can be
used to initialize the design. It will persist through synthesis. The Xilinx PAR
will remove it without complaining
Stephanie McBader wrote:
> Thanks a lot for your suggestion, Sweir.
>
> I have had a look at the Xilinx website for more info on this - do you know if
> the ROC component is only used for simulation or can it be also used for
> synthesis?
>
> Regards,
>
> Stephanie McBader
> Researcher/Design Engineer
> NeuriCam S.p.A
> Via S M Maddalena 12
> 38100 Trento TN, Italy
> Tel: +39-0461-260552
> Fax: +39-0461-260617
>
> sweir wrote:
>
> > Stephanie,
> >
> > I think what you are trying to ask is:
> >
> > "How do I use the internal global reset in a design that does not have an
> > external reset pin?"
> >
> > If so, then all you need to do is instantiate the ROC ( reset on
> > configuration ) component in your design. You can connect that output to
> > RTL that has async reset logic.
> >
> > Regards,
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43338amolitor-at@visi-dot-com.com wrote: > > In article <3CE71458.CB8FC6F5@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >I am finding that distribution is giving me prices that are rather high > >compared to what I expect to find given the current price of SDRAM > >modules for PCs. I am assuming that there are other avenues for buying > >SDRAM and I just don't know what they are. > > I think we're finding that SDRAM is something like 2x the > DIMM prices if you want bare chips, for 100ish quantities. We > also find a lot of datasheet and very little silicon for ANYTHING > except the stuff that goes on DIMMs (i.e. PC133). > > Our parts guy is a card carrying member of the parts mafia, > too. He comes up with stuff I don't WANNA know how :) > > If you're way under 2x, I'd love to hear how you're > doing it, and if you're way over 2x, I'd be happy to ask my guy > where the heck he's getting the stuff. We might be way over 2x > as well, but my impression is it's under. I am way over 2x. I am finding prices of >$20 for 256 Mbit parts in a x16 config, regardless of speed. I can buy a 256 MByte DIMM for about $30. This is about 8x. I would love to know where to get cheaper SDRAM parts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43339
rickman wrote: > > I am way over 2x. I am finding prices of >$20 for 256 Mbit parts in a > x16 config, regardless of speed. I can buy a 256 MByte DIMM for about > $30. This is about 8x. I would love to know where to get cheaper SDRAM > parts. > > -- > Sounds like it would almost be cheaper to buy some DIMMs and get an assembly house to use their re-work tools to remove the individual SDRAMs.Article: 43340
Hello I have an distributed arithmetic design that uses a scaling accumulator. The Xilinx core generator produces an accumulator that shifts right by one bit before feeding back into the adder to affect a divide by two. In the process the lsb is simply thrown away. My application is sensitive to truncation errors. Is there a simple way to use the carry_in pin of the accumulator to implement a round instead of a truncation in the shifted feedback data? The input and output data of the accumlator is signed two's complement. -- Pete Dudley Arroyo Grande SystemsArticle: 43341
Ray Andraka wrote: > > UCF will work on a hierarchy, but the UCF itself is flat. That means that everything in > the UCF has to have full hierarchical names. Ideally, there would be a hierarchical UCF > so that any components that are repeated in there only need the placement described > once. From what i can see, the only .ucf that gets read is the one that belongs to the file being compiled. It would be good if all the .ucf files belonging to files lower in the hierarchy were read too. That way, macros created in lower level .ucf files could be instantiated in higher level .ucf files. > The UCF uses LOCs and RLOC_ORIGINs to absolutely place anything that is placed > within the UCF. There is no relative placement in a UCF. I'm not sure what you mean. I used *only* RLOCs on everything in the .ucf, and no placements in the vhdl source. When i open floorplanner, i can place these 'clumps' of components with the structure intact (well, almost, there seems to be a bug that makes the carry chains come unstuck...) > russell wrote: > > > Ray Andraka <ray@andraka.com> wrote in message news:<3CE676B1.824F699@andraka.com>... > > > My apologies if this does indeed work in 4.2... > > > > I got the .ucf text method to work on a hierarchy:) > > The syntax is a bit finicky.Article: 43342
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in message news:ac3lp3$mu4$2@newsreader.mailgate.org... > Another thing to consider is that Spartan-II is a lot faster than > XC4000XL. > It is a lot easier to meet 33MHz PCI's Tsu < 7ns with a Spartan-II. > Plus, Spartan-II has more LUTs than XC4000XL for the same amount of > money. Hi Kevin, For a target, tsu should not matter, as you should register all the PCI I/O in the IOBs. It is only for a master that you really need to use some of the signals raw, and I/O timing becomes an "issue". AustinArticle: 43343
Ray Andraka wrote: > > UCF will work on a hierarchy, but the UCF itself is flat. That means that everything in > the UCF has to have full hierarchical names. Ideally, there would be a hierarchical UCF > so that any components that are repeated in there only need the placement described > once. From what i can see, the only .ucf that gets read is the one that belongs to the file being compiled. It would be good if all the .ucf files belonging to files lower in the hierarchy were read too. That way, macros created in lower level .ucf files could be instantiated in higher level .ucf files. > The UCF uses LOCs and RLOC_ORIGINs to absolutely place anything that is placed > within the UCF. There is no relative placement in a UCF. I'm not sure what you mean. I used *only* RLOCs on everything in the .ucf, and no placements in the vhdl source. When i open floorplanner, i can place these 'clumps' of components with the structure intact (well, almost, there seems to be a bug that makes the carry chains come unstuck...). If i was to write the constraints from floorplanner, then i guess some LOCs will be added. > russell wrote: > > > Ray Andraka <ray@andraka.com> wrote in message news:<3CE676B1.824F699@andraka.com>... > > > My apologies if this does indeed work in 4.2... > > > > I got the .ucf text method to work on a hierarchy:) > > The syntax is a bit finicky.Article: 43344
Austin Franklin wrote:
>
>
> Hi Kevin,
>
> For a target, tsu should not matter, as you should register all the PCI I/O
> in the IOBs. It is only for a master that you really need to use some of
> the signals raw, and I/O timing becomes an "issue".
>
> Austin
Although I no longer have Tsu related timing issues in my PCI IP
core at least for 33MHz PCI, I believe even in a target only PCI
interface, some signals will have to used right off the PCI bus
unregistered.
The first example I can think of is, in a backoff state, the target will
have to reference an unregistered FRAME# to see if the initiator (bus
master) is ending the transaction.
The second example will be to compare the parity of AD[31:0] and
C/BE#[3:0] with PAR one clock cycle after an address phase.
The third example will be during a no-wait burst cycle where FRAME# will
have to be monitored every clock cycle to see if the transfer is ending.
In my implementation, other than address decode, I really don't use the
registered version of the PCI signals, but I can still easily meet Tsu <
7ns in a Spartan-II-5.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 43345Jim Granville wrote: > also for some ability to 'seed' the > P&R tools to deliberately use other resource : Easy, run different cost tables in PAR. -- Phil HaysArticle: 43346
Kevin Neilson wrote: > The Xilinx mapper reports total component usage (slices, BRAMs, DCMs, etc.), > but how do I get a breakdown on a per-module basis? > -Kevin No. This shall be synthesis function. But even not all the synthesizers produce this statistics. My recommendation is to write a script that processes synthesizer's project file, takes filename from the project file as input and runs synthesis and this way information of all modules can be dumped to a "statistics info file". I don't know the case for Leonardo, Ambit, but script method above is universal and must be used with any synthesis program. UtkuArticle: 43347
Hi: I want to know what's the advantage Altera and Xilinx over each other. Are their performance very different from each other? -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 770-7081 Fax: 779-1621 Email: qijun@okigrp.com.sgArticle: 43348
Both are look up table oriented. Xilinx uses more a strategy of sea of identical logic cells. Altera is more structured in local groups of logic cells that are interconnected on a higher level. Xilinx has a better approach for dual ported ram (dual port == dual port). But Altera blockram can be used as asynchronuous RAM, Xilinx blockram is only synchronuous. There are a lot more differences, but these are the most important to my opinion. Stefaan "Kelvin XCJ" <qijun@okigrp.com.sg> schreef in bericht news:3ce8a00a@news.starhub.net.sg... > Hi: > > I want to know what's the advantage Altera and Xilinx over each other. > Are their performance very different from each other? > > -- > Best Regards, > ----------------------------------------------------------------- > Xu Qijun > Engineer > OKI Techno Centre (S) Pte Ltd > Tel: 770-7081 Fax: 779-1621 > Email: qijun@okigrp.com.sg > >Article: 43349
On Mon, 20 May 2002 08:59:20 +0200, Stephanie McBader <mcbader@neuricam.com> wrote: >Hmm so it wouldn't help the final - synthesised - design! :( >Oh well. Remember that the GSR net is driven at the end of configuration. The POC block makes you source code simulate the way it behaves on the chip. Regards, Allan. >Thanks anyhow. > >Stephanie McBader >Researcher/Design Engineer >NeuriCam S.p.A >Via S M Maddalena 12 >38100 Trento TN, Italy >Tel: +39-0461-260552 >Fax: +39-0461-260617 > >Ray Andraka wrote: > >> You can put the ROC in as an instantiated black box. For simulation it can be >> used to initialize the design. It will persist through synthesis. The Xilinx PAR >> will remove it without complaining >> >> Stephanie McBader wrote: >> >> > Thanks a lot for your suggestion, Sweir. >> > >> > I have had a look at the Xilinx website for more info on this - do you know if >> > the ROC component is only used for simulation or can it be also used for >> > synthesis? >> > >> > Regards, >> > >> > Stephanie McBader >
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