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Hi, I'd like to know whether there is a possibility to use two different clocks conected to two different registers in the same CLB. if it's possible , howto guidence will be most welcomed. Thanks in advance, EyalArticle: 43377
Greg wrote: > > Hi, > > I am looking at buying a Spartan II proto. board from Insight > Electronics and was wondering if I need to buy the package that comes > with the JTAG cable. There is ~ a $40 difference between the package > with and without the JTAG cable. Is it possible to use something other > than a JTAG cable to configure the FPGA? > Schematics of that board (vs. 3) are here: http://208.129.228.206/solutions/kits/xilinx/spartan-ii.html#order You will need a Parallel cable III or IV, or equivalent. The JTAG connector is in lower right corner of the board's photo. -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 43378
Check your datasheet for the Virtex-II. You'll see that the clock has to be the same between two registers in the same *slice*. There are 4 slices in a CLB and they should all have independent clocks available to them. The FPGA Editor can show you how routing could be done. Have you had problems assigning registers with different clocks (or clock polarities) to different slices in the same CLB? Are you using LOC constraints to the CLB level but not selecting the individual slice? Eyal Shachrai wrote: > Hi, > > I'd like to know whether there is a possibility to use two > different clocks conected to two different registers in > the same CLB. > if it's possible , howto guidence will be most welcomed. > > Thanks in advance, > EyalArticle: 43379
Hi, I did some serious thinhing about fpga cpu's for some months, but I come to the same bottleneck every time. After making small 8 bit processors with supporting assembler software on windows PC, ... After using Altera Nios, studying Xilinx Microblaze,... I every time want to make my own processor, with the best things of all the previous mentioned systems, and I always stuck on the C (c++) compiler port. Do I really need to learn everything on Linux (or cygwin) and gcc before I can do a successfull port? Can I do it uberhaupt on my own, or do I need a team of specialists? I thought on porting smaller compilers before (lcc), but I need the c++ support. Can someone please point me into the right direction? Is there documentation available (except the 'using and porting gcc' from Stahl)? Thanks.Article: 43380
I looked into this a few years ago. If I remember correct, fractional-N clocks were originally an HP invention back in the 70's for frequency synthesis in sweepers and spectrum analysers. They needed low phase noise (what RF guys call jitter) as well. I remember reading a patent, I'm pretty sure it was an expired HP patent on fractional-N dividers. It was a very good description of the techniques and the complexity trade-offs for low phase noise. Usually patents are hard to read, but this one was like a really good howto article on fractional-N dividers. Sadly, I no longer have the patent, maybe a delphion seach will turn up something. jeff "Marcel" <marcelgl-hates-spam@xs4all.nl> wrote in message news:<3ce90ef5$0$3874$e4fe514c@dreader4.news.xs4all.nl>... > Hi, > > I need to generate a tunable clock in the range from 18Mhz - 30Mhz with > 100Hz resolution. > I was considering to use an external VCO and implement a PLL in the FPGA. > But I was wondering is this > also can be done in another way. > > The main problem is that the clock is used for audio D/A, so it must be a > low jitter clock. > > Any suggestions ? > > MarcelArticle: 43381
In article <3CE71336.AE37F5A8@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >If you intend for the interconnect to be equivalent to an AND gate, then >there are several ways to implement this. Implementing several hundred >AND gates can be done using several hundred logic blocks or by time >multiplexing a single AND gate with all the inputs. > >A large FPGA can implement a huge number of neurons each with a large >number of inputs and yes, those inputs can be programmable. The trick >is to map these operations to the logic in an efficient way. Efficient >mapping in your application depends on the complexity of the >interconnect functions (the AND gate, not very complex) and the neuron >itself (no info on this since you don't feel we need to know that). > >Ignoring the issue of the neuron structure itself, the interconnect can >be time multiplexed to prevent duplication of the AND gate. The block >ram allows the controlling element of many neuron inputs to be held in a >single element and selected through the address lines. Now the output >will be time multiplexed and the only remaining feat is to time >multiplex the input. If your neuron states are time multiplexed, they >can be stored in a block ram as well. The neuron block ram can read out >in the appropriate sequence to feed the neuron input selector. This is >not a trivial design to tackle, even at a block diagram level, unless >you understand how the various logic elements operate and how the >various functional block operate. We understand how the logic element >operate and you understand what your functional elements are. To >architect this further we would need to understand better how the >neurons operate. > >To give you an idea of the limitations of a block ram approach, each RAM >has 16 kbits. This can implement about 80 sets of neuron inputs at 200 >each. There are 168 block rams in the largest Virtex II for 13,440 >maximum neurons if the block rams are only used for neuron inputs. >Using an external memory will get around this limitation. > >So how do you plan to implement the neurons? This will make a big >difference. It will help if you can describe the neurons in logic terms >rather than functional terms that will need to be translated to logic. >For example, I don't know what "input conditions are satisfied" means in >terms of logic. Is this a count of inputs at a logic '1' being above a >threshold? Or is it an AND gate for all inputs? Or is it a certain >pattern on the inputs? > >Finally, what is the input and output from this neuron array? Also how >do you plan to alter the interconnect "on the fly"? The nature of the >alteration makes a BIG difference to how you implement it. Do the >neuron outputs alter the interconnects? Or does some external process >alter the interconnects? How much time can be used to make the >changes. Can the neuron processing be stopped while the interconnects >are changed? Thanks for the informative reply. Here's a brief explanation of the neurons and their connections. Neurons Most of my neurons can be loosely compared to AND gates. I add up the strength (16-bit integer) of all the input synapses that fire at a given time. If it is over 90% of the total strength of all inputs, the neuron fires. The connections that contributed to firing are then strengthened and the others are weakened. Some of my neurons use a fixed time delay on all connections except one. Most neurons have a single input synapse that I call the master synapse. All other inputs synapses are slaves. The neuron cannot fire unless the master synapse fires. So there is no need to do an input summation unless a signal arrives at the master synapse. Command Neurons These neurons have the highest number of input synapses. A command neuron fires every time one of its input signals arrives. Command signals will have a special remedial input whose signal strongly suppresses the most recently fired synapse. Searching The system needs to periodically (every second or so) make random connections between neurons in a layer to neurons in a downstream layer. All connections are given a low initial strength. Connections persist indefinitely unless neural activity weakens their strength below what I call a disconnect level, at which time they are disconnected. Timing and Signal Flow The signal arrival time at the master synapse is the reference time. Ideally, the temporal resolution should be as high as possible. But since I want to emulate biological neurons, I will be satisfied with a 1 millisecond resolution. Signal flow through the system must remain constant because timing is critical. The making and breaking of connections must not disrupt signal flow. This seems to require some sort of master clocking mechanism. Layers There is only one type of neuron in any given layer. Temporal Intelligence: http://home1.gte.net/res02khr/AI/Temporal_Intelligence.htmArticle: 43382
Hello, I'm just trying to get an idea what percentage of logic designs are synchronous single clock domain with strict I/O, meaning no tristates or shared buses. Sure almost every complete chip design has several clock domains and most have some form of a shared inout bus. But I am curious what percentage of a design is purely synchronous single clock without shared buses. The last two years I have worked for an FPGA design firm that specialized in image processing cores. All of our individual cores were built synchronous, single clock. At times when we needed to integrate several cores together and connect to external devices, we would create a top level design unit that contained all the shared buses and tristates. If we needed to move data across clock domains we would drop in a multi-clocked FIFO between two design components. But still all the major design units were synchronous, single clock logic void of bidirectional buses--accounting for about 95-98% of a total design. Is this pretty typical? I'm curious what percentages are common within the ASIC and SoC design communities. Thanks for your input. TomArticle: 43383
Derren Crome wrote: > > Hi, > > How do I program a XCR5064 coolrunner? The ISE4.2i IMPACT tool detects > there is a JTAG device but cannot identify part (IDCODE). Tried earlier > versions of the JTAG programming software with same results. > > Any ideas? Yes, keep going back in time, until you find a tool that supports it :-) It may be under Philips banner, as Xilinx culled 5V Coolrunner quite quickly, and they (understandbly) remove support on newer toolsets to save the testing time. Perhaps Xilinx could run a museum section, on their Web, al la Borland ? If you want a current 5V ISP device, look at the ATF1504ASL. -jgArticle: 43384
The data sheet specifies a delay per logic function of <2 ns. Four of them add up to less than 8 ns. Then you have to add the routing delay which depends on your layout/floorplan. A rule of thumb is that a carefully planned design has routing delays of the same order as logic delays ( but the variation is wide, and you can influence it). That would indicate a reasonable clock frequeny of 60 MHz, less if the rouring is scattered all over the place, or a higher frequency for a well-structure design. Peter Alfke Songqing Zhang wrote: > Hi, which device did you tried? I later talked to a few seniors and they felt not confident. Did you try 8 stage logic on 4000XLA? > Thanks > SongqingArticle: 43385
You will need to use the XPLA Programmer which you can download from the link below Xilinx Home : Products and Solutions : Design Resources : Free ISE WebPACK Derren Crome wrote: > Hi, > > How do I program a XCR5064 coolrunner? The ISE4.2i IMPACT tool detects > there is a JTAG device but cannot identify part (IDCODE). Tried earlier > versions of the JTAG programming software with same results. > > Any ideas? > > Thanks > > -- > Derren CromeArticle: 43386
Hi, which device did you tried? I later talked to a few seniors and they felt not confident. Did you try 8 stage logic on 4000XLA? Thanks SongqingArticle: 43387
hi, Is there a power consumption scaling factor that can be used between FPGAs and ASICs. I understand that there are parameters such as process technology that will affect the actual power. But I would like to know if we could give an approximate power consumption in ASIC for a design based on the power values achieved in an FPGA. Thanks, PrashantArticle: 43388
Prashant, This is difficult, because one (if one is an FPGA vendor) tends to compare the latest and greatest FPGA with the present stable ASIC process, which is usually one of two generations older than FPGA technology. The reason for this (other than it results in a better looking comparsion) is that the latest FPGA is commercially available today (Virtex II, Virtex II Pro at 0.15u and 0.13u), wheras an ASIC at these nodes would take awhile to fab out, and get debugged, and placed into production. Hence, if you are conccerned with what is the performance difference, you need to assume that by the time the ASIC makes it into your system, the FPGA will already be one or two generations ahead of the ASIC by that time. If you are an ASIC vendor, you would compare the same technologies arguing that apples are apples, and comparing unlike technologies is not a valid comparison. The FPGA vendor counters with why would you compare a 0.18u ASIC when I can use a 0.13u FPGA to do the same job today? Compare solutions, not technologies. No one will argue that ASICs can be more power efficient per se, but as to what factor to use, that may be tough to get agreement on. Moving targets. Austin Prashant wrote: > hi, > Is there a power consumption scaling factor that can be used between > FPGAs and ASICs. I understand that there are parameters such as > process technology that will affect the actual power. But I would like > to know if we could give an approximate power consumption in ASIC for > a design based on the power values achieved in an FPGA. > > Thanks, > PrashantArticle: 43389
Traveler wrote: > Thanks for the informative reply. Here's a brief explanation of the > neurons and their connections. > > Neurons > > Most of my neurons can be loosely compared to AND gates. I add up the > strength (16-bit integer) of all the input synapses that fire at a > given time. If it is over 90% of the total strength of all inputs, > the neuron fires. The connections that contributed to firing are then > strengthened and the others are weakened. Some of my neurons use a > fixed time delay on all connections except one. > > Most neurons have a single input synapse that I call the master > synapse. All other inputs synapses are slaves. The neuron cannot > fire unless the master synapse fires. So there is no need to do an > input summation unless a signal arrives at the master synapse. > > Command Neurons > > These neurons have the highest number of input synapses. A command > neuron fires every time one of its input signals arrives. Command > signals will have a special remedial input whose signal strongly > suppresses the most recently fired synapse. > > Searching > > The system needs to periodically (every second or so) make random > connections between neurons in a layer to neurons in a downstream > layer. All connections are given a low initial strength. Connections > persist indefinitely unless neural activity weakens their strength > below what I call a disconnect level, at which time they are > disconnected. > > Timing and Signal Flow > > The signal arrival time at the master synapse is the reference time. > Ideally, the temporal resolution should be as high as possible. But > since I want to emulate biological neurons, I will be satisfied with a > 1 millisecond resolution. Signal flow through the system must remain > constant because timing is critical. The making and breaking of > connections must not disrupt signal flow. This seems to require some > sort of master clocking mechanism. > > Layers > > There is only one type of neuron in any given layer. > > Temporal Intelligence: > http://home1.gte.net/res02khr/AI/Temporal_Intelligence.htm Your neurons are quite complex having a weight for every synapse input. This requires that each input have an N bit register for the weight along with a mechanism for updating the weight on firing etc. Each of these weights for synapses that have fired must be summed. BTW, this is nothing like an AND gate, this is purely an arithmetic operation. Although the "Master Synapse" is processed with an AND gate. I am still not clear if the weighting you have described is the same as the connect/disconnect mechanism you described in the earlier post. If so, the structure is not too much more complex that what we originally thought. If this weighting is in addition to the connect/disconnect mechanism, then there is a lot more logic involved that I had originally thought. Your problem is basically of complexity order M where M is the total number of synapse inputs to all of the neurons. If you want 200,000 neurons and 200 synapses each, you need to evaluate 40,000,000 synapses per ms or 40,000,000,000 per sec. Assuming a clock of 100 MHz, this requires 400 processing units to achive that speed. With only 168 block RAMs to work with in the largest FPGA, you will fall short by a factor of 3. The speed can be met by reducing the number of synapses and/or neruons. But there is a tougher problem. Your arithmetic synapses require the storage of 40 million 8 bit weights (I am assuming this size). The 168 block rams can only store 344,000 8 bit numbers. Off chip storage is difficult due to the high bandwidth required (320 Gbps each read and write). To use external DDR-SDRAM, it would require 80 memory chips at 32 bits and 266 MHz. To bring this to a manageable size you would need to cut your total synapse size by a factor of about 4 (100 k neurons, 100 synapses each). This would require 20 memory chips, 32 bits each, 266 MHz and 640 data IOs. Or 10 memory DIMMs could be used. RDRAM RIMMs run at up to 800 MHz, 18 bits per module. Using 20 modules would provide 256 Gbits/s on a 320 bit data bus or just less than half the bit rate required. This of course assumes that the RDRAM electrical spec is supported by the VII chips. So it appears that in the Xilinx VII FPGAs your algorithm would be memory bound and not speed bound. External memory is possible, but not at full speed. The use of standard DDR memory or modules would facilitate the solution, or RDRAM might allow it to operate closer to full speed. But don't think this is an easy hardware solution. Connecting that much memory in parallel to one chip would be a difficult layout task. Initially you might want to work with a much smaller number of neurons to get the approach and design details ironed out. Work within a single chip on an off the shelf board initially. Then plan your custom board based on your results. Or as I suggested before, you could do the same amount of processing in software on 100 DSPs. This is a lot, but they will be much more flexible and should be simpler to optimize. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43390
Hello Matjaz, This issue, which affected Nios 2.0 VHDL simulation only, has been fixed. The resolution is listed on the Altera Online Solutions Database here: http://www.altera.com/support/solutions/rd02142002_8882.html. Thanks, Alan Calac Altera Corp. "Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message news:<ac08pe$jdk$1@planja.arnes.si>... > I have a problem with Nios (2.0) simulation in Modelsim Altera 5.5e. After > the SOPC builder configuration (and simulation contents setup of > peripherals) and generation I tried to simulate the original Altera 32bit > Nios vhdl example (standard_32). Modelsim seems to do the initialization ok > but when I tried to execute run command it terminates with the message: > > # ** Fatal: Value -1742495648 is out of range 0 to 2147483647 > # Time: 0 ps Iteration: 0 Instance: > /test_bench/dut/the_boot_monitor_rom/boot_monitor_rom_lane0 > # Fatal error at > C:/vhdl/excalibur/nios2/examples/vhdl/standard_32/ref_32_system_sim/boot_mon > itor_rom_lane0_module.vhd line 50 > # > > I did everything step by step as required in the Altera's app note (app189 - > simulating nios embedded processor designs) but it worked only with 16bit > Nios configurations. None of 32bit functioned. I used the same settings in > both 16 and 32bit configurations: no flash, uart with divisor 2, RAM (int or > ext) with the same build file (e.g. hello_world.c), ... In all cases just > the equivalent 16bit version could be simulated. > > What to do? Is it Nios or Modelsim problem? > > Please help. > > My OS: Win98 (I know Nios isn't 100% compatible but it fuctions ok with some > minor workarounds - but is it relevant in this case?) > > Regards, > > MatjazArticle: 43391
Rick Filipkiewicz wrote: > > I seem to be having enormous difficulties accessing the 2 basic Xilinx > distis which, until recently, have had at least reasonable web sites. > > o Insight: This used to have a decent US site but since the takeover by > the Memec group its been given some bloody corporate makeover by web > insultants. Now I can't get to it via Netscape on the PC, In order to > register I had to use IE (the welcome mat for viruses), and I can now > access the site using Netscape 4.7 under BSDI Unix but every time I try > a part search I get ``general error - please contact webmaster'' (also > happens with IE). > > o NuHorizons: Can't get to it at all via Netscape (some bloody > JavaScript complaint about the page's``tags''). Using IE I can get into > the home page but any attempt to part search just gets a ``server down > please try later...'' message!! This site has changed format twice in > the last 6 months. > > Is this some sort of charity service for HTML hackers unemployed since > the dot.bomb? > > Anybody else having the same trouble ? Any suggestions ? Upgrade to NS > 6.2 ? I know what you mean about Insight. Their web site is essentially disfunctional unless you are running on a high speed link and use IE. BTW, Insight has always been part of Memec. They even had the same look and feel web site as their sister companies. But about four months or so ago they did a major overhaul of the web site and now getting the most basic info is like pulling teeth. Complain to the web master and contact your local office for pricing. I don't see the same problem you are getting at Nuhorizons. That is where I go to check relative pricing on Xilinx now. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43392
Jeff Mock wrote: > > I'm looking at doing a contract project to design a compact flash > card. I would like to use a Spartan2 on the board, but I'm > concerned about the I(ccpo) parameter in Spartan2. The Spartan2 > needs 500mA for a couple mS during power-on until it sorts out the > random power-on bus contention in the chip. > > The Compact Flash spec says that a card shouldn't consume more > than 75mA. > > Xilinx has nice app notes on spartan power supply requirements at > power-up: http://www.xilinx.com/xapp/xapp450.pdf and > http://www.xilinx.com/xapp/xapp451.pdf > > I generally believe the Xilinx story, but I'm hesitatant to use > the part in an environment where I don't have control over the > power supply. It would be horrible to plug the CF card into a > PDA and have the power supply fold-back on insertion and screw-up > everything. > > Does anyone have any experience with SpartanII in a Compact Flash > sort of power environment? > > jeff I don't see how you can use any of the FPGAs from any of the main manufacturers with a 75 mA total Icc. The Iccintq is near that for the SIIs and over that for the SIIEs ignoring the startup current surge. The Altera parts also have about a 100 mA requirement, IIRC. They don't publish this number, but they will give it to you if you ask. The coolrunner parts may well be your best bet with that power draw. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43393
Tom Hawkins wrote: > > Hello, > > I'm just trying to get an idea what percentage of logic > designs are synchronous single clock domain > with strict I/O, meaning no tristates or shared buses. > > Sure almost every complete chip design has several clock > domains and most have some form of a shared inout bus. > But I am curious what percentage of a design is purely > synchronous single clock without shared buses. > > The last two years I have worked for an FPGA design firm > that specialized in image processing cores. All of our > individual cores were built synchronous, single clock. > > At times when we needed to integrate several cores together > and connect to external devices, we would create a top level > design unit that contained all the shared buses and tristates. > If we needed to move data across clock domains we would drop > in a multi-clocked FIFO between two design components. > But still all the major design units were synchronous, > single clock logic void of bidirectional buses--accounting for > about 95-98% of a total design. > > Is this pretty typical? I'm curious what percentages are > common within the ASIC and SoC design communities. > > Thanks for your input. > > Tom The way you describe it, yes, I expect the vast majority of designs will contain major blocks without tristate busses and single clocks. I expect most designers will construct the same way you did to facilitate the handling of clock domain crosses. I know I do. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 43394
Jeff Mock wrote: > > I'm looking at doing a contract project to design a compact flash > card. I would like to use a Spartan2 on the board, but I'm > concerned about the I(ccpo) parameter in Spartan2. The Spartan2 > needs 500mA for a couple mS during power-on until it sorts out the > random power-on bus contention in the chip. > > The Compact Flash spec says that a card shouldn't consume more > than 75mA. > > Xilinx has nice app notes on spartan power supply requirements at > power-up: http://www.xilinx.com/xapp/xapp450.pdf and > http://www.xilinx.com/xapp/xapp451.pdf > > I generally believe the Xilinx story, but I'm hesitatant to use > the part in an environment where I don't have control over the > power supply. It would be horrible to plug the CF card into a > PDA and have the power supply fold-back on insertion and screw-up > everything. How much logic do you need to integrate, and does it need to run faster than the Read BUS speed ? ( ie any on card clock ? ) -jgArticle: 43395
What is the preferred way to provide a PVT compensated 50 ohm source termination in CMOS for an IO driver? Thanks, AndyArticle: 43396
You can keep full precision by connecting a shift register to your LSB out of
the scaling accumulator. The brute force method would then be to use a second
adder to add 0.5 your output LSB before truncating. A more elegant solution is
to retain the LSB of the feedback (this is the bit that falls off the end) and
selectively add 1 during one cycle of the sequence. The timing of that add 1
depends on whether you retain LSBs below the LSB of the accumulator or not. If
not, then it gets added during the cycle the MSB input is getting added.
Pete Dudley wrote:
> Hello
>
> I have an distributed arithmetic design that uses a scaling accumulator. The
> Xilinx core generator produces an accumulator that shifts right by one bit
> before feeding back into the adder to affect a divide by two. In the process
> the lsb is simply thrown away.
>
> My application is sensitive to truncation errors. Is there a simple way to
> use the carry_in pin of the accumulator to implement a round instead of a
> truncation in the shifted feedback data? The input and output data of the
> accumlator is signed two's complement.
>
> --
> Pete Dudley
>
> Arroyo Grande Systems
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43397
To me these are relatively minor. The differences depend on your application.
If you have something that uses a lot of arithmetic, you need to look carefully
how it gets mapped into the Altera device of your choice. I've expounded on
this many times here, and a summary can be found in the FAQ maintained by Phil
Freidin.
stefaan vanheesbeke wrote:
> Both are look up table oriented.
>
> Xilinx uses more a strategy of sea of identical logic cells. Altera is more
> structured in local groups of logic cells that are interconnected on a
> higher level.
>
> Xilinx has a better approach for dual ported ram (dual port == dual port).
> But Altera blockram can be used as asynchronuous RAM, Xilinx blockram is
> only synchronuous.
>
> There are a lot more differences, but these are the most important to my
> opinion.
>
> Stefaan
>
> "Kelvin XCJ" <qijun@okigrp.com.sg> schreef in bericht
> news:3ce8a00a@news.starhub.net.sg...
> > Hi:
> >
> > I want to know what's the advantage Altera and Xilinx over each other.
> > Are their performance very different from each other?
> >
> > --
> > Best Regards,
> > -----------------------------------------------------------------
> > Xu Qijun
> > Engineer
> > OKI Techno Centre (S) Pte Ltd
> > Tel: 770-7081 Fax: 779-1621
> > Email: qijun@okigrp.com.sg
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43398
Thing is SPDT switches are more expensive, as are extra pins. If you do have the
unlikely luxury of a SPDT switch and pins to spare, a simpler set up is to use the
switch with the common contact connected to ground and the other contacts running
into the opposite sides of an RS latch with pull up resistors on both inputs. That
way the RS gets set/reset only when contact with the opposite contact of the switch
is first made.
John_H wrote:
> Ignoring debounce for the moment, the syntax you might want might look like the
> following:
>
> reg use_sync;
> reg used;
> always @(posed clk)
> begin
> use_sync <= USED_IN; // you don't want metastability
> used <= use_sync;
> if( use_sync && !used ) // edge detector
> lstate <= lstate +1;
> end
>
> This synchronous design won't give an incorrect count due to a switch edge
> detected at about the same time as the clock edge. The debounce mentioned by
> another poster could be used or you might try a technique I used a long time ago
> if your pushbutton is alterable: rather than using an SPST with a pulldown
> resistor and the switch to VCC, use an SPDT with the switch connections to VCC
> and GND and the center to 1) your input and 2) through a small resistor (200
> ohms, perhaps) to a pin driven by the use_sync register introduced above. The
> idea here is that when the VCC is detected, the "bounce" will be between VCC and
> open. The first contact in the bounce will be significantly more than one clock
> cycle so the resistor "feedback" will change the state of the "float" to a logic
> high. Similar behavior when the switch is released and the ground is
> reestablished. Nice little hardware debounce that requires an extra pin and a
> double throw.
>
> cfk wrote:
>
> > I have a board with a VirtexE on it and with amongst other things, a button
> > (call it USER_IN) and three leds (call then LED[2:0]) controlled by a
> > variable lstate. I want to create a modest state machine so that I
> > initialize lstate to 3'b000, and then with each button push, I move to
> > 3'b001..3'b111 and then back to 3'b000. I tried the following:
> >
> > always @(posedge clk and USER_IN)
> > begin
> > lstate = lstate + 1;
> > end
> >
> > But what seems to happen is the states are cycling through at clk speed. The
> > reason I could not use (posedge clk and posedge USER_IN) is then the Xilinx
> > ISE wants to assign USER_IN to a clock pin and I cannot implement the
> > design. Maybe this issue is my understanding of ISE and Verilog as I am
> > officially a newbie at this time.
> >
> > Next I tried
> >
> > always @(posedge clk and USER_IN)
> > begin: ledstater
> > reg lstate_toggle;
> > if(USER_IN & lstate)
> > begin
> > lstate_toggle = !lstate_toggle;
> > lstate = lstate + 1;
> > end
> > end
> >
> > This one doesn't seem to do anything to the LED's (which are set with a
> > seperate assign statement). So, any suggestions would be greatly
> > appreciated.
> >
> > Charles
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43399
The initialization of the registers in the FPGA in implicit: All the registers start
with a known initial value at the end of configuraiton whether you have the ROC
primitive in your design or not. The ROC component helps because it makes the
simulation match the hardware.
Stephanie McBader wrote:
> Hmm so it wouldn't help the final - synthesised - design! :(
> Oh well.
>
> Thanks anyhow.
>
> Stephanie McBader
> Researcher/Design Engineer
> NeuriCam S.p.A
> Via S M Maddalena 12
> 38100 Trento TN, Italy
> Tel: +39-0461-260552
> Fax: +39-0461-260617
>
> Ray Andraka wrote:
>
> > You can put the ROC in as an instantiated black box. For simulation it can be
> > used to initialize the design. It will persist through synthesis. The Xilinx PAR
> > will remove it without complaining
> >
> > Stephanie McBader wrote:
> >
> > > Thanks a lot for your suggestion, Sweir.
> > >
> > > I have had a look at the Xilinx website for more info on this - do you know if
> > > the ROC component is only used for simulation or can it be also used for
> > > synthesis?
> > >
> > > Regards,
> > >
> > > Stephanie McBader
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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