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This thread has gone on too long. For a clear description of the synchronous write and asynchronous read in Xilinx distributed RAM ( in the CLBs), see the schematic diagrams on pages 6-14, 16, and 17 in the 1999 Xilinx data book. These diagrams are detailed and accurate ( I drew them ) and they explain the latching of the addresses and data and the generation of the write enable pulse. (What is not shown is the elaborate mecahnism that guarantees that the write pulse is of sufficient length under all processing and ambient conditions). Virtex BlockRAMs are very different. They are 4K-bit fully synchronous (write and read) fully dual-ported RAMs where each port can individually trade off address width against data width. So that is very different. But Viretx has of course also the above mentioned distributed CLB RAMs with synchronous write and asynchronous read. Peter Alfke, Xilinx Applications ( yes, he is still alive, just was on vacation )Article: 17076
----- Original Message ----- From: Sven Lücke <luecke@esk.fhg.de> Newsgroups: comp.arch.fpga Sent: 29 June 1999 16:08 Subject: altera flex 10k20 dedicated input | Hi, All, | | | is it possible to use the flex 10k20 dedicated inputs as a general | purpose input. | | Yes, but MaxPlusII tends to get confused if your using an input which is registered and you've got "AUTO_FAST_IO = ON" in your .acf file. You may need to add: LOGIC_OPTIONS BEGIN |<your input signal> : FAST_IO = OFF; END; Hope this helps Chris Squires __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ e-mail: chris@highwater.co.uk www http://www.highwater.co.uk __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 17077
Rickman skrev i meddelandet <3778D404.D4F6F769@yahoo.com>... >"Thomas A. Coonan" wrote: >> >> Like I said, just saying: >> >> reg [7:0] my_memory[0:31]; >> >> Will typically create a flip-flop based "register file" that does >> *exactly* what I need - problem is that it is flip-flops and >> horribly silicon intensive. I need a real RAM. The above >> actually (in my synthesis experience) simply elaborates from >> the 2-D array into the flattened 1-D array (e.g. 256 >> flip-flops). >> >> Now, everyone. Please - the issue is not whether FPGAs >> and ASICs have memories. Of course they do. Do they >> have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs. > And you might want to try out the Atmel 40k FPGA family. Lots of distributed SRAM... For each 16 logic blocks, you have an additional 32 x 4 Dual Port SRAM in the routing area. Reading is always asynchronous,writing can be synchronous. Pin compatible with Xilinx also ... -- This is a personal view which may or may not be shared by my employer Atmel Sweden Ulf Samuelsson ulf 'a't atmel 'd'o't comArticle: 17078
Ray Andraka writes: >> Now, everyone. Please - the issue is not whether FPGAs >> and ASICs have memories. Of course they do. Do they >> have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs. > Most current devices do, including Xilinx4K/XCS, Virtex (CLB rams), Altera 10K, > and 20K. Make that Altera 10KE not 10K. AFAIK, 10K only allows both synchronous or both asynchronous. I'll be delighted if you can show me I'm wrong though. -- JamieArticle: 17079
I've been doing a trial post-synth simulation comparing results between
VITAL compliant representation and one using 'embedded' timing, etc. To
my initial bafflement I found that the VITAL simulation was not
catching the same number of setup violations as the non-VITAL sim. The
problem seems to be that a VITAL generic called
'tsetup_d_clk_noedge_negedge' (!) is being assigned a default value of
0ns whereas its +edge counterpart is getting a meaningful value.
When I looked at the SDF file all I see is
(TIMINGCHECK
(SETUP D (posedge CLK) (19:19:19))
(HOLD D (posedge CLK) (15:15:15))
))
Only when I manually edited this, poking in a negedge clk entry, did
said Generic get initialiased.
My SDF (2.1) was produced by Altera's MaxPlus2 (9.21) and I'm
simulating with Viewlogics Speedwave/Fusion 2.3.
This is scary; I don't want to know too much about VITAL, etc! Comments
would be appreciated.
MIKE
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17080The 10K can have synchronous write and async read, although the address for both read and write is shared. WHat that means is the address is either registered or it is not at the EAB. You can however control the registering on the input data and we, output data and address separately, so you could do sync write and async read (with some admittedly hokey addressing). Each of those registers can also be clocked by a different clock. The 10KE brings separate read and write addresses to the party for psuedo-dual port operation (one port is read-only, one is write only), as well as the capability of registering one address and not the other. Jamie Lokier wrote: > Ray Andraka writes: > >> Now, everyone. Please - the issue is not whether FPGAs > >> and ASICs have memories. Of course they do. Do they > >> have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs. > > > Most current devices do, including Xilinx4K/XCS, Virtex (CLB rams), Altera 10K, > > and 20K. > > Make that Altera 10KE not 10K. > > AFAIK, 10K only allows both synchronous or both asynchronous. > I'll be delighted if you can show me I'm wrong though. > > -- Jamie -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17081
Just to clarify it, as there seems to be confusion: The Virtex CLB ram is capable of async read + sync write operation (or of sync - sync operation). The Virtex block RAM is a true synchronous dual port. Both ports are synchronous only for both read and write, although they can use separate (unrelated) clocks. Rickman wrote: > "Thomas A. Coonan" wrote: > > > > Like I said, just saying: > > > > reg [7:0] my_memory[0:31]; > > > > Will typically create a flip-flop based "register file" that does > > *exactly* what I need - problem is that it is flip-flops and > > horribly silicon intensive. I need a real RAM. The above > > actually (in my synthesis experience) simply elaborates from > > the 2-D array into the flattened 1-D array (e.g. 256 > > flip-flops). > > > > Now, everyone. Please - the issue is not whether FPGAs > > and ASICs have memories. Of course they do. Do they > > have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs. > > Was I unclear in my earlier post? Let me restate... > > "I can guaranty that the Xilinx Vertex has such a memory. The Xilinx > parts since the XC4000E all have had a dual port synchronous SRAM built > into the LUT of each CLB. This will give you 32 x 1 when used as you > describe above which does not require a dual port memory if you cycle > the address using an external mux. Or you will get 16 x 1 in each CLB if > you want the memory to supply that mux. > > In addition, the Vertex parts supply separate blocks of memory with full > true dual porting. Each port can read or write independantly from the > other. They can even be configured for different data widths, such as 8 > bits in on one side and 16 bits out on the other. > > In the Xilinx library the CLB SRAMs are RAM32X1S and RAM16X1D for the > single port synchronous and dual port synchronous memories respectively. > I haven't worked with the Vertex so I don't know the name of the block > ram. " > > So yes, there are multiple types of memory in the Xilinx Vertex devices > that have sync writes and async reads. Is there anything unclear about > that? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17082
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There is an old application note on our web site entitled, "Pulse Width
Modulation in Xilinx Progammable Logic" and can be found at
http://www.xilinx.com/appnotes/pwm.pdf There are some Viewlogic schematic
files that accompany that application note however I do not suggest using
them since they are a bit old and out-dated. A while back I wrote some
Verilog code adapted from this app note for a project I was involved with. I
will go ahead and include it here if you are intersted and feel free to adapt
it however you see fit. It is really simple code so I am not going to
explain it.
Enjoy and good luck,
-- Brian Philofsky
Xilinx Applications Engineer
//
// PULSE_WIDTH_MODULATOR.V Version 1.0
// Pulse Width Modulation Circuit
// Addapted from "Pulse-Width Modulation
// in Xilinx Programmable Logic" application
// Brief, April 11, 1995
//
module pulse_width_modultor (pwm, duty_cycle, new_value, clk, reset);
input new_value, clk, reset;
input [7:0] duty_cycle;
output pwm;
reg pwm;
reg [7:0] dc, q;
always @ (posedge clk or posedge reset)
begin
if (reset)
dc <= 8'h00;
else if (new_value)
dc <= duty_cycle;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
q <= 8'h00;
else if (q)
q <= dc;
else if (pwm)
q <= q + 1;
else
q <= q - 1;
end
always @ (posedge clk or posedge reset)
begin
if (reset)
pwm <= 1'b0;
else if (q)
pwm <= ~pwm;
end
endmodule
EKC wrote:
> I am attempting to build a PWM Servo Motor Controller card based on an
> FPGA. I was wondering if anyone had any pointers to literature or other
> information sources that could help me design such a system. I haven't
> decided which FPGA vendor I will be using, so I would appreciate any
> suggestions.
>
> Thanks in advance,
>
> EKC
--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------
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<html>
<p>There is an old application note on our web site entitled, "Pulse Width
Modulation in Xilinx Progammable Logic" and can be found at <A HREF="http://www.xilinx.com/appnotes/pwm.pdf">http://www.xilinx.com/appnotes/pwm.pdf</A>
There are some Viewlogic schematic files that accompany that application
note however I do not suggest using them since they are a bit old and out-dated.
A while back I wrote some Verilog code adapted from this app note for a
project I was involved with. I will go ahead and include it here
if you are intersted and feel free to adapt it however you see fit.
It is really simple code so I am not going to explain it.
<p>Enjoy and good luck,
<p>-- Brian Philofsky
<br> Xilinx Applications Engineer
<br>
<p>//
<br>// PULSE_WIDTH_MODULATOR.V Version 1.0
<br>// Pulse Width Modulation Circuit
<br>// Addapted from "Pulse-Width Modulation
<br>// in Xilinx Programmable Logic" application
<br>// Brief, April 11, 1995
<br>//
<p>module pulse_width_modultor (pwm, duty_cycle, new_value, clk, reset);
<p> input new_value, clk,
reset;
<br> input [7:0] duty_cycle;
<p> output pwm;
<p> reg pwm;
<br> reg [7:0] dc, q;
<p> always @ (posedge clk or posedge reset)
<br> begin
<p> if (reset)
<br> dc <= 8'h00;
<br> else if (new_value)
<br> dc <= duty_cycle;
<p> end
<p> always @ (posedge clk or posedge reset)
<br> begin
<p> if (reset)
<br> q <= 8'h00;
<br> else if (q)
<br> q <= dc;
<br> else if (pwm)
<br> q <= q + 1;
<br> else
<br> q <= q - 1;
<p> end
<p> always @ (posedge clk or posedge reset)
<br> begin
<p> if (reset)
<br> pwm <= 1'b0;
<br> else if (q)
<br> pwm <= ~pwm;
<p> end
<p>endmodule
<br>
<br>
<p>EKC wrote:
<blockquote TYPE=CITE> I am attempting to build a PWM
Servo Motor Controller card based on an
<br>FPGA. I was wondering if anyone had any pointers to literature or other
<br>information sources that could help me design such a system. I haven't
<br>decided which FPGA vendor I will be using, so I would appreciate any
<br>suggestions.
<p>Thanks in advance,
<p>EKC</blockquote>
<pre>--
-------------------------------------------------------------------
/ 7\'7 Brian Philofsky (brian.philofsky@xilinx.com)
\ \ ` Xilinx Applications Engineer hotline@xilinx.com
/ / 2100 Logic Drive 1-800-255-7778
\_\/.\ San Jose, California 95124-3450 1-408-879-5199
-------------------------------------------------------------------</pre>
</html>
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--------------24CBF04A20ABE853B3D0F0F5--
Article: 17083Tom Kean wrote: > Steven Casselman wrote: > > > > > My patent predates Gilsons. > > My priority date is July 29, 1992 > > http://www.patents.ibm.com/details?pn=US05684980__&language=en > > > > I think it is generally accepted that the first papers on reconfigurable > computing with FPGA's were published in the 1988/1989 timeframe. DEC > Paris Research labs. published several papers about their Xilinx based > computer and Algotronix published several papers on their system which > used proprietary chips. I think the above people did great work. However I don't think my paper http://www.vcc.com/nsf1.html (1987) should be discounted just because I'm a commerical person concerned about patent rights. Also in the research I did I found many comments like "one design per program." As the goal. This was the main foucs of these groups up untill the early 90's (correct me if I'm wrong). In my final SBIR report (jan 90) I cover runtime reconfiguration among other things such as compiling from C or ADA. > Algotronix CHS2x4 custom computer was reviewed in the International > edition > of BYTE magazine in September 1991. This was the first commerically available product. We did not sell to the public untill around 1994. > > > Having said that 'reconfigurable computing' was really invented by a > bunch > of very smart people in the late 60's and early 70's who did not have > the > process technology available to make it stick. Look at http://www.computer-museum.org/groups/Slide/114.html Note the quote "instructions could be modified by the computer as it went along". So John von Neumann invented the reconfigurable computer. Many will argue but I contend that modern reconfigurable computers were not possible untill the invention of the FPGA by Ross Freeman. Anything before that was more like the work of Babbage when compared to the work of von Neumann (by the way I believe that Estrin worked with von Neumann before von Neumann died) > > > This does not mean that there are no patent issues around the > technology: > there are. The patents mentioned above are not the ones that would > worry > me the most if I was in the reconfigurable computer business. > > Tom. You should post what are the important patents in your opinon. I admitt that the claims in my patent could be better worded (which is why the patent was resubmitted and the new claims will be much broader). -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 17084
On Fri, 18 Jun 1999 14:59:42 -0400, Brian Boorman <XZY.bboorman@harris.com> wrote: Bye bye Coolrunner... >Dear Valued CoolRunner Customer, > >We are pleased to inform you of a change in ownership of the CoolRunner >product >family. Philips Semiconductors has elected to sell its CoolRunner >Programmable >Logic business to Xilinx Inc. This sale includes the CoolRunner XPLA >and the >CoolRunner 22V10 devices. The CoolRunner product family will >benefit from >dedicated and expanding support due to the new arrangement. > >Xilinx intends to keep and enhance the CoolRunner product line. In >the near >term, the primary goal during the transition is maintaining the same >level of >service and support you have come to expect of the CoolRunner product >group. > >Philips Semiconductors and Xilinx are grateful for your >understanding and >patience in this time of transition. If you have any questions, >please feel >free to call us at 1-888-COOLPLD or email your >questions to >coolpld@abq.sc.philips.com. > >Sincerely, > >Xilinx Inc. and the CoolRunner product group -- Steven J. Ackerman, Consultant ACS, Sarasota, FL sja@gte.net http://www.acscontrol.comArticle: 17085
This is a multi-part message in MIME format. ------=_NextPart_000_01CC_01BEC249.BCD17F80 Content-Type: multipart/alternative; boundary="----=_NextPart_001_01CD_01BEC249.BCD17F80" ------=_NextPart_001_01CD_01BEC249.BCD17F80 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hello my name is Jeff George, and I am contacting professionals with = FPGA experience hoping to find one of you available for an open position = with my client. The client I represent is a discretionary Commercial = Aerospace contractor working on both US Commerical Aerospace and US DoD = contracts. =20 Title: Ground Unit Design Engineer - f/Encrypted/Decrypted Voice & Data = Communications=20 Location: Torrance, CA Term: 2 - Contracts: 2 - 2 1/2 years and 1 - Perm/Full-Time Start date: Immediately/2 weeks notice =20 Details: We are looking for a high level FPGA Xilinx Digital Hardware Design = Analyst for a Ground Unit Design Engineer position. Prefer someone with = encrypted/decrypted voice and or data space/satellite communications = experience. This person should be experienced in running a small = program, doing the technical work and some management. Will have brought = a product from inception to output. Must be able to demonstrate = exceptional knowledge of digital and analog communication systems = hardware, firmware and high level software design experience. = Specifically individuals will be responsible for understanding = requirements as they apply to product designs. Capabilities MUST Include: TTL, CMOS, ECL and Xilinx FPGA or other FPGA design, implementation and = test. Product layout and digital/analog design to support speeds of up = to 250Mhz. Knowledge of RS-422/RS-232 or other real-time communication = protocols or high speed interfaces. Secured embedded processor and = computer designs with full or partial redundancy. Knowledge of NSA = product endorsement includes TEMPEST, Cryptographic Verification, = EMI/EMC, PCA and MRR a plus. Design analysis for single point failures, = reliability, MTBF requirements as well as worst case analysis. = Presentations for customers, marketing and design reviews will be = required. US Citizenship required! Must have active or previous = clearance. If you feel that you may fit this position and would like to proceed = with an interview, will you please forward a copy of your resume to me = at jgeorge@govjobs.com. If you are not interested and can refer someone = who knows this technology, can you please forward my e-mail address to = them. Thanks in advance Jeffrey George <*)))>< Senior Technology Specialist click to enter V: 714 928=B7 9797 / F: 714 444=B7 3513 JGeorge@GOVJOBS.COM ------=_NextPart_001_01CD_01BEC249.BCD17F80 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META content=3Dtext/html;charset=3Diso-8859-1 = http-equiv=3DContent-Type><!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 = HTML//EN"> <META content=3D"MSHTML 5.00.2614.3401" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV> </DIV> <DIV><FONT color=3D#000000 size=3D2> <DIV><FONT color=3D#000000 size=3D2> <DIV><FONT color=3D#000000 size=3D2>Hello my name is Jeff George, and I = am=20 contacting professionals with FPGA experience hoping to find one of you=20 available for an open position with my client. The client I represent is = a=20 discretionary Commercial Aerospace contractor working on both US = Commerical=20 Aerospace and US DoD contracts.</FONT><BR></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Title: <STRONG>Ground Unit Design = Engineer -=20 f/Encrypted/Decrypted Voice & Data Communications = </STRONG></FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT><FONT size=3D2>Location: = <STRONG>Torrance,=20 CA</STRONG><BR>Term: <STRONG>2 - Contracts: 2 - 2 1/2 years and 1 -=20 Perm/Full-Time<BR></STRONG>Start date: <STRONG>Immediately/2 weeks=20 notice</STRONG></FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Details:</FONT></DIV> <DIV>We are looking for a high level FPGA Xilinx Digital Hardware Design = Analyst=20 for a Ground Unit Design Engineer position. Prefer someone with=20 encrypted/decrypted voice and or data space/satellite communications = experience.=20 This person should be experienced in running a small program, doing the=20 technical work and some management. Will have brought a product from = inception=20 to output. Must be able to demonstrate exceptional knowledge of digital = and=20 analog communication systems hardware, firmware and high level software = design=20 experience. Specifically individuals will be responsible for = understanding=20 requirements as they apply to product designs.</DIV> <DIV> </DIV> <DIV>Capabilities MUST Include:<BR>TTL, CMOS, ECL and Xilinx FPGA or = other FPGA=20 design, implementation and test. Product layout and digital/analog = design to=20 support speeds of up to 250Mhz. Knowledge of RS-422/RS-232 or other = real-time=20 communication protocols or high speed interfaces. Secured embedded = processor and=20 computer designs with full or partial redundancy. Knowledge of NSA = product=20 endorsement includes TEMPEST, Cryptographic Verification, EMI/EMC, PCA = and MRR a=20 plus. Design analysis for single point failures, reliability, MTBF = requirements=20 as well as worst case analysis. Presentations for customers, = marketing and=20 design reviews will be required. US Citizenship required! Must have = active or=20 previous clearance.</DIV> <DIV> </DIV> <DIV><FONT color=3D#000000 size=3D2>If you feel that you may fit this = position and=20 would like to proceed with an interview, will you please forward a copy = of your=20 resume to me at <A = href=3D"mailto:jgeorge@govjobs.com">jgeorge@govjobs.com</A>. If=20 you are not interested and can refer someone who knows this technology, = can you=20 please forward my e-mail address to them.</FONT></FONT></DIV></DIV> <DIV><BR>Thanks in advance<BR><BR><B><FONT face=3DArial = size=3D4><B><FONT=20 face=3DArial><FONT size=3D4><B><FONT face=3D"Arial Narrow" = size=3D4><FONT=20 face=3DArial>Jeffrey George</FONT> </B></FONT></B></B><FONT=20 size=3D2><*)))><</FONT><B><B><B><B><FONT face=3D"Arial Narrow"=20 size=3D4><BR></FONT></B></B></B></B><FONT color=3D#000000 face=3D"News = Gothic MT"=20 size=3D2>Senior Technology Specialist</FONT><B><B><B><B><FONT = color=3D#808080=20 face=3D"News Gothic MT" size=3D1><BR></FONT></B></B></B></B><FONT = color=3D#000080=20 size=3D1><IMG align=3Dbaseline alt=3D"" border=3D0 hspace=3D0=20 src=3D"cid:01c401bec284$69272fc0$b9c7adce@sirius2">click to = enter<BR></FONT><FONT=20 face=3D"Arial Narrow" size=3D2>V: 714 928=B7 9797 / F: 714 444=B7 = 3513<BR></FONT><A=20 href=3D"mailto:JGeorge@GOVJOBS.COM"><FONT face=3DArial><FONT=20 size=3D2>JGeorge@GOVJOBS.COM</FONT></FONT></A></FONT></FONT></FONT></DIV>= </FONT></DIV></BODY></HTML> ------=_NextPart_001_01CD_01BEC249.BCD17F80-- ------=_NextPart_000_01CC_01BEC249.BCD17F80 Content-Type: image/gif Content-Transfer-Encoding: base64 Content-ID: <01c401bec284$69272fc0$b9c7adce@sirius2> R0lGODlh3QA2APYAAP////f///f/9/f3//f39+/3/+/v7+f39+fv9+fn597v997n797n597e3tbn 79be59bW1s7n787e787O1s7Ozsbe78bOzsbGzsbGxr3W5729vbXW57XG1rW9xrW9vbW1ta3O3q3G 3q3Gzq21ta2traW1vaWlpZzG3py93py1xpytvZycnJS93pS91oy91oyUjIyMjIS11oSMlHu11nut znuEhHOtzmulzmulxmtra1qcxlKUxkqUvUKMvTmMvTmEvTmEtTGEtSl7tSF7tSFztSFzrRhzrRBz rRBrrQhrrQhrpQhjpQBjpQAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAACH/ C05FVFNDQVBFMi4wAwEAAAAh+QQEyAAAACwAAAAA3QA2AEYH/4AAgoOEhYaHiImKi4yNjo+QkZKT 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Thanks everybody! I think I got it now. I did not mean to be per-snipity to anyone; it's just that the whole asynchronous read is crucial to my instruction cycle, and I have been misunderstood on this detail in the past. I'll make my little design based on such a memory timing. Solved! >Just to clarify it, as there seems to be confusion: The Virtex CLB ram is >capable of async read + sync write operation (or of sync - sync operation). >The Virtex block RAM is a true synchronous dual port. Both ports are >synchronous only for both read and write, although they can use separate >(unrelated) clocks. > >Rickman wrote: > >> "Thomas A. Coonan" wrote: >> > >> > Like I said, just saying: >> > >> > reg [7:0] my_memory[0:31]; >> > >> > Will typically create a flip-flop based "register file" that does >> > *exactly* what I need - problem is that it is flip-flops and >> > horribly silicon intensive. I need a real RAM. The above >> > actually (in my synthesis experience) simply elaborates from >> > the 2-D array into the flattened 1-D array (e.g. 256 >> > flip-flops). >> > >> > Now, everyone. Please - the issue is not whether FPGAs >> > and ASICs have memories. Of course they do. Do they >> > have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs. >> >> Was I unclear in my earlier post? Let me restate... >> >> "I can guaranty that the Xilinx Vertex has such a memory. The Xilinx >> parts since the XC4000E all have had a dual port synchronous SRAM built >> into the LUT of each CLB. This will give you 32 x 1 when used as you >> describe above which does not require a dual port memory if you cycle >> the address using an external mux. Or you will get 16 x 1 in each CLB if >> you want the memory to supply that mux. >> >> In addition, the Vertex parts supply separate blocks of memory with full >> true dual porting. Each port can read or write independantly from the >> other. They can even be configured for different data widths, such as 8 >> bits in on one side and 16 bits out on the other. >> >> In the Xilinx library the CLB SRAMs are RAM32X1S and RAM16X1D for the >> single port synchronous and dual port synchronous memories respectively. >> I haven't worked with the Vertex so I don't know the name of the block >> ram. " >> >> So yes, there are multiple types of memory in the Xilinx Vertex devices >> that have sync writes and async reads. Is there anything unclear about >> that? >> >> -- >> >> Rick Collins >> >> rick.collins@XYarius.com >> >> remove the XY to email me. >> >> Arius - A Signal Processing Solutions Company >> Specializing in DSP and FPGA design >> >> Arius >> 4 King Ave >> Frederick, MD 21701-3110 >> 301-682-7772 Voice >> 301-682-7666 FAX >> >> Internet URL http://www.arius.com > > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > >Article: 17087
In article <7l8ou8$4eo@dfw-ixnews17.ix.netcom.com>,
EKC <NOSPAMalpha3.1@ix.netcom.com> wrote:
> I am attempting to build a PWM Servo Motor Controller card based on an
>FPGA. I was wondering if anyone had any pointers to literature or other
>information sources that could help me design such a system. I haven't
>decided which FPGA vendor I will be using, so I would appreciate any
>suggestions.
National has a PID-compensated 32-bit PWM servo motor controller chip (but I
can't remember the number, but it was quite expensive ($45 in singles)).
Anyway, it's a completely straightforward implementation of a PID
compensator followed by a PWM modulator with quadrature inputs to measure
the rotor angle. It used a single difference for the D and the integrators
(accumulators, really) had settable limits to prevent correction magnitudes
from getting really out of hand. The controlled variable was angle, but a
ramp generator was provided to generate a constant speed (overflow is a
non-issue if the word lengths are all the same). It should be very easy to
implement this in an FPGA since it doesn't have to be very fast- the most
difficult circuit will be the multiplier or the sequencer. The NS chips cut
corners by only allowing limited ranges in some of the coefficients, so you
should try to find the datasheet for these hints. It might be possible to
do this with a PIC, which would be easier unless you need the FPGA for other
hardware.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 17088The rates for the PID for a motor controller are most likely low enough to do the PID compensator and most of the PWM logic bit serially. That should make for a very compact design in an FPGA, and would likely fit just fine in something cheap like an XCS05XL. The bit rate clock should be no problem to obtain, since you probably need something close to it for the PWM anyway. Joseph H Allen wrote: > In article <7l8ou8$4eo@dfw-ixnews17.ix.netcom.com>, > EKC <NOSPAMalpha3.1@ix.netcom.com> wrote: > > I am attempting to build a PWM Servo Motor Controller card based on an > >FPGA. I was wondering if anyone had any pointers to literature or other > >information sources that could help me design such a system. I haven't > >decided which FPGA vendor I will be using, so I would appreciate any > >suggestions. > > National has a PID-compensated 32-bit PWM servo motor controller chip (but I > can't remember the number, but it was quite expensive ($45 in singles)). > Anyway, it's a completely straightforward implementation of a PID > compensator followed by a PWM modulator with quadrature inputs to measure > the rotor angle. It used a single difference for the D and the integrators > (accumulators, really) had settable limits to prevent correction magnitudes > from getting really out of hand. The controlled variable was angle, but a > ramp generator was provided to generate a constant speed (overflow is a > non-issue if the word lengths are all the same). It should be very easy to > implement this in an FPGA since it doesn't have to be very fast- the most > difficult circuit will be the multiplier or the sequencer. The NS chips cut > corners by only allowing limited ranges in some of the coefficients, so you > should try to find the datasheet for these hints. It might be possible to > do this with a PIC, which would be easier unless you need the FPGA for other > hardware. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17089
This is a multi-part message in MIME format. --------------2973F9F1B0A20B685D318834 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit > I think the above people did great work. However I don't think my paper > http://www.vcc.com/nsf1.html (1987) > should be discounted just because I'm a commerical person > concerned about patent rights. I was not aware of this reference. It is certainly very early for the FPGA based computing machines. Did NSF or VCC publically disclose the full proposal or the abstract at the time it was submitted? > Also in the research I did > I found many comments like "one design per program." As > the goal. This was the main foucs of these groups up untill > the early 90's (correct me if I'm wrong). In my final SBIR report > (jan 90) I cover runtime reconfiguration among other things > such as compiling from C or ADA. Run time reconfiguration is found in many early references. Using multiple configurations for one design is not common. I think I remember a patent from the mid 1980's which had this feature but I'd need to check. I would like to get a copy of your final SBIR report if that is possible (especially if it was published in 1990). > Look at > http://www.computer-museum.org/groups/Slide/114.html > Note the quote "instructions could be modified by the computer > as it went along". So John von Neumann invented the reconfigurable > computer. > That is arguable: his work on cellular automata is certainly closely related. I'm also not 100% convinced by Estrin since he used patch panels and plug in modules rather than electronic switches under memory control in the paper I read. However, I have never put a lot of effort into answering the question 'who was first'. Prior art from the 70's is just as good as prior art from the 50's -- actually its usually better because it is easier to relate to the claim language in the more recent patents. > > Many will argue but I contend that modern reconfigurable > computers were not possible untill the invention of the FPGA > by Ross Freeman. > I would argue with that. Its more like modern reconfigurable computers were not possible before CMOS technology got to a certain level of capability. Ross Freeman's genius was building a team that could turn his idea into an industry and hitting the market just when process technology made the overhead of reconfiguration economically viable. Tom. --------------2973F9F1B0A20B685D318834 Content-Type: text/x-vcard; charset=us-ascii; name="tom.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Tom Kean Content-Disposition: attachment; filename="tom.vcf" begin:vcard n:Kean;Tom tel;fax:UK +44 131 556 9247 tel;work:UK +44 131 556 9242 x-mozilla-html:TRUE org:Algotronix Ltd. adr:;;P.O. Box 23116;Edinburgh;;EH8 8YB;Scotland version:2.1 email;internet:tom@algotronix.com title:Director note:Web Site: www.algotronix.com x-mozilla-cpt:;4768 fn:Tom Kean end:vcard --------------2973F9F1B0A20B685D318834--Article: 17090
I think John gave some good advice. I have entered the domain of PLL once and being naive discovered that there is a bit of application to fit the need. The whole concept of changing the frequency of an oscillator based on a feedback from golden reference that happens to be at a lower frequency and a choice selection from some human... Well, that is all control theory. When folks talk about phase noise, jitter, etc ouch. All trades. I would be curious to know the bottom line. i.e. PLL for dummies. They have been around for years and have made their way into our everday life, but there seems to be this loss of continuim with regard to basic knowledge. Will need to check the notes John put out. But, pretty neat topic. jim . John Janusson wrote in message <7kp94h$o86$1@eng25.eng.I-O.com>... >This isn't exactly VHDL, but here it goes... > >Check out http://www.microlet.com/yam/. Somewhere on that site they have >the schematics for their early FPGA, which includes a >Digital PLL implementation. > >You state you want to remove jitter in an incoming data stream... Without >fully understanding your requirements, I'll go out on a limb and say that an >all digital PLL is generally not a good choice to reduce jitter (unless your >jitter's real bad to begin with). Jitter attenuators do the job, though >http://www.dalsemi.com/DocControl/PDFs/2188.pdf... > >The Bell Labs tech journals from the mid 1970's have tons of articles on >jitter in communication systems. > >The bible on PLLs theory is Phaselock Techniques by Gardner (1979-- good >stuff, huh!!! I'd borrow this one from the library). Nothing on DPLLs >though... > >http://www.amazon.com/exec/obidos/ASIN/0471042943/qid%3D930095120/002-95847 3 >0-2474442 > >Phase Locked Loops : Design, Simulation, and Applications by Best has a very >basic intro to DPLLs (I have the second edition, not the third). This one's >pretty old too... >http://www.amazon.com/exec/obidos/ASIN/0070060517/ref=sim_books/002-9584730 - >2474442 > >Monolithic Phase-Locked Loops and Clock Recovery Circuits : Theory and >Design from the IEEE is more current, and has a good PLL theory section. >I'd buy this one, if nothing else but for the references. >http://www.amazon.com/exec/obidos/ASIN/0780311493/ref=sim_books/002-9584730 - >2474442 > >Good Luck > >JJ > > >Mountain wrote in message <376FEE4C.AE377FD9@magenta.com>... >>O.k. ... as a firm believer in RTFM, I have been searching all day for >>digital PLL references / source code / models / book recomendations and >>I have come up just about empty. I found a couple books on amazon.com >>that are out of print .... (course I could check the library) ..... but >>I am basically coming up empty. >> >>I am your basic hardware engineer who also does FPGA design (now in >>VHDL) .... and I need to develop a Digital PLL for removing jitter in an >>incoming datastream ..... so ... since I have never messed with any >>PLL's .... I need a decent start point .... book references, web page >>references, source code to start from, anything .... >> >>So, I come asking for any pointers any of you may have .... all help is >>appreciated ..... >> >>Thanks, >>John Ledford > >Article: 17091
I may need to do uLaw and ALaw conversion in an FPGA since the newer AC97 codecs don't seem to support that internally. I could dig out copies of the specs and figure out how to implement the conversion myself, but I really just don't feel like doing all that thinking tonight. I got beat at indoor badminton by little old ladies and they wore me out! You wouldn't think that badminton would be such a strenuous sport, would you? Is there a simple way to perform this conversion one bit at a time? I did a little brain work and decided that a direct table lookup would be too expensive in terms of LUTs. If I remember correctly, one of the two, uLaw or ALaw, could be done with a table lookup for part of the word and an interpolation for the rest. And, of course, I need to convert in both directions. If I can't get anyone to do my thinking for me tonight, can someone at least point me to the specs for these two codes? Are they available online? Or are there any good references online? And yes, I agree that the conversion not only could, but should be done in software, but my customer has put it in the spec that the codec should provide this function. It is not a MIPS issue since I have been told that they don't need all the MIPS I am providing anyway. It is a "customer is always right" issue. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17092
On Sat, 26 Jun 1999 adamjone@purdue.edu wrote: > I'm using a Virtex XCV300 and I'm having trouble finding documentation > on how to perform readback with the JTAG/boundary-scan interface. The > configuration and readback document (xapp138.pdf) references only the > SelectMAP method of readback. It says to reference xapp139 for > information on readback and configuration with the JTAG. After > calling tech support, I found that this document has not yet been > written. I've tried simply entering the CFG_OUT instruction into the > TAP instruction register and then clocking out data, but that doesn't > do it. Does anyone know what the proper method for readback using the > JTAG on Virtex parts is? I'm not familiar with the 300 but can't help but wonder if there is a default readback before configuration-- so you could validate the scan logic for the expected default without having to be concerned with configuration problems??? During a capture_DR state, some default may be loaded into your boundary register. --al toda ########################################################### Alvin E. Toda aet@lava.net sr. engineer Phone: 1-808-455-1331 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html 1363-A Hoowali St. Pearl City, Hawaii, USAArticle: 17093
Ray Andraka wrote: > > Just to clarify it, as there seems to be confusion: The Virtex CLB ram is > capable of async read + sync write operation (or of sync - sync operation). > The Virtex block RAM is a true synchronous dual port. Both ports are > synchronous only for both read and write, although they can use separate > (unrelated) clocks. Thanks to both Peter and Ray for the corrections. I thought the Virtex block RAM used an asynch read. I think (maybe wrongly) that this would be preferred. But since the read and write are totally separate, it likely doesn't matter. Sometimes I am just a little too lazy to look things up when I am not certain. Posting late at night or first thing in the morning doesn't help ;) -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17094
Ray Andraka writes: > The 10K can have synchronous write and async read, although the > address for both read and write is shared. WHat that means is the > address is either registered or it is not at the EAB. Ah yes, I use the above all the time. My apologies, this is what I meant by "it can't do...": you can't have synchronous write address & async. read address at the same time. -- JamieArticle: 17095
Rickman wrote: > I remember seeing one of the two (mulaw I think) done in a simple table, > which implies that the best algorithm is some form of a table lookup. > The other is a little more complex, but I think it can be done bit > serial as well. > > I'll just have to poke around until I find some info. I am sure it is > out there somewhere. The original spec may be copyrighted, but there has > to be some form of a description. I found an excellent app note on the TI web site. It didn't show up in the list of app notes for the C54x, but I found it with a search. The number is SPRA163A. It discusses the nature and function of both companders and shows the tables for compression and expansion of each. It also provides C54x asm for each. So I am set. Thanks to anyone who listened to my thinking out loud. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17096
Hello. I am Choi, Ick Sung in Korea. I am sorry to ask this basic question ^^; I am studying the design flow of FPGA synthesis using Synopsys Design Compiler and Xilinx M1. My implementation device is Xilinx virtex XCV1000. I don't know what value to set as input/output_delay constraints at the pre-simulation process. Is their typical assumption value of them ? or should I determine that constraint values thru. back-annotation ? Thanks.Article: 17097
Rickman, The reference is ITU-T Recommendation G.711 "PULSE CODE MODULATION (PCM) OF VOICE FREQUENCIES" (1988 vintage, I think). http://www.itu.int/itudoc/itu-t/rec/g/g700-799/index.html This is copyright, so you shouldn't be able to get any free copies from the web, unfortunately. I notice this web site also has a *free* reference G.711 implementation in C from Sun. Regards, Allan. On Tue, 29 Jun 1999 23:13:22 -0400, Rickman <spamgoeshere4@yahoo.com> wrote: >I may need to do uLaw and ALaw conversion in an FPGA since the newer >AC97 codecs don't seem to support that internally. I could dig out >copies of the specs and figure out how to implement the conversion >myself, but I really just don't feel like doing all that thinking >tonight. I got beat at indoor badminton by little old ladies and they >wore me out! You wouldn't think that badminton would be such a strenuous >sport, would you? > >Is there a simple way to perform this conversion one bit at a time? I >did a little brain work and decided that a direct table lookup would be >too expensive in terms of LUTs. If I remember correctly, one of the two, >uLaw or ALaw, could be done with a table lookup for part of the word and >an interpolation for the rest. And, of course, I need to convert in both >directions. > >If I can't get anyone to do my thinking for me tonight, can someone at >least point me to the specs for these two codes? Are they available >online? Or are there any good references online? > >And yes, I agree that the conversion not only could, but should be done >in software, but my customer has put it in the spec that the codec >should provide this function. It is not a MIPS issue since I have been >told that they don't need all the MIPS I am providing anyway. It is a >"customer is always right" issue. > >-- > >Rick Collins > >rick.collins@XYarius.com > >remove the XY to email me. > > > >Arius - A Signal Processing Solutions Company >Specializing in DSP and FPGA design > >Arius >4 King Ave >Frederick, MD 21701-3110 >301-682-7772 Voice >301-682-7666 FAX > >Internet URL http://www.arius.comArticle: 17098
Alan Hall wrote: > > Second problem. > > I have an ABEL macro under a schematic top sheet. If the ABEL contains > only combinatorial equations then everything works fine. If it contains > a simple state machine, then I get "unconnected inputs" and "output > driven by 0" errors from the fitter. > > The ABEL seems to compile OK. None of the log files seem helpful. I get > "dangling port" warnings, but I understand this is normal and can be > ignored. I get the same warnings in the simple combinatorial case. Well, i noticed the warnings and messages as you. I got a "dangling port" message for every pin from an abel macro. I think this is OK, because everything works so far. MatthiasArticle: 17099
You should not need to do this. I have the JTAG download cable connected to a 95144XL and V1000 and reconfigure either or both without having to do anything else other than run JTAGPGMR. By the way, DONE does not seem to change from the configured state during JTAG programming or reprogramming. Albano, David (EXCHANGE:RTP:3H91) wrote in message <37777389.3324D3A7@americasm01.nt.com>... >I think you have to pulse the PRGM_ pin low in order to reconfigure using >the JTAG port once the device is configured once. I know the PRGM_ pin >is on the xchecker port, but this is what I have been told by my FAE. It >must be pulsed low for 500nS before reconfiguring using the JTAG port. > >David A. > >adamjone@purdue.edu wrote: > >> >> Also, I have been able to configure the Virtex device after >> startup using the JTAG, but I haven't been able to reconfigure the >> device after the first configuration. Is the sequence of commands >> different for a second configuration? >
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