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# Messages from 18825

Article: 18825
Subject: Re: implementing TCP/IP on PLD
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 18 Nov 1999 01:40:38 GMT
Links: << >>  << T >>  << A >>
"Dirk Bruere" <artemis@kbnet.co.uk> writes:

>Jamie Lokier <spamfilter.nov1999@tantalophile.demon.co.uk> wrote in message
>news:m2ogctdoqy.fsf@pcep-jamie.cern.ch...
>> Austin Franklin writes:
>> > You can not implement a TCP/IP stack in just a PLD, there simply aren't
>> > enough gates, so you must not mean PLD, but something else...possibly
>> > microprocessor, FPGA.
>>
>> I heard it's been done on an FPGA, and not an especially large one either.

>Not without a CPU core, AFAIK.

Well, say you implement a simple processor, either existing or new,
on the FPGA and then write code for it.  Maybe even a C compiler and
compile an existing implementation.  Much easier if it is just UDP, but
if the code is in ROM or RAM then even TCP shouldn't be hard.

-- glen

Article: 18826
Subject: Re: How to use GSR-net in Virtex?
From: "Austin Franklin" <austin@darkroom2.com>
Date: 18 Nov 1999 06:06:06 GMT
Links: << >>  << T >>  << A >>

> Don't instantiate the startup block.  Just make sure that the reset
signal
> goes to EVERY SINGLE FLIP-FLOP IN YOUR DESIGN, and your synthesis tool
> should infer GSR.  If it does not, you should get a message saying that
it
> was not inferred, and you'll have to look at the synthesis report to see
> which flops were not included.

That sounds tedious, probably un-necessary and may be even not right.  Why
not just do it this way:

STARTUP_VIRTEX  startup_virtex (
.GSR     (I_RESET),
.GTS     (I_TS),
.CLK     (1'b0)
);


Article: 18827
Subject: Re: COM1-FPGA communication
From: edick@hotmail.com (Richard Erlacher)
Date: Thu, 18 Nov 1999 06:21:38 GMT
Links: << >>  << T >>  << A >>
You can use Hyperteminal under Win9x or Terminal under Win3.1x.  Under
DOS, any comm program will work, e.g. TELIX.  It's a freeware program,
IIRC.

Dick

On Wed, 17 Nov 1999 03:10:41 -0800, Bonio Lopez
<bonio.lopezNOboSPAM@gmx.ch.invalid> wrote:

>Hi friends,
>I have implemented the UART in my FPGA. Now I whant to communicate with
>com1 port of
>my PC. (I have made also level conversion.) Only the problem that I
>can't program PC. I do
>not know Visual C++ and do not have old good turbo pascal. Do you have
>such program or any links,
>where I could get it.
>The program must only send symbol, I give, to COM1 and receive from Com1
>when I whant.
>Any help will be appreciated
>
>
>
>* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
>The fastest and easiest way to search and participate in Usenet - Free!
>


Article: 18828
Subject: Re: How to use GSR-net in Virtex?
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Thu, 18 Nov 1999 08:49:12 GMT
Links: << >>  << T >>  << A >>
On 18 Nov 1999 06:06:06 GMT, "Austin Franklin" <austin@darkroom2.com>
wrote:

>
>> Don't instantiate the startup block.  Just make sure that the reset
>signal
>> goes to EVERY SINGLE FLIP-FLOP IN YOUR DESIGN, and your synthesis tool
>> should infer GSR.  If it does not, you should get a message saying that
>it
>> was not inferred, and you'll have to look at the synthesis report to see
>> which flops were not included.
>
>That sounds tedious, probably un-necessary and may be even not right.  Why
>not just do it this way:
>
>STARTUP_VIRTEX  startup_virtex (
>        .GSR     (I_RESET),
>        .GTS     (I_TS),
>        .CLK     (1'b0)
>         );

This way saves you a lot of time during design, but the pre-synthesis
simulation results don't match the post place-and-route simulation
results.  This may or may not be important for you.

Allan.

Article: 18829
Subject: Re: How to use GSR-net in Virtex?
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Thu, 18 Nov 1999 10:01:15 +0100
Links: << >>  << T >>  << A >>
Hi
I was trying to implement the startup_virtex in a design and found some
Xilinx App Notes recommending NOT to use it because the GSR net is
slower than long lines (http://www.xilinx.com/techdocs/6713.htm)

Anyway, if I don't use the startup block, how can I reset the FFs at
startup without an external RC network on the reset pin?

Austin Franklin wrote:
>
> > Don't instantiate the startup block.  Just make sure that the reset
> signal
> > goes to EVERY SINGLE FLIP-FLOP IN YOUR DESIGN, and your synthesis tool
> > should infer GSR.  If it does not, you should get a message saying that
> it
> > was not inferred, and you'll have to look at the synthesis report to see
> > which flops were not included.
>
> That sounds tedious, probably un-necessary and may be even not right.  Why
> not just do it this way:
>
> STARTUP_VIRTEX  startup_virtex (
>         .GSR     (I_RESET),
>         .GTS     (I_TS),
>         .CLK     (1'b0)
>          );

Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE

Article: 18830
Subject: How can I specify the fanout constraints at FPGA compiler II & M1
From: "ischoi(etri.re.kr)" <ischoi@etri.re.kr>
Date: Thu, 18 Nov 1999 18:13:01 +0900
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------B3C8A56480CC543F8989D09C
Content-Type: text/plain; charset=EUC-KR
Content-Transfer-Encoding: 7bit

Hello.

I have a problem in designing our systems using virtex under Synopsys
FPGA compiler II,

& Alliance M1 environments.

In the past version of FPGA compiler, I can set the fanout constraints
explicitly using synthesis commands.

But, I can't find the corresponding command nor what to do to constrain
the fanouts at FPGA compiler II.

Is there any one who has any knowledge about them ?

Thanks you in advance.

Choi, Ick Sung.

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org:ETRI;Switching Technology
adr:;;161 Kajong-Dong Yuson-Gu;Taejon;;305-350;KOREA
version:2.1
email;internet:ischoi@etri.re.kr
title:Senior Researcher
fn:Choi, Ick Sung
end:vcard

--------------B3C8A56480CC543F8989D09C--


Article: 18831
Subject: How to use multiple resets?
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Thu, 18 Nov 1999 12:19:15 +0200
Links: << >>  << T >>  << A >>
I have a question which close to this discussion:

We are using Spartan-XL and we intend to use TWO individual resets
in the chip. We wonder if one reset can be assigned to the dedicated
reset routing resources and the other one to the normal routing
resources. We are using Synplify v5.08a, M1.5 and Verilog.

We have looked at the Synplify and M1.5 manuals, and following things
came out:

1. In the Xilinx manual "Synthesis and Simulation Design Guide", page
4-9, in the first paragraph:

"XC4000 and Spartan devices have a dedicated Global Set/Reset
(GSR) net that you can use to initialize all CLBs and IOBs. When the
GSR is asserted, EVERY flip flop in the FPGA is simultaneously preset
or cleared. You can access the GSR net from the GSR pin on the
STARTUP block or the GSRIN pin of the STARTBUF (VHDL)."

2. In the Synplify User Guide book, at the section "Xilinx FPGA Support",
at the item "Startup Block for XC4000 and XC5200", 3rd paragraph:

"If multiple resets are used in the design, then Synplify will not
automatically create a startup block in GSR. If you still want one
of the reset signals to be used for GSR then you will need to
manually instantiate a STARTUP_GSR module in your design source file."

From 1, I understand that it is impossible to use two resets one of which
I want to dedicate to GSR routing, because when GSR is asserted, ALL
the flip flops in XC4000 and Spartan will be resetted, some of which
actually have their own individual reset signal, which is not using
GSR routing but normal routing.

From 2, I understand that it is possible to use two resets and one
reset can be asserted to GSR routing and the other one must be used then
in normal routing. But 2 is correct only for XC4000 devices, since
the item is "Startup Block for XC4000 and XC5200", there is not the
word "Spartan" at the header title of the item.

If Xilinx is true, then I conclude that when I want to use more than
one reset in Spartan or XC4000, then routing will be worse, since
I mustn't use GSR usage for a correct operation and the resets will
use normal routing resources. That will make the routing more difficult.

If Synplify is true, then I conclude that when I want to use more
than one reset in XC4000 and XC5200, and when I want to assign one
of the two reset signals to the GSR routing, then routing will be
used efficiently.

Which is correct?

Utku

Article: 18832
Subject: Re: How many bits in an FPGA bitstream?
From: Peter <peterc@hmgcc.gov.uk>
Date: Thu, 18 Nov 1999 12:05:49 +0000
Links: << >>  << T >>  << A >>
John Larkin wrote:
>
> On Sat, 13 Nov 1999 09:17:00 GMT, rbarris@quicksilver.com (Rob Barris)
> wrote:
>
> |
> |   Say for a relatively low end part like a Xilinx XC4005 as seen in the
> |XESS board, just how many bits is the "bitstream" file that is loaded into
> |it for configuration?  Hundreds, thousands, tens of thousands?
> |
> |   Sorry if this is a really basic question. I'm exploring tying a
> |microcontroller to an FPGA, and I'm wondering how much space I need to
> |worry about dedicating to the config stream.  It might change over the
> |life of the system so a fixed configuration EPROM isn't in the cards.
> |
> |Rob
>
> Rob,
>
> a 4005EX or XL needs 151,960 bits.
>
> We commonly put the microprocessor code and the Xilinx config data
> into a single eprom, and let the uP load the FPGA(s) at powerup. It's

<snip>

Alternatively, USe the Xilinx in master parallel mode to program itself
from the EEPROM.

Don't forget to hold the processor in some way (e.g. reset) until the
Xilinx is configured. This is easy to acheive using LDC or HDC.

--
Peter Crighton

Article: 18833
Subject: Re: How to use GSR-net in Virtex?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 18 Nov 1999 08:38:10 -0500
Links: << >>  << T >>  << A >>
On power-up the registers initial values are all defined by the configuration
program.  GSR is indeed too slow for use in higher performance designs.  A
better strategy for FPGAs (and I know this makes an ASIC designer's blood
curdle) is to reset only strategic flip-flops in the design, which basically
means you really only need to reset a flip-flop in any logic loops and the
outputs of your chip.

For example, If I have a dataflow design that performs some math function, I can
apply reset for however many cycles it takes for the data to flow through, where
the reset holds the outputs at zero.  If you hold the input at zero for n
clocks, all the interior flops settle to a known state, and as long as the
output is held zero no one is the wiser.  The only flip-flops in the design that
won't settle to a known state are those inside a logic loop, such as a state
machine or an integrator.  Usually, I'll put in a reset state machine that
stretches the a one clock cycle reset input to however many clocks are needed to
clear the whole thing.   You will get 'X's during the reset sequence, but after
n clocks you are in a known state.  That can easily be accommodated in a
testbench.

Nicolas Matringe wrote:

> Hi
> I was trying to implement the startup_virtex in a design and found some
> Xilinx App Notes recommending NOT to use it because the GSR net is
> slower than long lines (http://www.xilinx.com/techdocs/6713.htm)
>
> Anyway, if I don't use the startup block, how can I reset the FFs at
> startup without an external RC network on the reset pin?
>
> Austin Franklin wrote:
> >
> > > Don't instantiate the startup block.  Just make sure that the reset
> > signal
> > > goes to EVERY SINGLE FLIP-FLOP IN YOUR DESIGN, and your synthesis tool
> > > should infer GSR.  If it does not, you should get a message saying that
> > it
> > > was not inferred, and you'll have to look at the synthesis report to see
> > > which flops were not included.
> >
> > That sounds tedious, probably un-necessary and may be even not right.  Why
> > not just do it this way:
> >
> > STARTUP_VIRTEX  startup_virtex (
> >         .GSR     (I_RESET),
> >         .GTS     (I_TS),
> >         .CLK     (1'b0)
> >          );
>
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
> Fax 00 33 1 46 67 51 01    FRANCE

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18834
Subject: Re: How to use multiple resets?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 18 Nov 1999 08:42:09 -0500
Links: << >>  << T >>  << A >>
There is only one global set/reset network, which means only one global reset
should you use the network.  If you do reset every flip-flop with one of two
resets you will use up general purpose routing for the second reset.  In an
FPGA, you want to try to do strategic resets rather than global resets to
leave routing open for other signals, and more importantly to keep from
dragging your maximum clock frequency down into the weeds.  See my previous
post in this thread for more detail.

Utku Ozcan wrote:

> I have a question which close to this discussion:
>
> We are using Spartan-XL and we intend to use TWO individual resets
> in the chip. We wonder if one reset can be assigned to the dedicated
> reset routing resources and the other one to the normal routing
> resources. We are using Synplify v5.08a, M1.5 and Verilog.
>
> We have looked at the Synplify and M1.5 manuals, and following things
> came out:
>
> 1. In the Xilinx manual "Synthesis and Simulation Design Guide", page
> 4-9, in the first paragraph:
>
> "XC4000 and Spartan devices have a dedicated Global Set/Reset
> (GSR) net that you can use to initialize all CLBs and IOBs. When the
> GSR is asserted, EVERY flip flop in the FPGA is simultaneously preset
> or cleared. You can access the GSR net from the GSR pin on the
> STARTUP block or the GSRIN pin of the STARTBUF (VHDL)."
>
> 2. In the Synplify User Guide book, at the section "Xilinx FPGA Support",
> at the item "Startup Block for XC4000 and XC5200", 3rd paragraph:
>
> "If multiple resets are used in the design, then Synplify will not
> automatically create a startup block in GSR. If you still want one
> of the reset signals to be used for GSR then you will need to
> manually instantiate a STARTUP_GSR module in your design source file."
>
> From 1, I understand that it is impossible to use two resets one of which
> I want to dedicate to GSR routing, because when GSR is asserted, ALL
> the flip flops in XC4000 and Spartan will be resetted, some of which
> actually have their own individual reset signal, which is not using
> GSR routing but normal routing.
>
> From 2, I understand that it is possible to use two resets and one
> reset can be asserted to GSR routing and the other one must be used then
> in normal routing. But 2 is correct only for XC4000 devices, since
> the item is "Startup Block for XC4000 and XC5200", there is not the
> word "Spartan" at the header title of the item.
>
> If Xilinx is true, then I conclude that when I want to use more than
> one reset in Spartan or XC4000, then routing will be worse, since
> I mustn't use GSR usage for a correct operation and the resets will
> use normal routing resources. That will make the routing more difficult.
>
> If Synplify is true, then I conclude that when I want to use more
> than one reset in XC4000 and XC5200, and when I want to assign one
> of the two reset signals to the GSR routing, then routing will be
> used efficiently.
>
> Which is correct?
>
> Utku

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18835
Subject: Re: How many bits in an FPGA bitstream?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 18 Nov 1999 08:45:45 -0500
Links: << >>  << T >>  << A >>
This does not apply for Spartan, and you need to be careful about your pin
assignments for the dual use pins.  If you want to use a parallel EEPROM (and
there are several good reasons to do so), an alternate solution that works well
is to use a PLD to serialize a parallel PROM output and generate the CCLK,
PGM/DONE and INIT signals for a serial slave mode configuration..

Peter wrote:

> John Larkin wrote:
> >
> Alternatively, USe the Xilinx in master parallel mode to program itself
> from the EEPROM.
>
> Don't forget to hold the processor in some way (e.g. reset) until the
> Xilinx is configured. This is easy to acheive using LDC or HDC.
>
> --
> Peter Crighton

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18836
Subject: Re: Actel FPGA prices
From: John Devereux <john@devereux.demon.co.uk>
Date: Thu, 18 Nov 1999 14:05:18 +0000
Links: << >>  << T >>  << A >>
On 17 Nov 1999 22:11:03 GMT, johne@vcd.hp.com
(John Eaton) wrote:

>I recently received a mailing from uniqueTechnologies touting the
>actel sx family over the Altera 7128. One of the points of comparison
>was price and they listed prices "as low as" $3.90 or$6.90 for the
>54sx08,54sx16 actel parts.
>
>I then pop open the arrow distributer web page and do a search on those
>parts and the lowest numbers are about $61 and$88. Thats 2 orders of
>magnitude difference.
>
>Wheres the best place to buy actel parts in quanities of 1-2 hundred
>pieces.
>
>John Eaton
>

I've seen this sort of thing too, with xilinx too
and others it seems quite common and a great
annoyance. They suggest an extremely low price to
get you interested, then when you try to actually
buy any the real price has no relation. The excuse
is that they are still new parts so are expensive.
So in other words, _one day_, the original price
will apply but this might not be for years! But
prices always come down with time anyway, i.e.
Moores law, so this is grossly misleading. All the
manufacturer has to do is wait long enough!

<end rant>

-- John Devereux

john@devereux.demon.co.uk


Article: 18837
Subject: Re: Xilinx M2.1i SP2?
From: dfrevele@li.net
Date: Thu, 18 Nov 1999 14:14:54 GMT
Links: << >>  << T >>  << A >>
Yes the slow clearing of the files in the temp directory is documented,
but that is not what I am talking about. I had an instance where design
manager left a windowless process running. This process had some files
open which prevented updater from replacing them.

In article <s34ne88ohsq26@corp.supernews.com>,
"Joel Kolstad" <Joel.Kolstad@USA.Net> wrote:
> <dfrevele@li.net> wrote in message news:7vukch$ipu$1@nnrp1.deja.com...
> > I am administrator for the engineering tools here and have installed
> > this service pack on half a dozen NT machines with no problems like
you
> > describe. The only problem I encountered, which produced an error
> > message, was due to an background process unexpectedly still running
and
> > locking the file so the installer could not overwrite it.
>
> I believe this is documented; I know I've read about it before.  The
> background process takes some 5 or 10 seconds to delete its temporary
files
> and allow you to run another service pack installatoin program.  You
just
> have to hurry up and wait...
>
> ---Joel Kolstad
>
>

Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 18838
Subject: Re: How to use multiple resets?
From: Brian Boorman <XYZ.bboorman@harris.com>
Date: Thu, 18 Nov 1999 10:36:23 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------F650BE6EB46FD7D9B5E270C6
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Utku Ozcan wrote:
>
<snip>
>
> 1. In the Xilinx manual "Synthesis and Simulation Design Guide", page
> 4-9, in the first paragraph:
>
> "XC4000 and Spartan devices have a dedicated Global Set/Reset
> (GSR) net that you can use to initialize all CLBs and IOBs. When the
> GSR is asserted, EVERY flip flop in the FPGA is simultaneously preset
> or cleared. You can access the GSR net from the GSR pin on the
> STARTUP block or the GSRIN pin of the STARTBUF (VHDL)."
>
> 2. In the Synplify User Guide book, at the section "Xilinx FPGA Support",
> at the item "Startup Block for XC4000 and XC5200", 3rd paragraph:
>
> "If multiple resets are used in the design, then Synplify will not
> automatically create a startup block in GSR. If you still want one
> of the reset signals to be used for GSR then you will need to
> manually instantiate a STARTUP_GSR module in your design source file."
>
> Which is correct?

Both are correct. You can have two resets, one of which uses the GSR,
the other using normal routing. The downside is that the GSR reset will
reset ALL flipflops. If you want two INDEPENDENT reset signals (which
from reading your post I assume is the case) then you MUST use regular
routing resources for BOTH reset signals.

--
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>
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Article: 18839
Subject: Re: Actel FPGA prices
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 18 Nov 1999 09:14:37 -0700
Links: << >>  << T >>  << A >>
John Devereux wrote in message ...
>On 17 Nov 1999 22:11:03 GMT, johne@vcd.hp.com
>(John Eaton) wrote:
>
>>I recently received a mailing from uniqueTechnologies touting the
>>actel sx family over the Altera 7128. One of the points of comparison
>>was price and they listed prices "as low as" $3.90 or$6.90 for the
>>54sx08,54sx16 actel parts.
>>
>>I then pop open the arrow distributer web page and do a search on those
>>parts and the lowest numbers are about $61 and$88. Thats 2 orders of
>>magnitude difference.
>>
>>Wheres the best place to buy actel parts in quanities of 1-2 hundred
>>pieces.
>>
>>John Eaton
>>
>
>I've seen this sort of thing too, with xilinx too
>and others it seems quite common and a great
>annoyance. They suggest an extremely low price to
>get you interested, then when you try to actually
>buy any the real price has no relation. The excuse
>is that they are still new parts so are expensive.
>So in other words, _one day_, the original price
>will apply but this might not be for years! But
>prices always come down with time anyway, i.e.
>Moores law, so this is grossly misleading. All the
>manufacturer has to do is wait long enough!

John (and John),

sounds like those mailings are written by the same people who write the
headline copy for all of those stupid computer-reseller catalogs that flood
my snail-mail box.  To wit:

Pentium III/600! 23 GB HDD! 256 MB SDRAM! $1599! * note the asterisk. -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.  Article: 18840 Subject: analog capabilities? From: me@here.com (myself) Date: Thu, 18 Nov 1999 16:18:33 GMT Links: << >> << T >> << A >> Hi I work at a small company and I design most of the equipment. The typical product is a radiation detector and has -Analog sensor -Analog amplifiers and switches -Analog to digital converters -Motorola Micro controller (and assembly lang. program) -Memory storage (program in the micro controller, data in a prom (flash eeprom)) -I/0 LCD's, switches, printers (RS232) My question is, how much can a ASIC FPGA or CPLD do? Is it limited to just digital signal processing? Or has enyone made one with some analog capabilities? Is there a general (beginner) article on the general functionality and uses of Asics and FPGA in instrumentation design on the web? P.s. I also have a couple of instruments that are purely digital and will easily lend them selves to FPGA design Any guidance is greatly appreciated.  Article: 18841 Subject: Re: How to use GSR-net in Virtex? From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam> Date: Thu, 18 Nov 1999 09:23:09 -0700 Links: << >> << T >> << A >> Austin Franklin wrote in message <01bf318a$fc7c84d0$207079c0@drt1>... > >> Don't instantiate the startup block. Just make sure that the reset >signal >> goes to EVERY SINGLE FLIP-FLOP IN YOUR DESIGN, and your synthesis tool >> should infer GSR. If it does not, you should get a message saying that >it >> was not inferred, and you'll have to look at the synthesis report to see >> which flops were not included. > >That sounds tedious, probably un-necessary and may be even not right. Why >not just do it this way: > >STARTUP_VIRTEX startup_virtex ( > .GSR (I_RESET), > .GTS (I_TS), > .CLK (1'b0) > ); No, neither tedious or unnecessary. And it is right. When I write code that's supposed to end up as a flipflop, I always include an async reset that uses the GSR. That takes care of the power-on reset. If a flip has to be (re)set any time other than at power-up, I use a synchronous reset. -- a ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao \dot\ edu "Creation Science" is oxymoronic.  Article: 18842 Subject: Not complett multipier LUT in FPGA From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid> Date: Thu, 18 Nov 1999 09:03:20 -0800 Links: << >> << T >> << A >> Dear friends, I want to define subset of integer :1,5,15,128, But I know only the syntax for sequent digits (as subtype my_int is integer range (0 to 100 ); How can I define such subtype where the digits are not sequent I meen as subtype my_int is integer range 1,5,25,128; But in correct VHDL syntax! Why do I Need this: I want to paralell (in FPGA) only this 5 integers with only others 40 integers. Thats why I want to get not complett multiplication LUT but only for this possiable combinations! Does somebody have any other idaes? With best regards, Bonio * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!  Article: 18843 Subject: Re: Not complett multipier LUT in FPGA From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid> Date: Thu, 18 Nov 1999 09:21:25 -0800 Links: << >> << T >> << A >> Sorry, I must correct small error in my first message(I have not typed word multiply): .... I want to paralell MULTIPLY (in FPGA) only this 5 integers with only... * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!  Article: 18844 Subject: Re: Need advice on interfacing SDRAM modules From: Maciej Bartkowiak <mbartkow@et.put.poznan.pl> Date: Thu, 18 Nov 1999 21:34:20 +0100 Links: << >> << T >> << A >> Thanks a lot, Joseph and Martin. It puts some light, but not very much, I am affraid. I am sorry I didn't articulate our problem correctly. What we are develo- ping is a custom data storage system which is to be equipped with PC-100 compliant SDRAM modules (so called DIMMs). It is intended for sequencing live digital video signal, so the timing requirements are not very high, but the data capacity requirements are high (the plans are to have few sockets for DIMM modules that would be enough for few minutes of the video signal to be stored (approx. 1MB/sec)). Those little buggers are not pure SDRAM chips but they have a variable structure and timing requirements all of which is described in each module's internal EPROM. The first problem is that we do not even know how to use some of the parameters. Is there something like a common denominator for all kinds of DIMM that might be simply used for slow read/write ? (well, relatively slow I mean, at least not at 100MHz bus clock) any help and comments greatly appreciated -- Maciej Bartkowiak, PhD ======================================================================== Institute of Electronics and Telecommunication fax: (+48 61) 6652572 Poznan University of Technology phone: (+48 61) 6652171 Piotrowo 3A email: mbartkow@et.put.poznan.pl 60-965 Poznan POLAND http://www.et.put.poznan.pl/~mbartkow ========================================================================  Article: 18845 Subject: Re: Need advice on interfacing SDRAM modules From: Rickman <spamgoeshere4@yahoo.com> Date: Thu, 18 Nov 1999 16:12:30 -0500 Links: << >> << T >> << A >> Maciej Bartkowiak wrote: > > Thanks a lot, Joseph and Martin. It puts some light, but not very much, > I am affraid. > > I am sorry I didn't articulate our problem correctly. What we are > develo- > ping is a custom data storage system which is to be equipped with PC-100 > compliant SDRAM modules (so called DIMMs). It is intended for sequencing > live digital video signal, so the timing requirements are not very high, > but the data capacity requirements are high (the plans are to have few > sockets for DIMM modules that would be enough for few minutes of the > video signal to be stored (approx. 1MB/sec)). > Those little buggers are not pure SDRAM chips but they have a variable > structure and timing requirements all of which is described in each > module's > internal EPROM. The first problem is that we do not even know how to use > some of the parameters. Is there something like a common denominator for > all kinds of DIMM that might be simply used for slow read/write ? (well, > relatively slow I mean, at least not at 100MHz bus clock) > > any help and comments greatly appreciated The question is how slow are you running? I designed a SDRAM interface that was running at 33 MHz about a year ago. The SDRAMs have many timing specs associated with them, but they generally fall into two broad catagories; timing from clock edges, number of clock cycles. At that speed, other than refresh and a couple of delays having to do with initialization, all of the timing delays relative to a clock edge were no more than 30 nS and met by a single clock cycle. Of course some of the pipeline delays are spec'ed by a number of clock cycles and you must meet those delays regardless of how slow your clock is running. But this project was not done using modules. I don't know for sure, but I believe some modules add a register to the data or address bus. This would add a clock cycle delay to the appropriate path. I know this is not as much as you would like, but to give you more I would need to study the data sheets for the modules. If you really get in a bind, give me a call. I might be able to answer a few questions. But think state machine. If you draw a state diagram of what you want the SDRAM to do, and design all of the delays for the worse case, you should be able to make most modules work in a slow application such as yours. But watch out for the registered modules, they must be treated differently. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com  Article: 18846 Subject: Re: Need advice on interfacing SDRAM modules From: Stefan Ludwig <Stefan.Ludwig@Xilinx.com> Date: Thu, 18 Nov 1999 13:33:43 -0800 Links: << >> << T >> << A >> This is a multi-part message in MIME format. --------------105419AE981D35F2BA810C70 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hello Maciej, you might want to check out Xilinx' reference design implementing a 133 MHz SDRAM controller for the Virtex FPGA. Go to http://www.xilinx.com/products/virtex/memory.htm for a wealth of information on memories. Regards, Stefan Ludwig In article <38303A31.6A89@et.put.poznan.pl>, Maciej Bartkowiak <mbartkow@et.put.poznan.pl> wrote: > Dear All > > Here, at the University, we are running a design project that involves > interfacing the SDRAM modules with a custom FPGA-based system. We have > to cope with severe problems related to the complexity of SDRAM control. > We badly need advice from experienced designers of uC systems and would > be truly thankful for some hints. We are looking for any possibilities > to contact such experts, so please let us know if you know any. --------------105419AE981D35F2BA810C70 Content-Type: text/x-vcard; charset=us-ascii; name="Stefan.Ludwig.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Stefan Ludwig Content-Disposition: attachment; filename="Stefan.Ludwig.vcf" begin:vcard n:Ludwig;Stefan tel;cell:(408) 858 7303 tel;fax:(408) 377 3259 tel;home:(408) 983 2480 tel;work:(408) 879 6076 x-mozilla-html:TRUE org:<img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx Inc.">;Virtex Systems Engineering adr:;;2100 Logic Drive;San Jose;CA;95124-3450;United States of America version:2.1 email;internet:Stefan.Ludwig@xilinx.com title:Manager Reference Designs fn:Stefan Ludwig end:vcard --------------105419AE981D35F2BA810C70--  Article: 18847 Subject: ROLLER GARAGE DOORS From: figluufg@which.net Date: 18 Nov 1999 21:51:52 GMT Links: << >> << T >> << A >> begin 755 tmp.html M/$A434P^#0H\2$5!1#X-"CQ4251,13X\+U1)5$Q%/@T*/"](14%$/@T*/$)/
M1%D^#0H\4T-225!4($Q!3D=504=%/2),:79E4V-R:7!T(CX-"G=I;F1O=RYL M;V-A=&EO;BYH<F5F/2)H='1P.B\O=W=W+G)O;&QE<F1O;W(N9&$N<G4B.PT*
=/"]30U))4%0^#0H\+T)/1%D^#0H\+TA434P^#0IE

end

---

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Article: 18848
Subject: Re: Need advice on interfacing SDRAM modules
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Thu, 18 Nov 1999 16:19:31 -0700
Links: << >>  << T >>  << A >>
Maciej Bartkowiak wrote in message <383462CC.681D@et.put.poznan.pl>...
>Thanks a lot, Joseph and Martin. It puts some light, but not very much,
>I am affraid.
>
>I am sorry I didn't articulate our problem correctly. What we are
>develo-
>ping is a custom data storage system which is to be equipped with PC-100
>compliant SDRAM modules (so called DIMMs). It is intended for sequencing
>live digital video signal, so the timing requirements are not very high,
>but the data capacity requirements are high (the plans are to have few
>sockets for DIMM modules that would be enough for few minutes of the
>video signal to be stored (approx. 1MB/sec)).
>Those little buggers are not pure SDRAM chips but they have a variable
>structure and timing requirements all of which is described in each
>module's
>internal EPROM. The first problem is that we do not even know how to use
>some of the parameters. Is there something like a common denominator for
>all kinds of DIMM that might be simply used for slow read/write ? (well,
>relatively slow I mean, at least not at 100MHz bus clock)

OK, the EEPROM is provided so the DIMM can identify itself to the system and
the system can configure itself as required.  It identifies how much memory
is on the module, how it is organized, how fast it is, etc etc.

If you're doing a custom memory controller, there's nothing saying you have
to use it.  In fact, you may be better off making your life easier and
deciding that all of the modules will be identical (same size, same speed,
etc).  This, of course, limits your module choices.  I just finished a
design that used four 128Mb chips.  It ended up being easier for me to just
plop the chips I specified onto the board in the somewhat bizarre memory
organization my application required than to deal with putting DIMMs onto
the board.

You also need to remember that even though your read and write duty cycles
may be very low, you must still talk to the SDRAM module at the clock speed.
However, there's no law saying that you must run PC100 modules at 100 MHz.
You can run them at 33 MHz if you like.

You're asking about the SDRAM timing parameters.  You must understand them
in order to use SDRAMs.  Parameter #1, of course, is the clock frequency,
which should be obvious.  Parameter #2 is the "CAS latency" (also called
read latency).  This is the delay between registration of the READ command
and the availability of first data word.  It's usually two or three clock
cycles, depending on the clock speed (a higher clock speed may require an
extra clock cycle).  There's also a latency from the time you activate
(OPEN) a row to the time you are allowed to assert a command; sometimes it's
one tick, or two if the clock speed is fast.

You should check out the SDRAM data sheets at Micron's web site.  They're
large (50 pages) but you really need to understand how the parts work before
attempting a design with them.  They're not necessarily difficult, just
idiosyncratic.

a

--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

"Creation Science" is oxymoronic.


Article: 18849
Subject: Re: analog capabilities?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 18 Nov 1999 19:43:55 -0500
Links: << >>  << T >>  << A >>
FPGAs are digital animals (although there are some "analog FPGAs" out
there that consist generally of some uncommitted opamps, current sources
and other analog stuff that can be connected together through a switch
matrix sort of like the digital ones).  That said, you can do some crude
analog in a pinch:
A pwm approach can be made to get an analog output with the addition
of an RC filter.  You can also get an analog output using a resistor
network with taps grounded by tristate or low output pins, but be careful
of digital noise.  On the input end, you can make a schmitt trigger using
two pins and two resistors, which, combined with the output circuits above
can be made into a sloppy delta-sigma ADC.  These things can be done, but
for most apps, you are better served with a cheap analog circuit hanging
off the FPGA.

myself wrote:

> Hi I work at a small company and I design most of the equipment.
> The typical product is a radiation detector and has
> -Analog sensor
> -Analog amplifiers and switches
> -Analog to digital converters
> -Motorola Micro controller (and assembly lang. program)
> -Memory storage (program in the micro controller, data in a prom
> (flash eeprom))
> -I/0 LCD's, switches, printers (RS232)
>
> My question is, how much can a ASIC FPGA or CPLD do?
> Is it limited to just digital signal processing? Or has enyone made
> one with some analog capabilities?
>
> Is there a general (beginner) article on the general functionality and
> uses of Asics and FPGA in instrumentation design on the web?
>
> P.s. I also have a couple of instruments that are purely digital and
> will easily lend them selves to FPGA design
>
> Any guidance is greatly appreciated.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka

`

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