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You can use syn_keep or equivalent to force a particular construction. Put the syn_keep on the x LUT output. Xilinx FAE from Insight SANKET wrote: > Hi Paul, > > Try this > x <= ((a xor b) xor (c xor d)); > y <= (( b xor c) xor (d xor e) xor f); > > Juggle with the parenthesis. > > Regards, > SANKET. > > "Paul Butler" <Paul.Butler@ni.com> wrote in message news:<u877thegcjnsa6@corp.supernews.com>... > > Suppose I have 6 inputs and 2 outputs like so: > > > > x <= a xor b xor c xor d; > > y <= b xor c xor d xor e xor f; > > > > Targeting 4 input LUTs, "x" requires one LUT because it has 4 inputs. "y" > > requires two LUTs since it has 5 inputs. However, it's possible to rewrite > > "y" as such: > > > > y <= x xor a xor e xor f; > > > > This "y" is a 4 input function! My circuit could be as small as two LUTs > > (one for "x" and one for "y")! > > > > Experimentally, I find that Xilinx XST 4.0.3 and Synplify Pro 7.0.3 both use > > 3 LUTs for this circuit. Even when I write "y" to explicitly depend on "a" > > and "x", the synthesizer removes the redundant input "a" and ends up with > > the 3 LUT solution. > > > > Is it true that these synthesizers will always remove unnecessary inputs > > without regard for circuit size? Said another way, can I count on the > > synthesizer to not add extra inputs to my function in order to minimize > > circuit size? Is this behavior common to other synthesizers? > > > > Thanks, > > Paul ButlerArticle: 40301
I want to implement a dynamic clock division as a power saving feature for a
project I'm working on (using SpartanII). Can I count clock pulses from a
fixed frequency clock (100MHz) from a DLL and output a clock pulse through a
BUFG (to be used as a clock by variable speed logic) when the counter
reaches a certain value ? Will this save any power ? Do I have to use a grey
code counter ?
Will code like the following work ?
Thanks
Rob
module clkgen(reset, clki, clk, clk90, wr, di);
input reset;
input clki;
output clk; // cpu (system clock)
output clk90; // clk phase shift. Use for bram access
reg clk90;
input wr;
input [7:0] di;
wire clk2x;
wire clkfb;
reg [7:0] clkcnt;
reg [7:0] clkdiv;
wire clkdv = clkcnt==clkdiv;
BUFG bg0(.I(clk2x), .O(clkfb));
BUFG bg1(.I(clkdv), .O(clk));
CLKDLL cd0(.RST(1'b0), .CLKIN(clki), .CLKFB(clkfb), .CLK2X(clk2x) );
always @(negedge clkfb) begin
clk90 <= clk;
end
always @(posedge clkfb) begin
if (reset) begin
clkdiv <= 8'd100;
end
else begin
if (wr)
clkdiv <= di;
if (clkcnt >= clkdiv)
clkcnt <= 8'd0;
else
clkcnt <= clkcnt+1;
end
end
endmodule
Article: 40302I need to design a multiplexer/demuliplexer. The multiplexer support 4 input serial ports each (TXD,RXD,RTS,DTR) all the signals are sended via a signle pairArticle: 40303
Hi, lapraveen@yahoo.com (praveen) wrote: > Can anyone suggest me a method of converting a vhdl netlist > in to either EDN or EDF Write out a Edif file with tool that creates your vhdl netlist and use Edn or Edf as Postfix. bye Th"there_are_too_much_tools_doing_it_to_remember_ise"omasArticle: 40304
Hello, We are working with a XSV800 board from Xess (XCV800 from Xilinx) and the Foundation 3.1i. The simulation and timing simulation of our project goes fine, but we all know that simulating is not the same as synthesising. We are using 3 dual port RAM blocks (256x8) and a number of adder and substracters in our design, all of them obtained via the CORE Generator. The Data Sheet for this version (3.1i) is pretty poor, and it doesn't specify the latency for the operators neither the chronograms for the memory blocks. We have supposed that the memories have a Write First policy (as in the 4.0 version) and that the operators have a latency of 0 (or 1 if registered output). The fact is that, once synthesized, these operators under these assumptions, don't work at all. We have set the board speed to 100Mhz: 1) Can these components work at this speed? 2) Which is their latency? 3) Where can I find some synthesizable code example with a CORE RAM block being read and written? Thank you very much for help.Article: 40305
"David de Andrés" wrote: > Hello, > > We are working with a XSV800 board from Xess (XCV800 from Xilinx) and the Foundation 3.1i. > > The simulation and timing simulation of our project goes fine, but we all know that simulating is not the same as synthesising. > > We are using 3 dual port RAM blocks (256x8) and a number of adder and substracters in our design, all of them obtained via the CORE Generator. > > The Data Sheet for this version (3.1i) is pretty poor, and it doesn't specify the latency for the operators neither the chronograms for the memory blocks. > We have supposed that the memories have a Write First policy (as in the 4.0 version) and that the operators have a latency of 0 (or 1 if registered output). > The fact is that, once synthesized, these operators under these assumptions, don't work at all. > > We have set the board speed to 100Mhz: > 1) Can these components work at this speed? > 2) Which is their latency? > 3) Where can I find some synthesizable code example with a CORE RAM block being read and written? > > Thank you very much for help. Which version of the Xilinx 3.x tools are you using ? i.e. which service pack level. ? There was a big revision to the BlockRAM timing that occurred with one of them (SP6 ?) which might make getting 100MHz out of a non-E Virtex problematic. As to synthesis/inference of BRAMs: This is in its infancy and only some synth tools support some modes. Full dual port synthesis is difficult since the most obvious template violates the Verilog "No reg assigned from more than 1 always block" rule.Article: 40306
I can wholeheartedly agree with the asynchronous FIFO statement - see the thread "stuck in state in Spartan-II!" for some convincing evidence! Ken > It is allowed, but having less clock domains is always good. Since virtex > has 4 global clock nets, this is no problem. When transfering datas between > these clock domains, do it clean, means by use of asynchronous FIFOs or > simmilar proofen methods.Article: 40307
This is a multi-part message in MIME format. --------------EF2E578CEA4EE2B5EEFC7F33 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Phil, Phil wrote: > David, > > you easily can reproduce the performance advantage over Virtex 2 by just installing Quartus 2 software from Altera together with an appropriate sybthesis tool (both, Synplicity's Synplify and Exemplar) and run your designs with Stratix selecetd as target device family. P&R already supports Stratix devices. Timing report is always some kind of estimation. Just remember when Xilinx introduces Service Pack 8 for its M3.1 software. It showed up that timing estimates were a lot worse than previously reported results. > That is exactly my point! If you trust the figures that it is giving you then fine....If it don't work in production - then you know the reason why! > > Any questions on that? > > regards > > PhilArticle: 40308
This is a multi-part message in MIME format. --------------666FE74AAEBADF5B3C6B9A45 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Falk, I have been using this method for years and if you check the documentation I think that you will find that this is the recommended way of treating multi-cycle paths. The TNM is always forward propagated to the next synchronous element, and as a result of the TIMESPEC that I added, this will control only the datapath, not the clock enable itself. The clock enable to logic timing will still be covered by the PERIOD constraint which is not shown for clarity, and is exactly the desired functionality. Dave Falk Brunner wrote: > "David Hawke" <dhawke@xilinx.com> schrieb im Newsbeitrag > news:3C833429.27285B2C@xilinx.com... > > Antonio, > > > > Attach a TNM to the Clk_enable net, and then apply it to the gouping. The > TNM will be > > forward propagated to all the synchronous elements attached to the net: > > > > NET clk_enable TNM = clk_en; > > TIMESPEC TS_multi_cycle = FROM clk_en TO clk_en 30; > > I dont think so. Since this is a CLOCK ENABLE signal, it must propagate > within 1 clock cycle, NOT 2,3 or more. The clock enable is NO multicycle > path. Only the data from one stage to another can have a propagation time of > more than one clock cycle (when using a multi-cycle path). > > -- > MfG > FalkArticle: 40309
John, You were spot on correct - phantom timing constraints have gone! Cheers, Ken "John_H" <johnhandwork@mail.com> wrote in message news:3C83B491.8773D84B@mail.com... > In my Synplify experience, I've found little reason to have the very general > timing constraints I specify in the Synplify tool to end up in the Xilinx flow. > To make sure this doesn't happen, the item to "generate vendor constraints file" > needs to be turned off within the Synplify environment. The option generates an > "ncf" file (I'm pretty sure that's the suffix) that could be deleted to avoid > the phantom timing for stuff you've already compiled. The Xilinx flow specifies > an order for constraint interpretation such that a ucf will override anything > stated differently in the ncf. Anything that's not respecified is kept.Article: 40310
Hello Ray, thanks a lot your post clarified things. Xilinx Core Generator cant put additional register on the EN signal, so the only thing is to instantiate a D flip-flop and put it in the right place? Regarding my project I have to arbitrate the access in 3 BRAMs (registered for the reason described above) so I think I must use a MUX_BUS from the CORE GENERATOR (one MUX_BUS for each BRAM). I will use 3 MUX_BUS with 3 input 41-bit buses (32 for the data, 7 for the address, 2 bits for EN,WE). If I use non-registered MUXs I think is not good for the following reasons: 1) The timing analysis will not include them in the period calculation so I will not be able to see if my FPGA meets the timing constraints 2) Combinatorial logic in the BRAM paths. Here is my second question, as I said before I am going to use registered BRAMs do you think that these registers are capable to cope with the inserted MUXs' combinatorial logic? I don't know if these MUXs I'll use can be described as "large" or "small" combinatorial logic. So the right thing to do is to use registered MUXs (LUT based only as Xilinx says)? Best Regards, Harris "Ray Andraka" <ray@andraka.com> wrote in message news:3C824FD0.71540235@andraka.com... > > > "H.L" wrote: > > > Hi Ray, > > I have seen these tips written by you many times in this group. I have them > > always as a guide but I want to see if I understand them right. Please > > correct me where I am wrong: > > > > 1) The need for additional registers in DATA_IN and ADDR signals. > > In BRAMs the EN and WE signals have long set-up times thats why we need to > > register the data_in and addr of the BRAM, in this way the addr and data_in > > signals have a clock period delay.As EN,WE reach the BRAM 1 clock period > > earlier (at 155MHz clock speed that means about 6 ns) the setup-time for > > these signals is not violated resulting BRAM to be in the operation mode we > > wish (read or write) the moment addr and data_in arrive. > > If you look at the data sheet, there are fairly long set-up times on all the > BRAM inputs. Routing to the BRAMs also adds to the delay, as does any > combinatorial logic on these inputs. The idea of putting registers on the > inputs (which includes the EN and WE inputs) is to minimize the amount of delay > added externally to these signals. Your understanding is a bit incorrect, as > what you are suggesting is delaying signals to allow a long combinatorial > delay. That is dangerous, because there is no guarantee on the minimum delay. > Instead, what I am suggesting is to remove as much of the delay as possible > between the registers driving the BRAM inputs and the BRAM inputs, which meahs > avoiding combinatorial logic on these paths, minimizing the fanout of these > signals, and physically locating the registers close to the BRAMs. > > > > > 2) The need for floorplanning > > Xilinx software tool maybe has put the additional registers far from the > > BRAMs, if this is the case we must manual place them near the BRAM to > > decrease the propagation delay of the signals. > > That is correct. Routing in FPGAs is not just wire, it also consists of > switches which add to the propagation delay of signals on the connections > between logic. Manually placing the registers near the BRAM helps to minimize > the added delay. > > > > > 3) Tying the WE,EN inputs and contol access through the address when working > > at high speeds. > > Do you mean to keep WE,EN high all the time and when we wish not to use the > > BRAMs to write dummy data in some (or just one) specified addresses (or > > address) reserved for this reason? > > That is correct. The set up times for EN and WE are nearly twice the set-up > times for address and data, so if we can eliminate these from the equation we > can run at a higher clock rate. They can be eliminated by always writing, but > directing the writes of invalid data to locations where it does not affect the > operation of the design. In the case of FIFOs, you can just park the write > address until you have a valid write, since you are presumably not reading that > data until it is valid. > > > > > > > Also I have another one question about BRAMs, Xilinx says that BRAMs' DATA > > OUT are already registered. In Xilinx Floorplanner I believe this register > > is "inside" the BLKRAM box so no manual floorplanning for the output is > > needed. You need to manual floorplan (in the same way you do for the inputs) > > only if you choose to add an additional output register, correct? > > That is correct, the BRAM acts as though it is registered, although I believe > the actual implementation has the register on the address, not on the memroy > outputs. In any event, the clock to out time is long compared to that of the > CLB flip-flops. The system clock rate can be increased by putting an additional > register on the BRAM data outputs and placing that register physically close to > the BRAM (that register should have no combinatorial logic in front of it). > > > > > > > I really appreciate your help. > > > > Best Regards, > > Harris > > > > "Ray Andraka" <ray@andraka.com> wrote in message > > news:3C7FD73D.F6A3109A@andraka.com... > > > VirtexE BRAMs can be written at 155MHz in any speed grade. To do so, you > > will > > > likely have to put registers near to and with no logic between them and > > the > > > BRAMs. Watch the loading too, routing to more than 1 BRAM for each > > register may > > > cause you some heartburn. At higher speeds, you probably should also > > consider > > > tying the WE, and ENA inputs active and controlling your access through > > the > > > address registers instead. You'll also need to floorplan the registers to > > make > > > sure they are located physically close to the BRAMs. > > > > > > "H.L" wrote: > > > > > > > Hi Peter, thanks for your reply > > > > I was confident of this method's effectiveness but now I am worried :)) > > . I > > > > have already done a timing analysis in the paper and also the simulation > > > > waveforms seem promising. > > > > I didnt understand what do you mean when telling me that one of my words > > > > arrives early and the other one late. The transmitter sends to my FPGA > > an > > > > external clock (thats the 155MHz clock), a valid signal (1 bit > > indicating > > > > the transmission time period) and of course the 16-bit words that I have > > to > > > > store. Every clock period (~6 ns) I have available in my ports one > > 16-bit > > > > word, I register two sequential words from the in port to a 32-bit > > register > > > > (31->16 the first incoming word, 15->0 the second one). Then , in > > another > > > > 32-bit register I register (2 nd time) the 32-bit word I just "made" > > which > > > > are the BRAM data_in. All the above operations are in a process that has > > in > > > > its sensitivity list the 155 clock. I write to the BRAM at 77MHz using > > the > > > > incoming clock divide by 2 using a DLL. BRAM input signals are assigned > > in > > > > the falling edge of the 77MHz clock so as to be before the rising edge > > (of > > > > the same clock) where the BRAM samples them. The write operations are in > > > > another process with the slow clock in its sensitivity list. > > > > The timing waveforms of the simulation are the same with the timing > > analysis > > > > in paper but does this is a valid hardware design technique? > > > > Thanks for your time and help! > > > > > > > > Best Regards, > > > > Harris > > > > > > > > p.s: thats a small part of my design. I use DLL because other parts need > > > > them (BUS_MUX e.t.c) , I tried to implement my whole design @ 155 MHz > > and I > > > > got many timing errors (floorplanning managed to reduce them but still > > lot > > > > of work to be done) > > > > > > > > "Peter Alfke" <peter.alfke@xilinx.com> wrote in message > > > > news:3C7E621F.1E77A244@xilinx.com... > > > > > I suggest you grab pencil and paper and do a clock-by-clock timing > > > > analysis. You > > > > > will find that your clock-speed reduction buys you nothing, unless you > > > > also > > > > > double-buffer the data. > > > > > One of your words arrives nice and early, the other one late. However > > you > > > > clock > > > > > the BRAM, one of the two words has the same old short set-up time... > > > > > Double-buffering would help. But Ray has mentioned some neat tricks to > > > > avoid the > > > > > long set-up time of the control inputs. > > > > > > > > > > I will get back with more constructive notes. "Gotta run" > > > > > > > > > > Peter Alfke > > > > > =================== > > > > > "H.L" wrote: > > > > > > > > > > > Hello all, > > > > > > > > > > > > I have a module that accepts 16 bit words at 155MHz and I want to > > store > > > > then > > > > > > in an 128x32 BRAM. I am going to use a DLL (in a Virtex-E FPGA) to > > > > divide by > > > > > > 2 the 155MHz clock as this frequency seems to be pretty high to > > write in > > > > the > > > > > > BRAM. So far I think 2 processes are enough to do my job, one > > operating > > > > @ > > > > > > 155MHz to accept the 16-bit data and store them in a 32-bit register > > and > > > > the > > > > > > another one @ 75MHz to write the content of the 32-bit register in > > the > > > > BRAM. > > > > > > I am thinking to assign the BRAM's signals > > > > (ENABLE,WRITE,ADDRESS,DATA_IN) in > > > > > > the falling edge of the 75MHz clock, the main reason for this is the > > > > setup > > > > > > time of the BRAMs signals (in this way the address,data are 6 ns > > before > > > > next > > > > > > rising edge of the clock where BRAM samples its inputs). My question > > now > > > > :) > > > > > > , if one process uses the falling edge of one clock does this causes > > > > > > problems to other processes in the design , e.g to processes that > > use a > > > > > > different clock or to processes using the rising edge of the same > > > > clock? > > > > > > > > > > > > Best Regards, > > > > > > Harris. > > > > > > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 40311
Hi everyone, I'm producing a trailing edge pulse from a clock and passing it straight out as an output port for testing purposes but some of the pulses are missing when implementing onto a FPGA. It works fine when simulating with Modelsim. The clock going into the FPGA is correct. Could it be a metastability issues? Any help will be great. Thanks Paul LeeArticle: 40312
Paul wrote: > > I use Quartus2 1.1 SP2 with LS 2001.1d and find that I use Leonardo to > control quartus command line for P&R. > > I didn't successfully get Q2 to control LS however > > However I also now use ActiveHDL and that controls the command line of both > LS (for synthesis) and Q2 for P&R OK. > > I would say I wasn't at all keen on trying the new LS until I hear some good > reports. > > Take a look at the problems left in. If they can't get library (LPM etc) to > work correctly in a release something needs fixing. LPM integration is such > a basic requirement of an Altera tool IMHO. > From the LS readme file: > 5. The LeonardoSpectrum-Altera Software Version 2002a.14 will not recognize > LPM instantiations in HDL as black boxes. This may result in one or more > of the following types of Error messages :- > ======================================================================= > Error : output port/net "<net>" of instance "<instance>" of cell > <blackbox> has no driver. > WARNING: output port is not driven -- <port_name> > > ======================================================================= > <followed by a script fix> > > Reports on Q2 v2 and LS2002 gratefully areceived. I'm using LS v2001_1d.24_OEM_Altera. It *does* utilize LPM black-boxes from your vhdl such as counters etc. Things like dual-port rams with separate read and write addresses aren't tho. However, black-boxing of these functions works if you first generate the files using the megawizard thing in maxplus2/quartus2.Article: 40313
Unit Manager wrote: > Hi Group, > > I already had some working knowledge of VHDL and Verilog but I would > like to get a book or some to guide me for (1) doing design for > complex systems AND > (2) picking up techniques to clear the dirty corners of HDL design > such as async behaviour, signal crossing clock domains, verification, > etc that are slightly or even not mentioned in most HDL intro books. > > I aware of two books for my next digital logic design reading. I would > like to get some review from experienced readers for recommendations: > > 1. "Real Chip Design and Verification Using Verilog and VHDL" > VhdlCohen Publishing, ISBN 0-9705394-2-8 > 2. "VHDL Coding and Logic Synthesis with Synopsys" by Weng Fook Lee > > Thanks, > > -pat. > Hi I can give a very interesting Internet link, it may help you to achieve whant you want. http://lsiwww.epfl.ch/LSI2001/HTML/4CTeaching.htm# and click on "Integrated Systems". Kind Regards Khaled NsaibiaArticle: 40314
Ray Andraka wrote: > That said, I am assuming you are talking about audio mixing. If that is the > case, you can get into a smaller, cheaper device by working with bit serial > arithmetic for the mixing. In that case, the multiplier is little more than > an adder. See the multiplier page on my website (when it comes back > up...seems the ball got dropped in transferring the domain name to the new > ISP so it may be a day or so before you can get to the website). Apart from audio mixing, I want to implement a digital EQ, but I assume that doesn't make any difference for the multiplier? Thanks for the reply, Remco PoelstraArticle: 40315
When using Xilinx, I find it enlightening to have a look at the .pcf-file. In this case your timing group seems to end up with just the IOB in it. This is becasue you should specify TNM_NET instead of TNM when dealing with an input port. Having a clock_en as an input port in the top-level design is not that common, though. NET clk_en TNM_NET = clk_en; TIMESPEC TS_multi_cycle = FROM clk_en TO clk_en 30; Should do the trick. Yours, Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 40316
Dear FPGA experts,
I want to write synopsys library file (.lib) for FPGA.
Usually XILINX and other FPGA companies support
Synopsys db file, but the target I want is to generate Synopsys
db file from .lib file.
I have written the following library file.
> library (si03) {
> technology ( fpga ) ;
>
> ...
> cell(LUT2) {
> area : 1.000;
> pin(I0) {
> direction : input;
> capacitance : 1.0000;
> }
> pin(I1) {
> direction : input;
> capacitance : 1.0000;
> }
> lut(L) {
> input_pins : "I0 I1";
> }
> pin(Z) {
> direction : output;
> function : "L"
> capacitance : 1.0000;
> }
> }
>
and it was successful to convert it to .db file.
When I have tried to synthesis my simple design,
the error messages from fpga compiler(from Synopsys) came out.
> ------------ Message from dc_shell-------------
> Error: Target library must contain a usable N-input lut cell. (OPT-910)
> Error: Compile terminated abnormally. (OPT-100)
> Current design is 'TEST1'.
> 0
It means that there are problems in LUT description.
How can I describe LUT in .lib file?
--
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Young-Su Kwon
Ph.D Student
VLSI Systems Lab., KAIST
yskwon@vslab.kaist.ac.kr
-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
Article: 40317trying to do a just another conversion function. My compiler tells me "Array case expression must have a static subtype" . does it really mean i have to use "if ... elsif ... elsif ... " instead of "case" ? This is not for synthesis, just used in the testbench, to convert SLVs to strings in hexadecimal. thanx, matthiasArticle: 40318
all, Has anybody found a good method for implementing designs using the Xilinx 4.1 ISE (under windows) that require more than 2GB of memory for the place and route? I have read that Xilinx now supports their tools running Linux (using WINE). Does this new method allow users to exceed the 2GB limitations or is this a function of application executable? We are looking to complete an upcoming design that may require a Virtex 2 (xc2v8000) and xilinx recommends that you need at least 3 GB of memory for place and route. What are most people doing to overcome this? Are there any relatively cheap unix based machines ($<10,000) that can accomplish this? Any recommendations would be greatly appreciated. Thanks in Advance, Mike Schreiber hardware engineerArticle: 40319
Jay wrote: > Come on down to the CA (California that is), I have head hunters > calling all the time... Why is that? I have noticed that while the Silicon Valley is still dead I am getting calls from pondscum headhunters claiming jobs in Orange County. Is it related to the defense industry? Tom > > > "Albert" <wagain@hotmail.com> wrote in message news:<01kf8.239995$I8.48176768@news4.rdc1.on.home.com>... > > Hi, > > > > I have many years of experience on DSP/embedded system and FPGA/CPLD design. > > I'm in Vancouver and looking for jobs. If the company you work for has any > > opening or you know any job opportunities that my skills fit, and your > > information finally leads to my job, I will be glad to share half of my > > first two months' net income to you. I guarantee it. I will be glad to > > relocate to other cities in Canada. It is double wins, for me, I got a job > > and sharing my half of salary to you is absolutely no problem, and for you, > > that position you know will doom to be filled by someone finally, why don't > > you do me a favor? > > > > I appreciate any reply. My email address is: wagain@hotmail.com. > > > > > > Thank you for your time. > > > > AlbertArticle: 40320
Hi, I need to design a digital PLL to fit in a small FPGA or CPLD. This PLL should lock on a video H-sync which has a period of 64us. Could anyone please give me some hints on how to get started with it ? Many thanks, Guy.Article: 40321
We are using the: Xilinx Foundation F3.1i Build 3.1.177 But I am not sure where to find the Service Pack level. In some help file I have found the following data: Service Pack 5-6a With respect to the operators, how can I be sure when the output data is ready? It can not take the same time to add/substract 2 bits numbers than 18 bits numbers. Thanks.Article: 40322
We have Linux support now.....nice low cost way to break out of the 2Gbyte limit of Windows on PC platforms. Dell supports a 4Gbyte memory, that could be used by Linux. http://www.xilinx.com/prs_rls/software/0225_Em_Linux.html Austin M Schreiber wrote: > all, > Has anybody found a good method for implementing designs using the > Xilinx 4.1 ISE (under windows) that require more than 2GB of memory > for the place and route? I have read that Xilinx now supports their > tools running Linux (using WINE). Does this new method allow users to > exceed the 2GB limitations or is this a function of application > executable? We are looking to complete an upcoming design that may > require a Virtex 2 (xc2v8000) and xilinx recommends that you need at > least 3 GB of memory for place and route. What are most people doing > to overcome this? Are there any relatively cheap unix based machines > ($<10,000) that can accomplish this? Any recommendations would be > greatly appreciated. > Thanks in Advance, > Mike Schreiber > hardware engineerArticle: 40323
In article <3C84CD6B.8144AC5D@lucent.com>, Matthias Wenzel
<wenzel@lucent.com> writes
>trying to do a just another conversion function.
>My compiler tells me "Array case expression must have a static subtype" .
>
>does it really mean i have to use "if ... elsif ... elsif ... " instead of
>"case" ?
>
>This is not for synthesis, just used in the testbench, to convert SLVs to
>strings in hexadecimal.
>
>thanx,
>matthias
If you are using Modelsim, you can disable the error in the Modelsim.ini
file.
If you want to write to a file, there's a hex write routine in the
Synopsys package
std_logic_textio
Alan
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Article: 40324M Schreiber wrote: > > all, > Has anybody found a good method for implementing designs using the > Xilinx 4.1 ISE (under windows) Which windows ? win2k, nt4, or what ? They are different ... > that require more than 2GB of memory > for the place and route? I have read that Xilinx now supports their > tools running Linux (using WINE). Doesn't help you here ... > Does this new method allow users to > exceed the 2GB limitations or is this a function of application > executable? We are looking to complete an upcoming design that may > require a Virtex 2 (xc2v8000) and xilinx recommends that you need at > least 3 GB of memory for place and route. There is/was a special version of NT4, supporting 3 GByte User space > What are most people doing > to overcome this? Are there any relatively cheap unix based machines > ($<10,000) that can accomplish this? Any recommendations would be > greatly appreciated. No recommendations. Just more questions ... ;-) cheers
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