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Edwin Naroska <edwin@nospamthisaddress.either..de> wrote: > Hi, > You may take a look at part 3 section 5 of the VHDL FAQ > (http://www.vhdl.org/comp.lang.vhdl/). It lists some free > and commercial VHDL <-> Schematic/FSM Translators. Thanks Edwin but I meant a program that allows me to make "black-boxes" out of my VHDL and then use standard primatives like NAND2, OR2, etc and graphically hook it up. As the other posted said one could make these components in Renoir and then hook it up, but that defeats the purpose... Thanks.Article: 27251
this VHDL code will still give you a glitch on the output (pin?) of the register flop. in first instance the flop will probaly be reset by the global reset line of the FPGA??? and on the first clock edge it will set. so maybe problems?? regards ron proveniers Keith R. Williams <krw@btv.ibm.com> schreef in berichtnieuws 3A13EDE8.2AE0A699@btv.ibm.com... > > > Peter Lang wrote: > > > > Hi, > > by default FGPA Express will init all Registers in my Spartan device to > > zero. > > How can I change this default? > > When doing schematic entry this was easyly done by adding "INIT=S" > > But how can I do this with VHDL? > > Try: > > signal widget: std_logic_vector(7 downto 0); -- my register > > Reg: process (Clk,Reset) > begin > if Reset = '1' -- If asynchronous reset > then widget <= (others => '1'); -- then set flop to one > elseif rising_edge(Clk) -- else if clock > then -- then whatever > ... > end if; > end process; > > ---- > KeithArticle: 27252
hi, the xilinx parallel cable III also works at 3.3V regards, Guy.Article: 27253
Eric Smith wrote in message ...
>"Geoffrey G. Rochat" <geoff.nospam@nospam.pkworks.com> writes:
>> Given the slow speed of ISA
>> transactions LS-TTL speeds are adequate.
>
>Depends. If you're trying to do 0-WS I/O, the 74LS is too slow for
>some of the signals. This is due to poor design of the ISA bus; the
>time to decode the address and assert the necessary signals is very
>short. (It's been a few years, so I don't recall the exact details.)
>
Sorry for the delayed response, but I've been digging through my
library, trying to re-find just those details of which you wrote, having
tripped over exactly this point myself many years ago. This is becoming
part of forgotten engineering lore, but it's still worth bringing up.
On pg 167 of Solari, Edward, "ISA & EISA Theory and Operation",
Annabooks, 1992, ISBN 0-929392-15-9, is the following sidebar:
"The original IBM AT running the BCLK signal line at 8 MHz cannot
support ISA or E-ISA no-wait-state cycles... ...the add-in card has -5
nanoseconds to drive the SRDY* {aka 0WS/, my comments} signal line...
...Very few no-wait-state add-on cards have been built."
So, you're right, the decode time for 0 wait state cards is very short.
In fact, in some machines it's negative. This makes it impossible, at
least on those machines, to design 0 wait state cards irrespective of
the logic family used. On a bus as sloppy as the ISA I stuck to very
conservative design philosophies, and never tried for 0 wait state ISA
cards for this very reason. I didn't want to have to explain to people
that it wasn't _my_ fault my design worked in some PCs and not in
others. People don't really want to be told that the Super-Turbo Mega
Server Wizzi-Doo PC they just bought from a Big Name Manufacturer is,
from an engineer's perspective, really a cruddy piece of expensive junk.
Sometimes Truth doesn't go over well, don'tchaknow.
Article: 27254No Keith is right. The GSR is supposed to use the user asynchronous set or reset. In this case, it is SET. So the FF will be stated to '1' after the configuration. Regards OlivierArticle: 27255
Ron Proveniers wrote: > > this VHDL code will still give you a glitch on the output (pin?) of the > register flop. in first instance the flop will probaly be reset by the > global reset line of the FPGA??? and on the first clock edge it will set. so > maybe problems?? Huh? No, the flops can be asynchronously set or reset as required, with no glitches. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27256
Qian Zhang wrote: > > now I plan to setup my Spartan S40PQ240 pins, > > but check syntax says: > > "pinnum not declared " > > can anyone tell me how to define the FPGA pins > > to the corresponding input and output? Assign the pins in the UCF file. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27257
"S. Ramirez" wrote: > > I just found out that Synopsis wants $80K for a one year license of > their Mot 5307 or 8260 instruction set model! I consider this an ARM and a > leg!! That's ludicrous! I wonder how many licenses Synopsys has sold? > My client will never go for this. I guess I'm back to just simulating > the FPGAs and memories on the board, unless one of you out there knows of a > cheaper alternative. It may be worth your while to spend a week or so writing a model of the 5307. All it really needs to do is drive the busses and strobes at the proper time, in response to a "program." For "small" programs, I just have a little table in the code. For larger ones, I read the "program" from a file. I use VHDL records for each cycle. Use procedures for things like "bus read" and "bus write" and "interrupt ack" and so forth. I'd write it so that it's a unit-delay model, and have some way of adding real-life prop delays for post-FPGA-route timing sim (generics are good!). The timing model would probably also take setup and hold times into account, as well as checking to make sure the clock isn't too fast, and such. Maybe you could sell it to Motorola and make back your investment! I started to do a 5206e model but the project got put on the back burner. I did something similar with this Cypress VMEbus chip set I used. I'd send you that model if it wasn't an embarrassing mess. (I bought a copy of Janick Bergeron's book and now I hate all of my test benches!) -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27258
Three years ago I wrote here that FPGA-based single-chip MIMD multiprocessors were becoming feasible. I have now placed-and-routed a toy/proof-by-example 8-way multiprocessor-on-a-chip. I simply took the "work-in-progress" GR0000 compact 16-bit RISC core, which is now floorplanned as 8 rows by 6 columns of CLBs, plus two block RAMs (for a byte-addressable 16-bit wide 1 KB dual-ported embedded instruction/data memory), and instanced eight of them as 2 rows by 4 columns of processors plus memories, in the smallest Virtex-E part, the 16x24-CLB, 4x4 block-RAM XCV50E. More details, including a floorplan diagram, are at www.fpgacpu.org. So here's a rule of thumb, approximately correct. Take a Virtex-E data sheet, look up the number of block RAMs, divide by 2 (4) and that's how many streamlined 16-bit (32-bit) RISC CPUs will fit in that device. In larger devices, with 12 columns of CLBs per column of block RAM, it may be possible to double that number again, or else use the remaining 50% of the programmable logic for other purposes, like cache control, CPU interconnect, and custom datapath functions. For example, in an XCV600E, which has 12 rows x 6 columns of block RAMs, you get 36 16-bit RISCs with 50% uncommitted CLBs. Whether such a thing can run full out without melting into slag remains to be seen! Looking way ahead, there will be lots of interesting work to come, in memory architectures, interconnect architectures, programming models and tools, etc. Jan Gray, Gray Research LLCArticle: 27259
Then the only way to do this is to identify the TBUF instances in your wild carding. If for example you know that the all the TBUFs have an instance name that matches the string --> "top/transmit/block/*tbuf*" then you could create two constraints (the order in the UCF file DOES matter). INST "top/transmit/block/*" LOC=CLB_R1C22:CLB_R20C59; INST "top/transmit/block/*tbuf*" LOC=TBUF_R1C22:TBUF_R20C59; If there is no way to currently pick out the TBUFs by their instance name then you would need to either instantiate BUFTs in your hdl, make your BUFT inference in a seperate hierarchial HDL module and indicate to your synthesis tool to maintain the hierarchy, or floorplan the BUFTs using the floorplanner. Generally I don't floorplan BUFTs unless I have instantiated them, and know the name isn't going to change when I resynthesize. Cheers, Tom Utku Ozcan wrote: > Tom Branca wrote: > > > > Hello Utku, > > I think I would use the area group constraints in this situation, > > rather than the LOC range constraints. Area groups allow you to define > > groups of logic by assigning logical instance to a specific area group, > > then you can assign this area group to a specific range in the device. > > There is more flexibility with area groups because you can specify the > > type of resource that you want constrained to the area via the RANGE > > constraint. I have included some syntax and usage information for the > > area group constraint below. > > > > Cheers, > > Tom > > Tom, > > thank you for your response. > > The AREA_GROUP is not supported by M2.1i SP6. As I stated > in my first posting, I am using M2.1i SP6. > > UtkuArticle: 27260
I have found that after upgrading to the latest service packs for Xilinx Alliance M3.2i and coregen I am no longer able to generate any multiplier core: ERROR: Error locating library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. ERROR: Error loading library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type ERROR: Could not load/define class file com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com ERROR: Sim has a problem implementing the selected core. Implementation netlist will not be generated. ERROR: SimGenerator: Failure of Sim to implement customization parameters core multhaccko ERROR: Core multhaccko did not generate EDIF implementation netlist (.EDN) file. WARNING: Warnings and/or errors encountered while generating multhaccko (Multiplier 2.0) All output products requested may not have been generated. ERROR: Elaboration failure for core Multiplier ERROR: Elaboration of core Multiplier failed. Xilinx tech support has already been alerted. Does anyone know a cure for this? Thanks, -ArrigoArticle: 27261
this is a test. sorry.Article: 27262
Daniel Hanczewski wrote: > > Hi all, > > I am rookie in programmable logic and I have just started getting in > this subject. > My question is: what is the difference between PLD, CPLD and FPGA? If I > have a logical circuit and want to implement it in programmable chip > what circumstances should I consider to choose a proper kind of chip? Is > it so that PLD and CPLD are used for large combinational projects while > FPGA are used for register-based circuits? > > Thank you in advance. > DanielArticle: 27263
Article: 27264
I post a question here... anybody know if fpga support float point calculation? thanx. jyArticle: 27265
dempson@actrix.gen.nz (David Empson) writes: > Well, let us start with the well known mathematical properties of a > correctly implemented 16-bit CRC (e.g. CRC-CCITT or CRC-16), courtesy of > Tanenbaum. It will detect errors as follows: > > - All single bit errors (as does a simple checksum) > - All double bit errors > - All errors with an odd number of bits > - All burst errors of 16 bits or less > - 99.997% of 17 bit burst errors > - 99.998% of 18 bit or longer burst errors Some of those claims (specifically the double-bit and odd-number-of-bits) are only true if the block size is below a maximum. I don't know offhand what the maximum is, but it's under 65536 bits. Proof left as an exercise to the reader.Article: 27266
Hello Thomas, I searched the online 3.2.04i documentation and could find no usefull documentation of the AREA_GROUP constraint, or the AREA_GROUP keyword. Or COMPRESSION. Or RANGE. Just one hit, on an example MAP report. Could you please file a case with Xilinx to have the documentation fixed. Philip Freidin On Wed, 15 Nov 2000 10:32:47 -0800, Tom Branca <thomas.branca@xilinx.com> wrote: >Hello Utku, > I think I would use the area group constraints in this situation, >rather than the LOC range constraints. Area groups allow you to define >groups of logic by assigning logical instance to a specific area group, >then you can assign this area group to a specific range in the device. >There is more flexibility with area groups because you can specify the >type of resource that you want constrained to the area via the RANGE >constraint. I have included some syntax and usage information for the >area group constraint below. > >Cheers, >Tom > >---------------------------------------------------------------------------------------- > >The area group constraint when used in the UCF or NCF has the following >syntax. > >INST <logical_block> AREA_GROUP = <group_name> ; > ><logical_block> - Name of logical block assigned to group <group_name>. >If the AREA_GROUP constraint is attached to a hierarchical block, all >the children in the block are assigned to the group. > ><group_name> - This is the name of the area group and is used to >uniquely define a group. > >In addition to the INST command, AREA_GROUP can be used as a separate >command to define a range and compression factor for an area group as >follows: > >AREA_GROUP <group_name> RANGE=<range>; > >AREA_GROUP <group_name> COMPRESSION=<percent>; > ><range> - Defines the physical area for <group_name> using RLOC_RANGE >syntax. The site names for Virtex and VirtexII are as follows: > > CLB/Slice Constraint: CLB_RnCm > Block RAM: RAMB4_RnCm > TBUF: TBUF_RnCm > > >The constraint will only apply the range to a logical block if it of the >appropriate type (e.g. LUTs and FLOPs get CLB range and TBUFs get TBUF >range). > ><percent> - Defines the compression factor for <group_name>. This is >equivalent to -c option in map but operates on the group instead of the >whole design. The mapper computes the available resources in the group >from the <range> and attempts to compress the logic to the percentage >specified. The percent values can be from 0 to 100. If the group does >not have a RANGE, only 0 (no compression) and 1 (maximum compression) >are meaningful. >Compression does not apply to TBUFs or block RAMs. > ><group_name> - Name of area group. The mapper will generate an error >if an RANGE or COMPRESSION command is specified and there is not a >corresponding area group <group_name> defined in an INST command. Philip Freidin FliptronicsArticle: 27267
"J.Niu" wrote: > > I post a question here... anybody know if fpga support float point > calculation? thanx. Yes. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27268
Yes, but it will cost you more area per function, especially for add/subtract. Of course, you or someone will have to design the floating point hardware just as you would any other hardware to be put in the FPGA. "J.Niu" wrote: > > I post a question here... anybody know if fpga support float point > calculation? thanx. > > jy -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27269
This question was previously asked and answered in 1999 -- see www.fpgacpu.org/usenet/fp.html. Jan Gray, Gray Research LLCArticle: 27270
What questions do you have? For FAQ and Tutorials visit http://xup.msu.edu. http:// xess.com offers example projects and a users forum that may be of assistance. djley wrote: > Would some one be interested in answering questions on this software. > I'm not a student but would like to learn and there is no support for this > product by Xilinx. -- ***************************** Anna M. Acevedo Xilinx University Program 2100 Logic Drive San Jose, CA 95124 PH: (408) 879-5338 FAX: (408) 879-4780 Email: anna.acevedo@xilinx.com http://www.xilinx.com/programs/univ.htm *****************************Article: 27271
Hi, Is there a model of the AT6010 that uses a 3.3V core and has 5V tolerant I/Os? I looked around and couldn't find one; but I'm not sure that I have all the documentation (used old data books and www site - perhaps I missed something). Thanks! rkArticle: 27272
I hope this will not get interpreted as "marketing" and be flamed: The upcoming Virtex-II family will be far more efficient, thanks to a large number of 18 x 18 2s-complement multipliers ( a few ns prop delay) that, of course, can also be (ab)used as shifters, thus dramatically reducing the logic and the interconnect for a floating-point application. Peter Alfke, Xilinx Applications ======================================= Ray Andraka wrote: > Yes, but it will cost you more area per function, especially for add/subtract. > Of course, you or someone will have to design the floating point hardware just > as you would any other hardware to be put in the FPGA.Article: 27273
As I read your question, I believe you are asking why the Spartan device doesn't program from the PROM device. You observe the INIT did not go low, indicating a failure. But DONE doesn't go high. When you generated your bitstream, sync the startup to the user clock, not the JTAG clock (bitgen). The Spartan cannot be programmed from the PROM if the bitstream is defined to sync up with the TCK clock. > Hello!!! > > Iīm student and I still working on my diploma. In addition to the line up of > my hardeware, I need support for configuring the JTAG-chain. > My Boundary-Scan chain is built up with a Spartan XCS40 and an ISP XC18V512. > The configuration of the FPGA via the ISP is established, but the direct > JTAG download with the parallel Xilinx cable (required for JTAG-Programmer > with XC18V00 devices) doesnīt work. Whenever I try to download the following > messages appear: > > JTAGProgrammer:Release WebPACK 3.2WP3.x - JTAG Boundary-Scan Download D.23 > Copyright:1991-1999 > JTAG Programmer Started 2000/11/16 10:37:06 > Loading Boundary-Scan Description Language (BSDL) file > 'xc18v512_so20.bsd'.....completed successfully. > Loading Boundary-Scan Description Language (BSDL) file > 'C:/Xilinx_WebPACK/spartan/data/xcs40_pq208.bsd'.....completed successfully. > Checking boundary-scan chain integrity...done. > Verifying device positions in boundary-scan chain... > Instance 'design_level_1_fpga4(Device1)' at position '1'...verified. > Verification completed. > Boundary-scan chain validated successfully. > 'design_level_1_fpga4(Device2)': Checking boundary-scan chain > integrity...done. > 'design_level_1_fpga4(Device2)': Reading bit-stream file...done. > 'design_level_1_fpga4(Device2)': Programming device.....done. > 'design_level_1_fpga4(Device2)': Programming completed successfully. > > Oh fine, it should work, but on my hardware, the DONE-pin never changes to > HIGH (also no changes on /INIT). The input TDI receives data via the TDO of > the XC18V512. > By the way, the JTAG-Programmer canīt read the ID from the Spartan FPGA. > Whatīs wrong? Is that the reason for the failure? > > Christian > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27274
I installed the latest IP two days ago without incident, and it simulates fine. Sounds like you need to compile the library, and if that has been done, make sure it is mapped to your simulator. You also may have to put the edfs in the projects you updated. There are some step by step install instructions and compile scripts on the xilinx website that make the whole thing easier. Arrigo Benedetti wrote: > > I have found that after upgrading to the latest service packs for > Xilinx Alliance M3.2i and coregen I am no longer able to generate > any multiplier core: > > ERROR: Error locating library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. > ERROR: Error loading library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type > ERROR: Could not load/define class file com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. > ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com > ERROR: Sim has a problem implementing the selected core. Implementation netlist will not be generated. > ERROR: SimGenerator: Failure of Sim to implement customization parameters core multhaccko > ERROR: Core multhaccko did not generate EDIF implementation netlist (.EDN) file. > WARNING: Warnings and/or errors encountered while generating multhaccko (Multiplier 2.0) All output products requested may not have been generated. > ERROR: Elaboration failure for core Multiplier > > ERROR: Elaboration of core Multiplier failed. > > Xilinx tech support has already been alerted. Does anyone know a cure for this? > > Thanks, > > -Arrigo -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
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Compare FPGA features and resources
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