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Yes, the XSE 2.1i in the Wakerly's Digital Design: Principles and Practices book is the same as the standalone Xilinx Student Edition 2.1i by Prentice Hall The Xilinx Student Edition software is available in several Prentice Hall books For a list of XDS (Xilinx Design Series) books visit http://vig.prenhall.com/ and do a catalog search, key work Xilinx Anna Guest Internet User wrote: > I was in Irvine ScitechBooks, today, looking for Xilinx Student Edition > 2.1i. (The website www.scitechbooks.com doesn't show it as stocked, but > I've learned from the retail store workers that the website and store > inventory are separate entities.) I came across Wakerly's "Digital > Design:Principles and Practices" (third edition, ISBN: 0137691912) > > The book was bundled with Xilinx Student Edition 2.1i. I was surprised > to see 2.1i bundled with a book published back in 1999, but the pricetag > sticker showed a date code of '09/00' (meaning Scitech > received/processed it this month.) The book was shrinkwrapped so I > couldn't even open it, but the back of the book had a blue cardboard > envelope package labeled "Xilinx Student Edition 2.1." > > Does anyone know if this is the same software as the standalone Xilinx > Student Edition 2.1i by Prentice Hall? Seems like the standalone > package is hard to find. -- ***************************** Anna M. Acevedo Xilinx University Program 2100 Logic Drive San Jose, CA 95124 PH: (408) 879-5338 FAX: (408) 879-4780 Email: anna.acevedo@xilinx.com http://www.xilinx.com/programs/univ.htm *****************************Article: 25901
Nial Stewart wrote: > > I'm about to order bits to build a PC for FPGA simulation/ > compilation/PAR. > > I'm going for a 750M Althlone Thunderbird on an Asus A7V motherboard > with > 256M memory (to start), a 15G IBM ATA100 hard drive with a > Yamaha 8x8x24 CD-WR for project documentation. > Any comments? I get along "fine" with a PII/333 with a PIII-650 in the "background" for PAR. Synplify and ModelSim work fine on a PII/333 w/192K. In fact Synplify is almost acceptable on my P120 - zero L2 laptop. However, Foundation 3.1i sucks a system to its knees for hours sometimes (even with 640MB of RAM) so I have a separate system for PAR. I put the "background" system in the lab with and also use it for debug, simulators, EPROM programmer, and such. > I've been thinking about buying a Matrox G400 video card with > dual output as I was thinking that it would be very handy to > be able to view a modelsim wave window on one monitor, with > all the other modelsim windows on another one. > > Has anyone tried this? I know that windows98 supports dual > monitors, but does the application software have to support > them too, or does it jut create more desktop on the second one? This system has two Matrox Mystique Business/220s for dual screen in a "KeithKit" with the above PII/333. I have a 20" on the left and a 19" to the right (well, they were available ;-). The setup essentially gives me one 2560x1024 (2 x 1280x1024)desktop under NT4. It works very nicely. There is some strangeness with messages wanting to go to the center (across the split between the monitors) and windows that refuse to remember where I put them last, but it is a very nice setup. Running simulations on one screen while compiling or looking at schematics (with Synplify) on the other is very nice! Cut-n-paste to get entities and mappings right is really nice too. ---- Keith Sender: eric@ruckus.brouhaha.comArticle: 25902
Does anyone have a simple explanation of the differences between Foundation Base ($1090) and Foundation ISE Base Express ($695)? They both seem to support the same devices (except for the XC3000 and XC5200 series)? Does Foundation Base not support VHDL? And how do those packages compare to the student edition 2.1i, which Amazon lists for $55? I can't even *find* a supported device list for the student edition. The Xilinx marketing people must have worked long hours and legal holidays to make sure that it's difficult to get useful information from their web site. They reference comparison charts that are "currently not available." I want to do VHDL design using Spartan and Spartan II parts, and I'd like to get started as cheaply as possible.Article: 25903
I don't know what is in the Student Edition. They keep that under pretty close wraps. But here are the two pages the tell you what is in the ISE and the Foundation packages... http://www.xilinx.com/products/foundise.htm http://www.xilinx.com/products/found.htm If you can get Xilinx marketing to focus on providing data rather than the glossy info-deprived web pages and literature you will be a better man than I. Xilinx has done this for years. I remember opening the first Dynabook searchable data book only to find an incredible multi-layered graphic that took over a minute to draw each time I started it up or came back to the main page. They get beat up about things like this and correct them. But nobody does anything about the guy that keeps making new problems. So they add a lot of silly, useless and time wasting stuff to the install script or to the web pages or to anything else they think they can use to brainwash you into using their parts... instead of just giving you the information that will let you see how their part fits perfectly into your design. Can you tell that I am having a bad day? Eric Smith wrote: > > Does anyone have a simple explanation of the differences between > Foundation Base ($1090) and Foundation ISE Base Express ($695)? > They both seem to support the same devices (except for the XC3000 and > XC5200 series)? Does Foundation Base not support VHDL? > > And how do those packages compare to the student edition 2.1i, which > Amazon lists for $55? I can't even *find* a supported device list > for the student edition. > > The Xilinx marketing people must have worked long hours and legal > holidays to make sure that it's difficult to get useful information from > their web site. They reference comparison charts that are "currently > not available." > > I want to do VHDL design using Spartan and Spartan II parts, and I'd > like to get started as cheaply as possible. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25904
Hi, May i know how to get the free core that U mention? thank you regards, chew "Scott Thibault" <thibault@gmvhdl.com> wrote in message news:8qfo69$rf4$1@slb7.atl.mindspring.net... > Hi Ray, > > VHDLStudio is only required to run the included HC11 debugger. The core is > in standard VHDL which can be simulated and synthesized with any standard > tool. > > Regards, > --Scott Thibault > Green Mountain > Computing Systems, Inc. > > "S. Ramirez" <sramirez@deleet.cfl.rr.com> wrote in message > news:ETIy5.20208$W45.2292373@typhoon.tampabay.rr.com... > > Ray, > > I agree that this is a substantial amount of effort, but the site > does > > say that you need VHDL Studio. I do not know why it is needed, but this > > could explain why the core is free. This could be an example of bait and > > switch. Depending on the price of VHDL Studio, this could be a "gift > > horse," too, as you say. > > -Simon Ramriez, Consultant > > Synchronous Design, Inc. > > > > > > > > "Ray Andraka" <ray@andraka.com> wrote in message > > news:39CB52F5.9DDCB49C@andraka.com... > > > Evan, his website tells all. He's apparently sythesized it to Altera > > 20K100 and > > > Virtex400E, both of which ran at about 31-32 MHz. One could probably > > double the > > > speed and cut the size by a considerable amount by tailoring the design > to > > a > > > specific part, but hey this ain't bad and who's to look a gift horse in > > the > > > mouth? > > > > > > Nice piece of work, and a substantial amount of effort to give away. > > > > > > > > > eml@riverside-machines.com.NOSPAM wrote: > > > > > > > > On Thu, 21 Sep 2000 10:17:19 -0400, "Scott Thibault" > > > > <thibault@gmvhdl.com> wrote: > > > > > > > > >We have a synthesizable HC11 CPU core available for download. See > > > > >http://www.gmvhdl.com/hc11core.html for details. > > > > > > > > > >--Scott Thibault > > > > >Green Mountain > > > > >Computing Systems, Inc. > > > > >http://www.gmvhdl.com > > > > > > > > Very nice. Have you done an FPGA implementation? Do you know how > > > > big/fast it is? > > > > > > > > Evan > > > > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com or http://www.fpga-guru.com > > > > > > > > >Article: 25905
Hi, Do anyone have resources or related material regarding the PPP point to point core development in fpga using vhdl. thanx. regards, HewArticle: 25906
Scott,
Is there a list of errata for this core?
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Scott Thibault" <thibault@gmvhdl.com> wrote in message
news:8qd59o$iom$1@slb3.atl.mindspring.net...
> We have a synthesizable HC11 CPU core available for download. See
> http://www.gmvhdl.com/hc11core.html for details.
>
> --Scott Thibault
> Green Mountain
> Computing Systems, Inc.
> http://www.gmvhdl.com
>
>
>
>
Article: 25907
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Article: 25908Forward error correction (FEC) can be realized in ASSP, for example AHA, in ASICs and in FPGAs. Does anyone know What are the key advantages of realizing Viterbi Decoder and Reed Solomon Decoder in FPGAs, in terms of speed and cost. Of course flexibility is the inherent feature of FPGAs. Thanks in advance. Regards, Shahzad Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25909
Hi, Marc. You can do this: output_pin <= 'Z' when desired_output = '1' else '0'; This casuses the output pin to mimic Open-Collector behavior, and the pull- up resistor that you install external to the chip is responsible for your TTL '1' (5v). The place-and-route tools will know that this uses a tri-state output buffer. HTH, Kent. -- Marc.Battyani@fractalconcept.com (Marc Battyani) wrote in >I've seen on the Xilinx web an application note (vtt002.pdf) where they >use a pull-up resistor to 5V and use the input to put the output in 3 >state when it has reached a 3.3V 1 level. (not very clear description. >i't better explained in the AN) > >How can I use this in VHDL? I use this output as a 3-state bus. >Should I instanciate an OBUFT gate or is there a more clever way to do >this? > >Thanks > >Marc Battyani > > >Article: 25910
Hi all, in my design, i am using Xilinx virtex 1000E and design operates at two clock frequencies (100Mhz one side and 62.5 Mhz on the other side). The design contains more than 16 FIFO (async.FIFO). The design doesn't meet the timing requirements(10ns). So i instantiated DLLs(CLKDLLHF).Then also the clock skew is more. i have some doubts, 1.How to reduce the RAM setup time timing violations and how to control the clock skew. 2.What is the use of DUTY_CYCLE_CORRECTION constraint and how to use it. 3.What is the use of NODELAY constraint and how to use it properly.Will it improve the DLL performance?. 4.In the FIFO the write clock frequency (100MHz) is more than the read clock frequency(62.5MHz).How to set delay constaint for this. could anybody suggests me? thanks in advance, sivakumar.s Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25911
Thank you! I don't suppose Xilinx could also update their webpage, to announce the availability of XSE 2.1i? The webpage still lists 1.5. And after double checking the book title "Digital Design:Principles and Practices", I'd like to add a correction. The full title is Digital Design:Principles and Practices, Updated Edition" (3rd edition) The original third-edition comes with XSE 1.5, apparently. > Yes, the XSE 2.1i in the Wakerly's Digital Design: Principles and Practices > book is the same > as the standalone Xilinx Student Edition 2.1i by Prentice Hall > > The Xilinx Student Edition software is available in several Prentice Hall > books > For a list of XDS (Xilinx Design Series) books visit > http://vig.prenhall.com/ > and do a catalog search, key work XilinxArticle: 25912
What you need to do is to use OBUFT to create a open-drian output. When you need to drive a logic 0, the output buffer will drive it low, if you need a logic 1, the output buffer will be tri-state and the external pull-up will do the job. In your vhdl code, you can do: output <= '0' when (oe = '0') else 'z'; So, when oe is 0, output will be 0, and vice versa.Article: 25913
"K. Orthner" <korthner@hotmail.nospam.com> wrote in message news:8FBB82E6Fkorthnerhotmailcom@158.202.232.7... ... > You can do this: > > output_pin <= 'Z' when desired_output = '1' else '0'; > > This casuses the output pin to mimic Open-Collector behavior, and the pull- > up resistor that you install external to the chip is responsible for your > TTL '1' (5v). Thanks. This will indeed mimic an open drain output, but the Xilinx trick is to force the output to "1" and then tristate it so that the rise time is much shortened compared to only tristating it. Doing this reduce the rise time from 20ns to 3ns. It's what I would like to do in VHDL. Marc BattyaniArticle: 25914
"Steven" <steven.yeung@xilinx.com> wrote in message news:ee6e195.0@WebX.sUN8CHnE... > What you need to do is to use OBUFT to create a open-drian output. When you need to drive a logic 0, the output buffer will drive it low, if you need a logic 1, the output buffer will be tri-state and the external pull-up will do the job. In your vhdl code, you can do: > > output <= '0' when (oe = '0') else 'z'; Thanks, but the xilinx trick is to use a feedback from the output to force the output to 1 before going to tristate. (see my previous post). Marc BattyaniArticle: 25915
In article <8qpibm$bf3$1@reader1.fr.uu.net>, "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote: > > "K. Orthner" <korthner@hotmail.nospam.com> wrote in message > news:8FBB82E6Fkorthnerhotmailcom@158.202.232.7... > ... > > You can do this: > > > > output_pin <= 'Z' when desired_output = '1' else '0'; > > > > This casuses the output pin to mimic Open-Collector behavior, and the > pull- > > up resistor that you install external to the chip is responsible for your > > TTL '1' (5v). > > Thanks. This will indeed mimic an open drain output, but the Xilinx trick is > to force the output to "1" and then tristate it so that the rise time is > much shortened compared to only tristating it. > Doing this reduce the rise time from 20ns to 3ns. > > It's what I would like to do in VHDL. > > Marc Battyani > > Maybe this slightly modified statement does what you want : output_pin <= 'Z' when desired_output = '1' else desired_output; This assumes that threestating is slower than the gate delay (which usually holds true). -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25916
Hi: Now, i am doing "16bits converting 64bits fifo" of four channels ,my application is to write a lot of data to a fifo first by polling ,and then read it from the fifo by polling, my design is: the input data is 16 bits width,and use four 16 bits latches and 2 bits counter,the data is sent into 64 bits fifo when counter==2'b11.And then i will transfer it at the top level,if i write and read only a certain fifo ,the data of being read is correct.However,when i switch channel,the reading first data is 0 from the switched channel.Obviously ,the "0" of 64 bits is excrescent,but the back data is correct,that is ,it reads a "0" more.the phenomena happens only switching channel. why?Article: 25917
A very strange thing happened to me yesterday. I'm using a RAM block
generated by the Coregenerator in
my structural design.
The first time I didn't have any problems i my behavioral simulation,
but the second time the following error appeared.
Internal ERROR : Access violation
Occurred in architecture BEHAVIORAL of entity
C_MEM_BLOCK_V1_0 (which is a single port RAM block).
Where does this problem come from?
christophe
Article: 25918"Klaus Falser" <kfalser@durst.it> wrote in message news:8qpkjh$rbk$1@nnrp1.deja.com... > In article <8qpibm$bf3$1@reader1.fr.uu.net>, > "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote: > > ... the Xilinx trick is > > to force the output to "1" and then tristate it so that the rise time is > > much shortened compared to only tristating it. > > Doing this reduce the rise time from 20ns to 3ns. > > ... > Maybe this slightly modified statement does what you want : > > output_pin <= 'Z' when desired_output = '1' else desired_output; > > This assumes that threestating is slower than the gate delay > (which usually holds true). I think it could be more like : output_pin <= 'Z' when desired_output = '1' and output_pin = '1' else desired_output. But the second output_pin should be the actual external signal after the output buffer not the internal one... may be I will have to instanciate low level gates. (OBUFT...) Marc BattyaniArticle: 25919
Marc,
My apologies.
I should have read the appnote before I responded.
I beleve that this is what you're looking for.
I synthesized it with Synopsys FPGA Express, and it gave what the appnote
described.
pin <= '0' when desired_output = '0' else
'1' when pin = '0' else
'Z';
-Kent
Article: 25920"K. Orthner" <korthner@hotmail.nospam.com> wrote in message news:8FBBBD919korthnerhotmailcom@158.202.232.7... > Marc, > > My apologies. > > I should have read the appnote before I responded. > > I beleve that this is what you're looking for. > > I synthesized it with Synopsys FPGA Express, and it gave what the appnote > described. > > > pin <= '0' when desired_output = '0' else > '1' when pin = '0' else > 'Z'; Thanks! Exactly what I needed. Marc BattyaniArticle: 25921
Hello All, I have some trouble regarding primary global and secondary global clock lines. I have a design that generates a clock from two inputs. This clock is then used to clock other ff's. The problem now is that there are only 4 global clock lines with low skew in the spartan II (which i am using) and i need aprox 8. The 4 global clock lines are used for other purposes. There are however 24 secondary global lines which also could do the job. Now my design is not yet finished, but when i implement/synthesize part of the design, it inferres BUFG (1 of the primary global clocks) instead of just a IBUF, and placing the pin on the top or bottom row of the device. I looked at the xilinx site, nothing usefull found. I have the constraints setup for these lines with USELOWSKEWLINES. I also tried by hardcoded instantiating an IBUF to the clock line, but it gets replaced. Anybody some suggestions???? Richard -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 25922
There are _no_ secondary clock nets on the Virtex/E/SpartanII. This was an unfortunate choice of wording in (early?) Virtex data. You should be able to stop your synthesiser inserting BUFGs in your secondary nets. Synplify does this via the 'syn_noclockbuf' attribute. You can get good low-skew routing off the top/bottom pins to adjacent columns, particularly if you keep within the span of a 'hex' line. Try playing around in the Editor to see what is possible. Richard Meester wrote in message <39D0964B.50AD8AD0@quest-innovations.com>... >Hello All, > >I have some trouble regarding primary global and secondary global clock >lines. > >I have a design that generates a clock from two inputs. This clock is >then used to clock other ff's. The problem now is that there are only 4 >global clock lines with low skew in the spartan II (which i am using) >and i need aprox 8. The 4 global clock lines are used for other >purposes. There are however 24 secondary global lines which also could >do the job. > >Now my design is not yet finished, but when i implement/synthesize part >of the design, it inferres BUFG (1 of the primary global clocks) instead >of just a IBUF, and placing the pin on the top or bottom row of the >device. I looked at the xilinx site, nothing usefull found. I have the >constraints setup for these lines with USELOWSKEWLINES. I also tried by >hardcoded instantiating an IBUF to the clock line, but it gets replaced. > >Anybody some suggestions???? > >Richard > >-- >Quest Innovations >tel: +31 (0) 227 604046 >http://www.quest-innovations.com > >Article: 25923
Gary Watson wrote: > > I'm doing a board with a Xilinx Spartan II (XC2S150) and have provided > places for both a XC17S150XL and a XC18V01S20 config prom. Am I being > overly paranoid? Hi Gary, Well, maybe not... It all depends on how careful you have been with your architecture and area/speed calculations. But I wouldn't take space for more prom's than the ones I plan to use. On the other hand, you never know when the customer changes his mind about product requirements :) Regards, Johan > Gary Watson > gary2@nexsan.com > Nexsan Technologies Ltd. > Derby DE21 7BF ENGLAND > http://www.nexsan.comArticle: 25924
Richard Meester wrote: > Hello All, > > I have some trouble regarding primary global and secondary global clock > lines. > [...] > Now my design is not yet finished, but when i implement/synthesize part > of the design, it inferres BUFG (1 of the primary global clocks) instead > of just a IBUF, and placing the pin on the top or bottom row of the > device. I looked at the xilinx site, nothing usefull found. I have the > constraints setup for these lines with USELOWSKEWLINES. I also tried by > hardcoded instantiating an IBUF to the clock line, but it gets replaced. > > Anybody some suggestions???? I had a similar trouble a while ago. I was using a Virtex 1000 and I needed a clock pin to be located on a general I/O pad. The workaround I used was to manually edit the edif netlist generated from Synopsys DC and to replace the BUFGP component instantiation with an IBUF. Then I read this netlist with the Xilinx tool and all worked fine! Hope this will help. -- SteVe
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