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Might have something to do with the relative (a)symetry of carry logic [in the vertical columns] and tri-state lines [in the horizontal rows] or something else to do with their overall routing scheme. husby@my-deja.com wrote: > erika_uk@my-deja.com wrote: > > why virtex chips are rectangular and not square > > My guess is because the BlockRam takes up several columns > which, if filled with CLBs would make it square. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net ==============================Article: 25676
I used both virtex xcv400 and 4085XLA. For the former I reached 96% utilization. The design met timing (16MHz for about half the design and 32MHz for the rest). I selected the pin outs so the data flow horizontally limited by two real DPR (only distributed RAM ! could be used because of wide word and few location required). I did not change any of the pin out selection during the entire project. As for timing - the design used pipe line where possible except form some path that pipe line meant performance reduction - and still met the timing. Of course I had to work on the layout and had to find the seed best for the design. As for Assume design can only achieve 25% of expected... I think that every design starts with some calculation on paper where you can make calculation in the worst case FF2FF with approximating the routing time (where segmented FPGAs give better result usually). As for I/O : if you don't have critical ones (does not go directly through a register) and you use the ones in the PAD, then it is fully predictably and has good performance.Article: 25677
In article <39C37C92.FB919779@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > Ulf Samuelsson wrote: > > > > "Darin Johnson" <darin@usa.net> wrote in message > > news:uaed9o4fn.fsf@nokia.com... > > > bjolin@lin.foa.se (Björn Lindgren) writes: > > > ..... > > In the light of the ARM threats to the "www.open-cores.com" activity it > > would be interesting to see how easy the ARM patents would fall down in > > court...." > > I have not heard of the conflict with ARM. Is there a web page > discussing it? It's not really a conflict, it's just one of those "Don't you dare ..." Check out the news section on www.opencores.org, I think it's in one of the EEtimes articles ... > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25678
My project is targeted to Virtex 1000E and the frequncy targetted is
100Mhz and written using verilog. It works well in functional
simulation and fails at post route timing simulation.
I am using Xilinx2.1i for place and route (the option is set for
modelsim verilog) and Modelsim for timing simulation
While doing the timing simulation using model sim, it shows
error in sdf file .
The error is
error:
time_sim.sdf(16): near "(": expecting:MACRO MODULE PRIMITIVE
and it shows some errors in X_LUT4.V and X_FF.V
I couldn't find a solution for this.
can anybody please help me.
thanks in advance,
sivakumar
mettur_siva@hotmail.com
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25679>It sometimes seems to me that US patents are issued for just about >anything that isn't already common knowledge to 8th grade schoolers >and which doesn't even have to be novel. That about sums it up for the USA, and unfortunately things are going the same way in Europe too, with software patents being expanded. The business really stinks - to the extent that innovation is being clobbered. Most technology patents are for products with a very short life, a few years at most, but they run for 20 or so years. Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 25680
Nial,
The simplest way is to test for one signal at a time.
If you have several parallel signals that are asynchronous, and you
need to test them all, then testing for one signal at a time can become time
consuming, literally. In this case, test for one signal, and then on the
next state test for all of them. This assumes that the rest of the signals
have had time to change and become stabilized. This often happens in
systems.
The VMEbus is a good example. When ALE* changes, it means that a new
read/write cycle is starting. Test for ALE* and the rest of the signals
have become stabilized thereafter. I call these rest of the signals
"protocol stabilized," where by protocol, they are known to be stable after
an event happens. I have seen VMEbus designs where the address lines were
synchronized. They don't need to be, because they are stable when ALE*
activates (or shortly before or after, I can't remember). Adding
synchronizer FFs to these address lines only causes a one clock cycle delay,
thus slowing down the design.
The real answer to your question, though, is to know the system that
you are working with in order to understand which signals are asynchronous,
which are protocol stabilized, which are skewed relative to your clock, and
which are synchronous. By knowing these parameters, you can take advantage
of the properties of these signals and design a synchronous system that is
reliable and fast.
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
"Nial Stewart" <nials@sqf.hp.com> wrote in message
news:39C2201F.1EB9C5C8@sqf.hp.com...
> "S. Ramirez" wrote:
> >
> > Thomas,
> > Of course I still call my company Synchronous Design! Parallel
> > synchronizers are simply a no-no design technique of synchronous design.
>
> Simon,
>
> What techniques do you use for synchronising parrallel data that is
> being generated asynchronously?
>
> Nial.
Article: 25681I don't think you understand how the license works. By being node locked it will only work on the node it was licensed for. There is no "keyword" for a particular feature that allows you to copy that feature around. All of the licensed features are encoded into the key number of the license file. If you change any aspect of the license, like node ID or feature set or even the time period of the license, you will get a new key number. So no one else's license file will help you unless you have the same node number. Now a few words about disk drive serial numbers. The serial number of a hard drive is written on the first few blocks of the platter. It can be changed fairly easily and I have done this on my machines. I am a little bit paranoid about the issues of needing to replace hard drives or NIC cards and the resulting problems of trying to get support for the licensing when I am no longer paying for support of the software as a whole. So I give all of my machines the same serial number on the hard drive. Then I can install the software on any of my machines that I choose without needing for the vendor to send me a new license file and forcing me to pay for another year of "support". Although this does not work with the new Xilinx approach of renting you the software. They now say that your ownership of the software is limited to one year. That is a tough one to work around. If you want to get a new license number, you have to pay for support after the year is up. gk7eong wrote: > > Hi, yes I will appreciate it if you send the license.dat for ModelSim to me. > > About my school paying for the software? I think it is really fat hopes. The > way things work here is kind of different. =) > > Thanks in advance. > > Kheng Teong > > Andy Peters wrote: > > > gk7eong wrote: > > > > > > Hi, > > > > > > I'm a final year electrical electronics engineering student. I'm using > > > Max Plus 2 Baseline 9.6 to do my final year project. Is there anyone out > > > there with full licences? Can you send me a copy of your license.dat or > > > can anybody tell me how to get the partitioner features from it. Thanks > > > in advance. > > > > I can send you a license.dat for ModelSim. It will be as useful to you > > as anyone's Max+Plus 2 license.dat file, since the software is > > node-locked. > > > > You could consider having your school pay for the software, which is the > > Right Thing to do. > > > > -- a > > ---------------------------- > > Andy Peters > > Sr. Electrical Engineer > > National Optical Astronomy Observatory > > 950 N Cherry Ave > > Tucson, AZ 85719 > > apeters (at) n o a o [dot] e d u -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25682
That was a very good paper and answered a lot of questions. But the part I fail to understand is that most of the "noise" in a digital Power Distribution System (PDS) is near or above 1 GHz. Nearly all of the data they present is below this frequency. They do a nice introduction, however, explaining that the PDS needs to deal with noise across the entire frequency spectrum. So the data they present is very useful. After looking at this data, I still feel that the combined multivalued capacitor approach does not have significantly greater advantage compared to the same number of capacitors of the same value. Above 1 GHz, the impedance is primarily inductive for all capacitors and the impedance is largely the same regardless of which device you use. Bob Perlman wrote: > > Hi - > > Some good papers on decoupling can be found at: > > http://www.qsl.net/wb6tpu/si_documents/docs.html > > Take a look at the first paper listed. Among other things, it > describes the amount of inductance introduced by several different > capacitor-pad-to-via geometries. > > Bob Perlman > > On Sat, 16 Sep 2000 11:28:57 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > > >I have built a few high speed boards and looked at the capacitive > >decoupling issues in detail. I have not found a basis for adding the > >0.01 uF caps. If you look at the data sheets for the caps you will find > >impedance vs. freq curves for many of these parts. AVX has very good > >data sheets in this regard. > > > >If you study the impedance curves you will find that all of these caps > >are inductive at the frequencies that are important for decoupling (>200 > >MHz). When a capacitor is operating in the inductive region, the > >characteristics are determined much more by the physical package than by > >the capacitance of the device. In this case the smaller packages are > >better, but more importantly, the *wider* packages are better. The > >inductance of a package very strongly related to the ratio of length to > >width. > > > >Another important feature is the manner of connecting the capacitor to > >the power pins. The shortest length trace possible should be used. This > >can be a large contributor to the overall decoupling impedance. So > >adding two different values of capacitor to a power pin will increase > >the length of the PC trace and may actually reduce the effectiveness of > >the decoupling. > > > >I looked in my archive of appnotes for information to support this, but > >could not find any data to quantify the contribution of trace length to > >decoupling impedance. Anyone have data on this? > > > > > > > >"S. Ramirez" wrote: > >> > >> Dan/Ben, > >> In general, as Ben said, both caps are a very good and much better > >> decoupling method than just 0.1uF. > >> I have seen both used and both work. The 0.01uF/0.1uF combination is a > >> more conservative and relaible design for high frequency designs. I have > >> never seen quantitative results, though, to determine just how much better > >> it really is. I have seen analytical results that say it is better. > >> I think Ben meant "power distribution system" rather than "power > >> supplies." The power distribution system includes but isn't limited to the > >> connector power and ground pins, the power and ground plane design, and the > >> decoupling caps. > >> The way I see it is that 0.01uF caps are cheap. If you have the real > >> estate and a few bucks to spare, why not use them? > >> -Simon Ramirez, Consultant > >> Synchronous Design, Inc. > >> > >> > > Is such a recomendation useful ? > >> > > > >> > > Dan > >> > > >> > That is true, it is better than a cap of .11 uf? > >> > For the high frequencies the .01 cap has less > >> > inductance and is able to respond power supply fluctuations quickly until > >> > the .1 cap can catch up. With transistors switching in ps range you need > >> > very good high freq response on the power supplies. > >> > > >> > -- > >> > "We do not inherit our time on this planet from our parents... > >> > We borrow it from our children." > >> > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk > >> > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25683
That's odd... I found a statement on the Xilinx web site which says these lines may be left open if not needed... -- Gary Watson gary2@nexsan.com Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com <news@rtrussell.co.uk> wrote in message news:8pq2rg$pfn$1@nntp0.reith.bbc.co.uk... > Hawker <Hawker@connriver.net> wrote: > > : Are you going into some sort of boundary scan mode? > : I had a similar problem with a XCS05. I found some > : sort of app note about adding some pull-ups and 2 small caps > : to the JTAG pins and it fixed the problem. Basically random noise > : was putting me an a boundary scan or JTAG programing mode of some sort > > That's exactly what it was! Tying the unused JTAG pins > high has fixed the problem. Many thanks for your > suggestion. > > Richard. > http://www.rtrussell.co.uk/ >Article: 25684
> I want to design a board with one of the Spartan FG456s (because of the cost > issue) but they will not be in stock for months. Can I layout a PCB and > stuff it with a Virtex for development ? I gave their pinouts a quick once > over. They look the same but I need to be certain. I'm planning to do the same in one of my projects. The only difference I found so far are the two temperature diode pins (virtex). Anyone else with more information? thanks MichaelArticle: 25685
> We are considering moving the fanout functionality inside the > Virtex, to save on external parts count. The issue I have a > question about is the following. When one sets up the constraints > for the P&R tool (Alliance in this case), is there a way of doing > this so that one can specify the **maximum skew** between any 2 > clock outputs? In other words, is it possible to fan out a clock > inside the Virtex for external use and simultaneously approximate > (dare I say guarantee?) the low skew among all clock outputs that > is characteristic of an external buffer? Maybe you can use the 2x output of the DLL, divide it by 2 in a CLB, and feed the divided signal to several IOBs with output registers, clocked by the 2x-clock. Using this approach, you get multiple low skew signals with the wanted frequency. MichaelArticle: 25686
Hello, We are looking for a freelance designer who can help us develop a daughterboard module. This work will involve the schematic capture and layout of the PCB in (preferably in Protel), and the programming of the SpartonII FPGA. The hardware design will be based on a detailed block diagram of the board that we provide, along with some key part numbers and other needed information. The board includes some A/Ds, D/As and a DDS. The work should take between 30 to 40 hrs and can be done at your location. The project deliverables will be Protel design files, the FPGA design files, and any documentation used to create the design. All rights and claims to any work on this project at all times is unequivocally the property and intellectual property in origin and by any extension with all rights and privileges reserved to Southwest Software & Systems LLC (3S). Payment for the work will be a flat fee of $2000.00 plus a royalty of 5.0% of the sale price for each board, and the boards will sell about $675ea and volume is expected to be a few hundred (For example, assuming a 200 board volume, the total payment for the hardware design would be: $2000.00 + 0.05 x $675.00/Board x 200Boards = $8,750). Additionally, there could be similar follow-up designs. If you are interested and qualified to do this work, please contact me as soon as possible, we are ready to begin immediately. Regards, Walt White Southwest Software & Systems LLC www.southwestsoftware.comArticle: 25687
Michael Rhotert wrote: > > > I want to design a board with one of the Spartan FG456s (because of the > cost > > issue) but they will not be in stock for months. Can I layout a PCB and > > stuff it with a Virtex for development ? I gave their pinouts a quick once > > over. They look the same but I need to be certain. > > I'm planning to do the same in one of my projects. > The only difference I found so far are the two temperature diode pins > (virtex). > Anyone else with more information? > > thanks > Michael I believe it has been stated by Peter Alfke previously that this is the only difference in pinout. But you might want to confirm this through him. I am a little surprised that there is not an appnote discussing this. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25688
In article <39C518D1.E50F6006@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >I believe it has been stated by Peter Alfke previously that this is the >only difference in pinout. But you might want to confirm this through >him. I am a little surprised that there is not an appnote discussing >this. IIRC, it is that the temperature sensing diode pins are used instead for a suspend/sleep mode, but I'm not positive. Agreed, there should be a 1 page appnote on this. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 25689
> > --Yes and no. That somebody is the Xilinx FAE, but we're not talking about > him, we're talking about disties. A disty does not need to be involved, > i.e., register a design, every time. Just ask the direct accounts. > Agreed, but I think this discussion was started by someone who is not a direct account...or have I misunderstood?Article: 25690
Rick,
How do you change the disk drive serial number?
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
> Now a few words about disk drive serial numbers. The serial number of a
> hard drive is written on the first few blocks of the platter. It can be
> changed fairly easily and I have done this on my machines. I am a little
> bit paranoid about the issues of needing to replace hard drives or NIC
> cards and the resulting problems of trying to get support for the
> licensing when I am no longer paying for support of the software as a
> whole. So I give all of my machines the same serial number on the hard
> drive. Then I can install the software on any of my machines that I
> choose without needing for the vendor to send me a new license file and
> forcing me to pay for another year of "support".
Article: 25691I can send you some information if you can provide an email address. I can't seem to decode your email address. "S. Ramirez" wrote: > > Rick, > How do you change the disk drive serial number? > -Simon Ramirez, Consultant > -Synchronous Design, Inc. > > > Now a few words about disk drive serial numbers. The serial number of a > > hard drive is written on the first few blocks of the platter. It can be > > changed fairly easily and I have done this on my machines. I am a little > > bit paranoid about the issues of needing to replace hard drives or NIC > > cards and the resulting problems of trying to get support for the > > licensing when I am no longer paying for support of the software as a > > whole. So I give all of my machines the same serial number on the hard > > drive. Then I can install the software on any of my machines that I > > choose without needing for the vendor to send me a new license file and > > forcing me to pay for another year of "support". -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25692
I am trying to get the Xilinx Web Pack up and running on my machine and am having trouble. The first problem I had was the fact that the install did not seem to handle properly the path in the shortcut as I put it under the "Program files" directory and it needed quotes around it to be able to incorporate the space in the path. The next problem I have is trying to access the help. Many of the items in the help window cause errors like "Can not find or run the program or file 'dkxilinx.hlp'". It also could not find a current version (or any for that matter) of "hhcntl.ocx". When I try to bring up the online version of help, I get an error that it can not open the site with a very long and complicated name containing characters that are not legal in a URL such as the @ sign. I don't know what either of these files are, but I am beginning to think that I can't run this software under Win95. Is that my problem? The real problem I am having is that when I try to create a new project, I am not presented with the option of using a real part, but rather the only option for device is "virtual device". -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25693
Hi - To download a utility that will change the volume ID, go to: http://www.sysinternals.com/misc.htm and download the VolumeID at the bottom of the page. This utility is supposed to work on both FAT and NTFS partitions, but I've tried it only on the former. Bob Perlman On Sun, 17 Sep 2000 20:07:29 GMT, "S. Ramirez" <sramirez@deleet.cfl.rr.com> wrote: >Rick, > How do you change the disk drive serial number? >-Simon Ramirez, Consultant >-Synchronous Design, Inc. > > >> Now a few words about disk drive serial numbers. The serial number of a >> hard drive is written on the first few blocks of the platter. It can be >> changed fairly easily and I have done this on my machines. I am a little >> bit paranoid about the issues of needing to replace hard drives or NIC >> cards and the resulting problems of trying to get support for the >> licensing when I am no longer paying for support of the software as a >> whole. So I give all of my machines the same serial number on the hard >> drive. Then I can install the software on any of my machines that I >> choose without needing for the vendor to send me a new license file and >> forcing me to pay for another year of "support". > >Article: 25694
Rick,
I can't decode yours either; otherwise I would have contacted you
privately.
My email address is: sramirez@cfl.rr.com
Thanks.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:39C532B2.35946A67@yahoo.com...
> I can send you some information if you can provide an email address. I
> can't seem to decode your email address.
>
>
> "S. Ramirez" wrote:
> >
> > Rick,
> > How do you change the disk drive serial number?
> > -Simon Ramirez, Consultant
> > -Synchronous Design, Inc.
> >
> > > Now a few words about disk drive serial numbers. The serial number of
a
> > > hard drive is written on the first few blocks of the platter. It can
be
> > > changed fairly easily and I have done this on my machines. I am a
little
> > > bit paranoid about the issues of needing to replace hard drives or NIC
> > > cards and the resulting problems of trying to get support for the
> > > licensing when I am no longer paying for support of the software as a
> > > whole. So I give all of my machines the same serial number on the hard
> > > drive. Then I can install the software on any of my machines that I
> > > choose without needing for the vendor to send me a new license file
and
> > > forcing me to pay for another year of "support".
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
>
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com
Article: 25695Thanks, Bob, I'll check this one out. -Simon Ramirez, Consultant Synchronous Design, Inc. "Bob Perlman" <bobperl@best_no_spam_thanks.com> wrote in message news:34jasscf7omdb79orj49mn24fckr2fouth@4ax.com... > Hi - > > To download a utility that will change the volume ID, go to: > > http://www.sysinternals.com/misc.htm > > and download the VolumeID at the bottom of the page. > > This utility is supposed to work on both FAT and NTFS partitions, but > I've tried it only on the former. > > Bob Perlman > > On Sun, 17 Sep 2000 20:07:29 GMT, "S. Ramirez" > <sramirez@deleet.cfl.rr.com> wrote: > > >Rick, > > How do you change the disk drive serial number? > >-Simon Ramirez, Consultant > >-Synchronous Design, Inc. > > > > > >> Now a few words about disk drive serial numbers. The serial number of a > >> hard drive is written on the first few blocks of the platter. It can be > >> changed fairly easily and I have done this on my machines. I am a little > >> bit paranoid about the issues of needing to replace hard drives or NIC > >> cards and the resulting problems of trying to get support for the > >> licensing when I am no longer paying for support of the software as a > >> whole. So I give all of my machines the same serial number on the hard > >> drive. Then I can install the software on any of my machines that I > >> choose without needing for the vendor to send me a new license file and > >> forcing me to pay for another year of "support". > > > > > >Article: 25696
Rick,
Excellent idea to have an app note discussing the differences so that
Virtex savvy engineers can switch over quickly. There has been much
discussion of this on this newsgroup, and I also think it's worthy of an app
note in order to clarify most things that comes up. From what I understand,
here are the differences:
1) temperature sensitive diodes missing on Spartan II
2) core (CLB) transistors are 0.18u on Spartan II and 0.25u on
Virtex
3) Spartan IIs come in limited (read: cheapest) packaging
4) Spartan IIs are viperware as I write (no need for this
to be in the app note)
Are you listening, Xilinx?
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
Note: viperware (vïpêr·wär) n. something that will bite you if you design
it in and don't have the parts in hand.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:39C518D1.E50F6006@yahoo.com...
> Michael Rhotert wrote:
> >
> > > I want to design a board with one of the Spartan FG456s (because of
the
> > cost
> > > issue) but they will not be in stock for months. Can I layout a PCB
and
> > > stuff it with a Virtex for development ? I gave their pinouts a quick
once
> > > over. They look the same but I need to be certain.
> >
> > I'm planning to do the same in one of my projects.
> > The only difference I found so far are the two temperature diode pins
> > (virtex).
> > Anyone else with more information?
> >
> > thanks
> > Michael
>
> I believe it has been stated by Peter Alfke previously that this is the
> only difference in pinout. But you might want to confirm this through
> him. I am a little surprised that there is not an appnote discussing
> this.
>
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
>
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com
>
Article: 25697You are correct that it was started by Andy Peters, a disty account today, but it quickly digressed into how the the reps and disties work. The discussion went that way because we were trying to find a way to cut out the disties in order to keep him from getting hassled about how many thousands of parts he will need in the next 10 days. It is actually possible to convert a low usage guy from a disty to direct account. All it takes is the rep and Xilinx agreeing that it should be handled direct. Sometimes there are reasons for doing this sort of thing, and usually the disty will get a bone thrown his way just to have him bow out. -Simon Ramirez, Consultant -Synchronous Design, Inc. "Mark Harvey" <mark.harvey@iol.it> wrote in message news:oS8x5.35637$XZ4.438867@news.infostrada.it... > > > > --Yes and no. That somebody is the Xilinx FAE, but we're not talking > about > > him, we're talking about disties. A disty does not need to be involved, > > i.e., register a design, every time. Just ask the direct accounts. > > > > > Agreed, but I think this discussion was started by someone who is not a > direct account...or have I misunderstood? > > >Article: 25698
In article <VvXu5.3068$tj4.28495@news-server.bigpond.net.au>, "Carl Rouse" <Carl@versatiletechnology.com.au> wrote: > Hi all, > is the Xilinx Student Edition 2.1 actually available from anywhere > or is it still on the way? > Last I heard was on 24/7/00: > I havent seen it yet Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25699
daniel.deconinck@sympatico.ca (Dan) wrote: >The Spartan II has three sizes that come in the FG456 package: <snip> >The Spartan II has three sizes that come in the FG456 package: <snip> >Are the footprints interchangable ??? I asked this question of Xilinx support, and this was their answer: <open quote> Hi Kent, There are actually some minor pinnout differences between the two: The Virtex DXN and DXP pins have been replaced w/ STARTUP and PWRDN pins in the Spartan-II. Those are the only differences. <close quote> ** Note 1. The pin is called "STATUS", not "STARTUP" in the data sheet (DS001/03/03/2000). 2. /PWDN should be pulled high for normal operation. (So thereis a tiny PCB change). -Kent
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