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Stuart, If you're only doing Spartan-II with an HDL, Xilinx will soon have support in the free WebPack ISE which is basically a subset of Foundation ISE - no FPGA Express though, only the new Xilinx synthesis tool XST (but its pretty good). Mark. Stuart J Adams <sja@world.std.com> wrote in message news:G29wqH.4Gu@world.std.com... > Is it worth the extra $$ for Foundation/ISE > Express vs. Base Express ?? I am doing > Spartan II designs so the only added features > would be the FPGA Express graphical constraints > editor, Time Tracker and Vista GUIs. Are these > worth the extra $$ (about $2000 extra) ?? > > (So far I've just been putting my constraints > in the UCF files - does FPGA Express do anything > useful during synthesis with the constraints > if you put them in with the FPGA Express GUI ??) > > -- Stuart >Article: 26351
We're finding that occasionally the Foundation Express schematic editor will refuse to read or write a file if the name is more than 8 characters. The strange thing is that sometimes it works OK, other times it fails. The software is 2.1i, with and without patches, on WinNT and Win98. Anyone have an explanation for what's happening? -- Caleb Hess hess@cs.indiana.eduArticle: 26352
Hi, I'm totally new to FPGA and PCB design. Now I have a project to do: there is a PCI board with Xilinx XC4013XLT chip, an ASIC chip (M1) and two SRAM chips. My job is to simulate if the ASIC chip works correctly. Specifically, I need to: 1. Use Xilinx chip to download(or upload?) some data from a file to SRAM; 2. Use M1 to process the data and save the results back to SRAM. 3. Use Xilinx chip to upload the data to a file and check the result. I will use VHDL to write the simulation program. My questions are: 1. Can I treat the Xilinx chip as a kind of black box? What should I know about it for the simulation? How to use it in VHDL program? 2. Is there any example about PCI communication (with Xilinx chip)? I have the book PCI System Architecture already. 3. Which software is suitable for the simulation? Thanks a lot. JeffArticle: 26353
rickman <spamgoeshere4@yahoo.com> writes: > Neil Franklin wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > > What exactly do you do with FPGAs? > > > > Emulate historical CPUs. PDPs for the beginning. > > I would be very interested in working on a PDP-8 or PDP-11 design. I > have been looking for a good processor to fit inside an FPGA and I think > the PDP-11 would do very well. I have no idea of the size. Depends on what you want the processor to do. If an 12 bit, single accumulator, 4k*12 address space (32k*12 with MMU), average 2.5 memory accesses per instruction will do, then PDP8. There exists an PDP8/I on XCS10 called PDP8/X at: http://surfin.spies.com/~dgc/pdp8x/ PDP-11 is an 8x16 register CISC architecture, which is mainly interesting for historical reasons. Just as an CPU for productive work without legacy code, it is most likely a waste of space. Then a 16x16 register RISC will be better, such as the one at: http://www.fpgacpu.org/ > I also have > little idea of where to get the proper documentation. Do you have info > on this? PDP8 I have the "Small Computer Handbook 1973 (PDP8/E hardware element description for people putting systems together) and "Introduction to Programming" (the official educational material for application programmers). There is also other manuals and a software emulator that will run all OS binaries unchanged at: http://www.cs.uiowa.edu/~jones/pdp8/ PDP11 I only have web based docs, an software emulator that runs multiple OSes at: ftp://minnie.cs.adfa.edu.au/pub/PDP-11/Sims/ and an real PDP11/23 to experiment with. > I am also toying with the idea of a Forth processor. Try: http://www.cse.cuhk.edu.hk/~phwl/msl16/msl16.html, it runs 3 instructions per memory access, runs on a XC4006E. > My goal is to have > a processor which will work in on chip memory for small programs to > perform DMA and other board control functions. A simple 16 bit processor > could fit very well into the main FPGA on my board. Either the fpgacpu RISC or msl16, depending on preference for C or Forth. > > Linux tradition would be really nice. Momental state of investigation > > seems to be: no Linux tools. > > That is totally true except for some of the smaller chip vendors. Which? > > > toolset under Linux and we still don't have that yet. People even run > > > the tools using WINE, but still no formal support from Xilinx. > > > > I suppose I will have to do that then. > > > > Or get the tools for Sun (if they are also in the free (beer) > > license). In what size are, say, 20x20 to 32x32 CLB parts > > netlists and bitstreams as files (my Sun access is over modem and > > metered telephone line). > > I am not clear as to what you are asking. Are you saying that you are > worried about the download time for a completed bitstream file over a > phoneline? Yes. SOme of the larger chips have megabit sizes. But I assume the smaller chips to be more managable. > I think you will find the place and route time on even the > fastest Sparc to take a lot longer than the download time for a > configuration file. This being? Worst case I can start and log out. > The file in binary is about 100K bytes for an XCV100 > which is 20 x 30 CLB (quad LUTs and FFs). That is acceptable. > If you are working over a phone line, what happens if you try to run a > tool that is inherently graphical, like a chip editor? One of these > programs does not update the screen all that fast on a dedicated PC. You > might be much better off biting the bullet and working on a local PC. Editing will have to be local. But with the target being ASCII files with publically specified content (EDIF, XNF) that is something I can write myself if neccessary. So only non-graphical compiling will need the Sun. > > > The back end tools accept the gate level design and figure out how to > > > put that into the vendor's FPGA. This is by definition, vendor specific. > > > > So generating EDIF or XNF ASCII files by some means and then compiling > > them to bitstreams on a Sun or WINE is all the tools I need? > > You make that sound so simple, but yes. Where are the difficulties? What are these? > > > You tell me. Why do you want open source tools? > > > > So I can run them on this box here, which implies being able to > > compile them, as the vendors don't seem to be offering them for it. > > > > That is why I asked about if it was free beer or speach. I need the > > second for this. > > What is "this box here"? Do the chip vendors offer tools for it? AMD K6-2 350 running Linux 2.2.13. > > If you have no back end, the front end is no use. IIf I have change my > > setup (install WINE, use remote Sun) to use a vendors back end, I > > can just as good use their front end, so why then spend time making > > an own front end. > > > > At least that was my thought 2 days ago. Of course avoiding front end > > cost may make such a development still worth it. > > If your design is not too complex, If I am making own boards (wire wrap perfered), I am limited to PLCC84, so 20x20 CLBs (XC4010) seems to be the limit (and enough for the first few projects, use 2 of them if neccessary). > you will be able to use the free > (beer) tools when they come out later this month assuming you are > willing to use WINE and the tools work under WINE. That will definintely > be the path of least resistance assuming that you want to do chip > designs rather than change the way chips are designed. Will have to try that then. > > > That is the place to start > > > regardless of the status of the back end tools. > > > > OK, if doing front end only development. > > I just found out a couple of days ago that the WebPack ModelSim XE > simulator has a 500 line code limitation. How big a limit is that? I have no experience to range this as "cripling, toys only" or "only stops big commercial projects". > Verilog ASCII to EDIT of XNL ASCII, I may just look into what direct > > working with EDIF or XNL is like, or generating them by some own > > means. And then just compiling the bitstreams with vendor tools. > > > > Do I get this right tht VHDL : EDIF = C : Assembler, sort of? > > This is valid only in a limited, crude way. EDIF is just a way of > discribing a netlist. That netlist is very close to the hardware. So in > that sense, it is similar to assembly language. But EDIF is also > hardware independent. So more like Java bytecode, level wise, but still ASCII formatted. > You can generate EDIF from VHDL or C or even Forth if you have the mind > to do that. But others are working in that area (not the Forth... yet). > You should do some searching on the web to get info. I have already found Jan Grays CNets (C++ based) on the fpgacpu website. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 26354
tnx to allArticle: 26355
I have clients who occasionally "need" palasm, to support an old design. Anyone have a suggestion for where one might find/buy/download palasm ? Originally, it was a freebie that AMD distributed to encourage design-ins of their PALs... Thanks, in advance ! Bob Elkind John Larkin wrote: > On Wed, 11 Oct 2000 09:34:10 +0200, "news tin" <rinux@iternet.it> > wrote: > > >hi at all > >anyone use palasm??? > > > > yeah, I still use it once in a while. It's fast and simple, good for > simple 22V10 or 18CV8 things. > > John -- ****************************************************************** Bob Elkind email:eteam@aracnet.com 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ****** Video processing, R&D, ASIC, FPGA design consulting *******Article: 26356
On Tue, 10 Oct 2000 22:33:48, Neil Franklin <neil@franklin.ch.remove> wrote: > Oops, I caused a bit of confusion here. > > Kent Orthner <korthner@hotmail.nospam.com> writes: > > > krw@attglobal.net (Keith R. Williams) writes: > > > > > Andy Peters <"apeters <"@> n o a o [.] e d u> writes: > > > > > Stop right there. You're thinking that a software person can design > > > > > hardware? Sorry. Just because VHDL is a "programming language," it > > > > > doesn't mean that a person who writes VHDL is a good hardware designer. > > I suppose I forgot to mention, that I am an (ex-) hardware person. I > do have a few 74(LS)xx and 8051 style designs behind me. I am only new > to FPGAs, not to hardware. Sorry, my new ISP (went to cable a month ago) has a rather poor news server and didn't get this article. Anyone with a suggestion for a *good* server? I am also a hardware type who has done extensive 74xxx and 8051 stuff. In fact the board I'm doing now has an 8051 on it just to do FPGA configurations and some house-keeping. The 8051 is a wild beast, but it makes a nice controller. ...and I know it well (I used it or some crypto key management 10 years ago - on IBM's 3090s and ES9000s). > > > On Tue, 10 Oct 2000 00:49:34, Kent Orthner > > > > If I'm not mistaken, VHDL *isn't* a programming language. It's a "Hardware > > > > Description Language". the purpose of VHDL is not to program anything; you're > > > > not telling some CPU what to do, you're describing a hardware construct. > > And programming is? Telling the hardware what to do. CLB1 take from ... Very different, yet there are similarities. When VHDL is used as a simulation language it's rather more like programming, except that the dreaded time and concurance thingies come into play. ..then there are the several data-types that work differently depending on the libraries loaded. No, I haven't figured this all out. This is *not* programming, yet VHDL is a progamming language. When doing hardware design one must worry about what the compiler is going to do with your design. Again, add in *time* and *concurrancy* and you'll find that it is a *very* field than that where programmers play. Further add in the details of actually getting a board to production and it's very different than programming. Note that my current project has a production run of 3 and 7, but it's still not something that programmers do. > > > Well, it is a programming language. The intention is certainly > > > to abstract hardware, but it is a programming language. > > And like any other programming language uses textual symbols to > describe which operations a piece of programmable hardware should do. You have no clue. Certainly a CPU is programmable. However, VHDL describes *HARDWARE*. This is very different. I suggest you try it before knocking it. It *is* hard! > And then a compiler makes bits from it that are fed to the hardware. a rather simple apporach to life. Hey, a million monkeys... > I suppose that P in F>P<GA and C>P<LD does stand for programmable :-). I suppose, but what's you excuse? I can program the bits, can you? Note that just programming the damned things isn't easy. It took me a week to simply get the proper bit stream and handshaking to program a SpartanXL. The documentation is poor for both the part and the bit-generator. Such is life when you have multiple variables. > > > > interesting thing about VHDL and Verilog (remember I'm a relative > > > newbie here) is the concurrancy. Things one learns in > > Normal hardware feature. Can also be found (and screwed up) in 74(LS)xx. Try it in a programming language. Add time to the language and you'll be humbled very quickly. Things just don't work as you think they do. This is not easy stuff. I've worked with schematics for 25+ years and am very comfortable with them. HDL takes some mind-bending. For data-flow it's a PITA, for state-machines - I have no idea how I lived without. I can code some fairly complex state machines and only find one or two *easily* fixed problems. Productivity? I guess! > > I absolutely agree with you (And Andy). "Programming" and "FPGA/ASIC/Hardware > > > design" are completely different. One consists of a series of steps for a > > CPU (A program!), and the other describes how hardware should work. > > And both consist of taking a task, decomposing it into structural > elements of the target systen (instructions for CPUs, connects for > FPGAs) and expressing them in code, the (source) program. Complexity reduced to the absurd... > The elements may be different, but the process is the same, once one > knows the elements behaviour and gotchas. And that electronics is > parallel is well known. As for specific FPGA models gotchas, they have > to be learned like specific CPU models ones. It sure sounds simple, eh? > > > Also, you forget the fact that Engineers have things like timings > > > to meet, and the I/O is not a monitor. > > > > <laughing> I only wish I could forget that. It would make my life > > a *lot* easier if I didn't have to worry about timing constraints! > > Timing problems also exist on 74(LS)xx. And a 8051 often doesn't have a > monitor either, particularly if you are the one writing the 7-seg LED > driver and keypad scanner. Good grief. The 8051 is a trivial beast. I do assembly code for that thing every day. One years I spit out 25K lines of high rel stuff (not a fail in the field). I rather like the 8051, in fact. Simple, yeat does its thing. However, in the widget I'm working on it's been a pain. As slow as it is, I'd like to be able to make it wait more. You simply cannot compare any 8051 logic to FPGAs. It's just not possible. > And like anything else: begin small, 1 clock, all FFs clocked from it, > slow enough so all inputs are ready. For 1-10MHz designs that should > not be too difficult. The vendors are talking of 100MHz, so with > factor 10 distance from that life should not be too difficult. Have you done it? I've been through just this awakening and you are wrong. 1-10MHz designs are few. Trivail, but few. It took me months (no formal help, sad to say) to get my design above 30MHz in a XCS40XL-4 (man, how stupid I was - even though the kind folks here told me what I was doing wrong long ago, but didn't understand) and now am targeting 200MHz on a XCV600E-7. I still may not understand, but I'm learning fast. > > > Hmm, VHDL doesn't seem to me to have any of the above atributes. > > > Sure, you can code hardware in VHDL as if it's a schematic (i.e. > > > a markup language), but trust me. you soon learn that isn't the > > > way to go. > > Could you expand on this? What is the problem? What the better method? See others articles. Basically one doen't want to get into the gates and latches. One wants to infer them. The hard part is infering the logic you want. This is where the tools come in. > They weren't needed. Them 74HCxxs (you use newer chips than I) can > become a CPU if wired right. Just that I have decided that I would > like to try something new and programm up CLBs instead of wiring up > TTLs. Try it. It's not your Father's idea of design. One doesn't "wire up" CLBs. That was where I was at some time ago when DynaChip was still in business. I studdied their architecture until I *knew* how to wire than damed chip. ...ooops. I was wrong on so many sides it hurts. I'm still not over the pain, so I listen! > > > I think it's rather arrogant for a "C programmer" to think they > > > understand hardware. > > For clarification: A intended that statement as > bitstreams : VHDL/Verilog eqiv binary instructions : C programs I don't buy it. > It seems to have been misunderstood. Did make a few interesting to > read posts though :-). > > > > "C programmers" don't need to know about > > > concurrancy, and if you did you would sh!t. ...and that's only > > > the start of your problems. > > > > I'm not a C programmer. Once again, I think this rant was aimed > > at someone else! > > At me. But it missed, in multiple respects. No, you have no idea. > > -- > Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ > Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, Mystic I don't see hardware engineer in the above. ---- KeithArticle: 26357
On Thu, 12 Oct 2000 02:12:30, Kent Orthner <korthner@hotmail.nospam.com> wrote: > > > krw@attglobal.net (Keith R. Williams) writes: > > <korthner@hotmail.nospam.com> wrote: > > Well, this thread is confusing, but it may be me. I've been > > doing 7-day weeks and am burnt. It looks like good weather this > > weekend, so I promised the wife I'd take her leaf-peeping. :-) > > The "little woman" convincd me to go "Dam-peeping" this weekend. > We leave sat'day night, spend the night on a bus, see the > Dam & the Dam's tourist shop, get back on the bus, and be back > in time for supper sunday night. Envious, anyone? By bus? No! I'm tired of dam(ned) busses when I leave work every night! I gots busses for reads, and writes, and addresses, and... Oh, that's not what you ment. Anyway, I'll go by car (I live in prime leaf territory), thanx!. ;-) > > It is a programming language. All programming languages have > > their targets. VHDL and Verilog are optomized for hardware > > simulation and synthesis. Each are *very* different than what a > > programmer would consider a "programming language". > > > > As I pointed out the concurrancy issue is a biggie (the concept > > of time is the other). Most programmers can't deal with > > multi-threading effectively, yet hardware is *always* > > "multi-treaded". > > Maybe I have my definitions mixed up. But if nobody objects, in my mind, > I'm going to go ahead and consider C++ a programming language and VHDL > something else, a 'modeling language' or somewhat. Although I'll admit > <grudgingly> that it *does* fit the requirements of a programming language. It is a programming language. It has a different target than most, and understand different parameters, but it is a programming language. > As I see it, designing hardware/ASICs/FPGA's, etc, is so considerably > different than designing software (Although there are similarities), > that it's a bit of a disservice to ourselves to call them both > programming languages. Although I use the 'programming language' VHDL, > I certainly don't consider myself a programmer. Ok. I think the hardware types understand this. Evidently the software types don't. In additon to time and concurrancey (I've been told that it's damned hard to find programmers who can write multi-threaded applications) there are such things like I/O (V/ns) and decoupling (A/ns) to worry about. A programmer that crosses the barriers ceases to be a programmer. Those of us that cross to the dark side cease to be engineers. There *is* a difference! > > No. I don't buy that at all. There are many things about > > software that I don't grok, and there are many things about > > hardware they just can't get. There is a very different mindset > > between hardware types and programmers. Yes, I can program, but > > I think hardware, so program in assembler. My comrades are > > software types and think in C++. There is a chasm here. Neither > > is wrong. Both are needed. To think the programmers can design > > hardware is simply nuts. > > You don't grok. But that doesn't mean that you couldn't grok if > you wanted to. Maybe, though my partner has his problems too. I can't even spell C++ (though C seems to me to be nothing more than an assembler with good libraries/macros). > I'll clarify what I meant, so nobody thinks I'm nuts. <grin> > > I'm not saying that a programmer can design hardware. I am saying > that most programmers (Any that i have known) can, given the time > and desire, become hardware designers and design hardare. I don't agree. There is physics in the way. For example, few programmers know what the hell a transmission line is (and I can only grok Sockets at a high level). IMO there is a *big* difference between programmers and engineers. > Similarly, hardware designers don't necessarily know how to > program, but can learn given the time and desire. I have different thigns to do, but you're somewhat right. I can plink at programming. > I never said a programmer could program VHDL. I only said > they could learn. Learn VHDL, likely. Learn how to do hardware design, I disagree, without becoming an engineer, and all that baggage. > <stupid pun> > Personally, I poke around in Perl a bit, but I like to keep C++ > away with my ten-foot-pole object. > </stupid pun> Well, I like objects, which is why I still use OS/2. Now, my ten-foot-pole object has been drastically shortened by Xilinx and Synplicy's (and ModelTech) lip-lock on WinBlows. I can't even get the windows to sit still! It takes me ten minutes every morning to put all the windows in place for the day. Grrr! ---- KeithArticle: 26358
On Thu, 12 Oct 2000 15:26:39, Jamie Lokier <spamfilter.oct2000@tantalophile.demon.co.uk> wrote: > Keith R Williams writes: > > My comrades are software types and think in C++. There is a chasm > > here. Neither is wrong. Both are needed. To think the programmers > > can design hardware is simply nuts. > > You're aware of attempts to translate Java into hardware aren't you? :-) No. A JVM, yes. Java, no. This is *not* software. I do believe the hardware types are the ones trying to do the hardware JVM. Hmm, would it then be called a JHM? ;-) ---- KeithArticle: 26359
Jamie Lokier wrote: > > rickman writes: > > If you are working over a phone line, what happens if you try to run a > > tool that is inherently graphical, like a chip editor? One of these > > programs does not update the screen all that fast on a dedicated PC. You > > might be much better off biting the bullet and working on a local PC. > > Agree, however you can get a long way without doing anything graphical, > and the rest is painful but possible over compressed X or VNC. > > These days I always run Maxplus2 via the command line and "make". > However, if I need to read some documentation, or search for some option > to tick, I'll need to pull out the GUI. Yes, you can work from the command line for most of the stuff. But it seems it would be a real PITA when you get to the graphical stuff. > >> Unfortunately they have too few FFs for emulating CPU register sets > >> (exeption seems to be Alteras MAX9000, but is that info available?). > > The bigger FPGAs have enough internal RAM to emulate CPU register sets. > Generally you get a more registers than you wanted, and not as wide as > you wanted though :-) I assume you realize this was not my comment you were responding to. I disagree that there are not sufficient resources to construct register sets. To the contrary, in Xilinx and Lucent chips there are dual port RAMs in each LUT that can be used easily and line up well with the counters, buffer and other linear objects used in FPGAs. Each LUT RAM contains 16 or 32 deep memory. > >> > You tell me. Why do you want open source tools? > >> > >> So I can run them on this box here, which implies being able to > >> compile them, as the vendors don't seem to be offering them for it. > >> > >> That is why I asked about if it was free beer or speach. I need the > >> second for this. > > > What is "this box here"? Do the chip vendors offer tools for it? > > Fwiw, _my_ interest in open source tools has nothing to do with being > able to run them on my box, which runs Linux. On the whole, the vendor > tools work ok under Wine. Not that my box has enough RAM or MHz, so I > still use the big Sparc in the computer centre :-) > > >> > An open source back end > >> > is of no value with out the front end. The vendor's back end tools are > >> > free (beer) or nearly so. The front end tools can be very expensive at > >> > $5,000 and up! That's a lot of beer!!! > >> > >> Actually after getting the point that the front ends are just VHDL or > >> Verilog ASCII to EDIT of XNL ASCII, I may just look into what direct > >> working with EDIF or XNL is like, or generating them by some own > >> means. And then just compiling the bitstreams with vendor tools. > >> > >> Do I get this right tht VHDL : EDIF = C : Assembler, sort of? > > > This is valid only in a limited, crude way. EDIF is just a way of > > discribing a netlist. That netlist is very close to the hardware. So in > > that sense, it is similar to assembly language. But EDIF is also > > hardware independent. The tailoring is done by the specific elements > > that are linked together. They are the basic blocks within the FPGA. > > You can, however, write EDIF and XNF by hand or using Perl scripts. > > It's worse than writing assembler for a CPU, but for small circuits > where you're designing all the logic explicitly, translating a > home-brewn language of equations into EDIF is plausible. I can only imagine that this is difficult. But it does pose an interesting possiblity. I had thought of writing programs in Forth which would output an EDIF netlist. I think I can even see in my mind how this would work for simple netlist generation of very complex designs. But the hard part is that this is no different than drawing a schmatic in function. You need to design every FF, gate and Tbuf you need to use in the FPGA. One of the advantages of VHDL is that synthesis can "infer" much of your design from the VHDL description which is not truly at a gate or FF level. Of course people have been doing lots of good work with schematics for a long time. Ray Andraka and others have developed the heiarchical schematic approach to a fine art with lots of resuable blocks that can get very close to the hardware. The same can be done in a text based language using Forth, or likely Perl or even EDIF. Has anyone taken a look at that? > > You can generate EDIF from VHDL or C or even Forth if you have the mind > > to do that. But others are working in that area (not the Forth... yet). > > You should do some searching on the web to get info. Or if you ask > > direct questions you will likely get some direct answers. > > > I know that there are tools to generate hardware from C. It may use > > VHDL as an intermediate form however. > > EDIF in the case of Handel-C, which I use. Actually, I think Handel-C is the one that I have heard the most about. Thanks. > > The real trick to all this is to learn how to describe hardware in *any* > > language. I have been designing digital hardware for twenty years. I > > have been working with VHDL for about three. I still do not find it so > > easy to write good VHDL that gives me just the hardware that I want. I > > know that C would be worse and I'm not sure about Forth. ;) > > I've compared the performance of an application written in Handel-C, > which is similar to C, with the same application written by someone else > in AHDL, which is Altera's VHDL-like language. > > Handel-C came out slower, as in 2/3 of the clock rate, but I was able to > write a more sophisticated pipeline to make up for that. I don't have > an explanation for the lower clock rate. Circuit area came out > identical -- that surprised me. The fact that you don't understand the circuit is what bothers me about synthesis. When I code in C for a CPU, I can accept what the compiler produces. This is because they have been honed to a point where the code is so highly optimized that I can not improve on it by hand. In fact, I often can not even understand it. But the HDL compilers I see don't work nearly as well. So I always check my EDIF output to see what the HDL hath wrought. I often find very clumsy constructs and I have to tweek my VHDL to get something closer to the hardware I have picked for the solution. But that is the point. I know what I expect in the way of hardware. If you don't know why one is slower than the other, I suspect that is because you do not know what hardware you expected and so don't know how close the output came to the optimal solution. This is not meant as a criticism of you, but rather the HDL tool. > Interestingly, place & route was much faster with the Handel-C output, > for the same level of resouce utilisation. > > On the whole my experience with Handel-C has been good. I find it much > easier to write good Handel-C than good VHDL -- mainly because I can > read what I wrote and understand what it does! > > I'm in a privileged position though -- most Handel-C users don't know > how the source is translated into logic. I do have a very good idea, > and just like writing C for a CPU, I bear it in mind when coding. > > enjoy, > -- Jamie Then why could you not figure out why the C HDL result was slower than the AHDL? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26360
Andy Peters wrote: > > rickman wrote: > > That is totally true except for some of the smaller chip vendors. I know > > I have heard of tools for Linux, but they are not free (beer or speech). > > I don't understand. Why should a tool be free, just because it runs on > Linux? > > (I wouldn't MIND free tools, if they work, as much of the networking > stuff for Linux/Unix does. I just haven't figured out how a programmer > can afford to eat if (s)he's giving away all of her work.) Razor blades are not of much use if you don't have a razor. That is why razors are sometimes given away or at least sold very cheaply. But they always make money on blades. The tools don't have to be free. I don't think I said that. But if FPGA companies want to sell chips, they will give away the tools. And I know that they do that. They give away tools to anyone who buys a minimum amount of chips. Several companies, such as Atmel, give away their tools for WinXX to anyone. But I just don't see any free tools under Linux or Unix. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26361
Neil Franklin wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > > Neil Franklin wrote: > > > rickman <spamgoeshere4@yahoo.com> writes: > > > > What exactly do you do with FPGAs? > > > > > > Emulate historical CPUs. PDPs for the beginning. > > > > I would be very interested in working on a PDP-8 or PDP-11 design. I > > have been looking for a good processor to fit inside an FPGA and I think > > the PDP-11 would do very well. I have no idea of the size. > > Depends on what you want the processor to do. If an 12 bit, single > accumulator, 4k*12 address space (32k*12 with MMU), average 2.5 memory > accesses per instruction will do, then PDP8. There exists an PDP8/I on > XCS10 called PDP8/X at: http://surfin.spies.com/~dgc/pdp8x/ > > PDP-11 is an 8x16 register CISC architecture, which is mainly > interesting for historical reasons. Just as an CPU for productive work > without legacy code, it is most likely a waste of space. Then a 16x16 > register RISC will be better, such as the one at: http://www.fpgacpu.org/ I am actually looking for a very small engine that can be programmed. It should have very small memory requirements (< 1K words, maybe << 1K words) so that it can operate from on chip memory. It will be used to control an IO chip doing DMA and data formatting. It may not be in the direct data path, but will have to do high speed control of the data path. I have fully formed the requirements in my mind. I am exploring new territory to see if there is something useful here. > > I also have > > little idea of where to get the proper documentation. Do you have info > > on this? > > PDP8 I have the "Small Computer Handbook 1973 (PDP8/E hardware element > description for people putting systems together) and "Introduction to > Programming" (the official educational material for application > programmers). > > There is also other manuals and a software emulator that will run all > OS binaries unchanged at: http://www.cs.uiowa.edu/~jones/pdp8/ > > PDP11 I only have web based docs, an software emulator that runs > multiple OSes at: ftp://minnie.cs.adfa.edu.au/pub/PDP-11/Sims/ and an > real PDP11/23 to experiment with. I really need electronic documentation so that I can get my hands on it easily. I also used to have a LSI-11. It was the Heathkit version with the 11/04? board from DEC. But I tossed a couple of years ago when I moved. I never expected to need it again. I guess if I do a PDP-11 in a chip, I could have used the RT-11 from the 8 inch floppies!!! > > I am also toying with the idea of a Forth processor. > > Try: http://www.cse.cuhk.edu.hk/~phwl/msl16/msl16.html, it runs 3 > instructions per memory access, runs on a XC4006E. Yes, I found that site today, thanks. > > > Linux tradition would be really nice. Momental state of investigation > > > seems to be: no Linux tools. > > > > That is totally true except for some of the smaller chip vendors. > > Which? I know that Atmel offers free software for under Win95, WinNT, SunOS and HP Unix operating systems. I guess I was wrong about Linux. I do know that ModelSim is available for Linux, but that is far from free (beer). > > I think you will find the place and route time on even the > > fastest Sparc to take a lot longer than the download time for a > > configuration file. > > This being? Worst case I can start and log out. I don't know what it takes on a Sparc, but my place and route times for a 4013 design are from 30 min to an hour on a 233 MHz PC. I guess this may shrink a lot on a current Sparc. > > If you are working over a phone line, what happens if you try to run a > > tool that is inherently graphical, like a chip editor? One of these > > programs does not update the screen all that fast on a dedicated PC. You > > might be much better off biting the bullet and working on a local PC. > > Editing will have to be local. But with the target being ASCII files > with publically specified content (EDIF, XNF) that is something I can > write myself if neccessary. So only non-graphical compiling will need > the Sun. You are thinking about the source. But there are other tools that need to show you the chip layout, floorplanner for one. I also use EPIC which actually lets you connect the dots inside the chip in infinite detail. If I have any doubt about what the design is doing (usually *after* place and route) I go into the chip editor (EPIC) and look at the funny little lines and the little squares to see what the chip really is doing. This involves boatloads (thats a technical term invented by Dave Berry) of graphics. > > > So generating EDIF or XNF ASCII files by some means and then compiling > > > them to bitstreams on a Sun or WINE is all the tools I need? > > > > You make that sound so simple, but yes. > > Where are the difficulties? What are these? You are the one who is going to do it, right? I will let you tell me after you have tried. Maybe it is no big deal. I think it can be done easily in forth if you know what you want in terms of a design. I just don't know how easy it will be to read the resulting HDL source that way. Hierarchical design by schematic can be a bear to see what you really have. You can't see all the levels at the same time. I have the same problem with VHDL. I think I should learn to apply software development techniques to my hardware. One problem is that I feel a very strong need to optimize my design for single cycle speed and this often requires iterative design. Then you need to see many levels of the heirarchy at the same time. > > What is "this box here"? Do the chip vendors offer tools for it? > > AMD K6-2 350 running Linux 2.2.13. So you want tools that run under Linux, right? Why does that require open source? > > If your design is not too complex, > > If I am making own boards (wire wrap perfered), I am limited to PLCC84, > so 20x20 CLBs (XC4010) seems to be the limit (and enough for the first > few projects, use 2 of them if neccessary). Any reason that you can't buy a board with a larger chip? The chip cost of an XC4010 is about $45 which is not too far from the price of an assembled board with a newer, larger chip like a Spartan or Spartan II on it. I don't use these "prototype" boards, so I don't know exactly what is available. But I thought there were boards for $159 from Xess. I looked at their site and the price is right, but it is only a Spartan XCS-10 on board. They inflate the gate count a bit compared to the 4000 series. But I expect they will have a Spartan II product out soon. This should give you a lot of bang for the buck and you won't have to worry about board construction. I really don't recommend that you wire wrap an FPGA board. The power decoupling is much too sensitive for that I think. > How big a limit is that? I have no experience to range this as > "cripling, toys only" or "only stops big commercial projects". I am doing a "small" design and I did not get past the 500 line limit until I started working on the testbench. But that does not stop the simulator. It only slows it by 10x or so. It is a PITA though. I guess they just can't give away all the tools. But don't get me started on the ModelSim XE license. If you pay $995, you get the right to use a *higher* cripple level (8000 lines instead of 500) for a year. Xilinx does all their licencing on a time limited basis. I would have bought a set of tools myself since I do consulting. But not with this license. > So more like Java bytecode, level wise, but still ASCII formatted. Now you are talking Greek to me. And Greek is the only language I don't speak. But it is not at all like any assembly language or p-code or other language construct. I think the software analogy breaks down here. It is just a list of parts and connections (wires) between the parts. > > You can generate EDIF from VHDL or C or even Forth if you have the mind > > to do that. But others are working in that area (not the Forth... yet). > > You should do some searching on the web to get info. > > I have already found Jan Grays CNets (C++ based) on the fpgacpu website. Good luck in that department. You can have lots of fun with this stuff using C or other languages. But if you want to experiment with the FPGA to do fun and/or useful stuff that explores the limits of the FPGA rather than pushing the limits of the tools, you need to stick with something more conventional for a toolset. Sorry... :( -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26362
Andy Peters wrote: > > rickman wrote: > > > RcvDataRegister: process (SysClk, AsyncReset) begin > > if (AsyncReset = '1') then > > RcvDataReg <= (others => '0'); > > elsif (rising_edge (SysClk)) then > > if (SPIRiseClkEn = '1') then > > if (SPI_CSNot = '0') then > > RcvDataReg <= RcvDataReg(14 downto 0) & SP_DOut; > > else > > CTS <= RcvDataReg(9); > > end if; > > end if; > > end if; > > end process RcvDataRegister; > > > > This is a 16 bit shift register with a clock enable and a load signal. > > Oh, and I add a one bit register that gets loaded with the output of bit > > 9 when the register is not being shifted. Does this look anything like a > > language you have seen before? It doesn't to me! This is logic > > "synthesis"! > > Well, you forgot the async reset for CTS. :) > > And I would have written separate processes, which would be less > confusing (at the expense of more keystrokes). To wit: > > RcvReg : process (clk, reset) is > begin > if reset = '1' then > RcvDataReg <= (others => '0'); > elsif rising_edge(clk) then > if (clken = '1') and (csnot = '0') then > RcvDataReg <= stuff; > end if; > end if; > end process RcvReg; > > CTSReg : process (clk, reset) is > begin > if reset = '1' then > CTS <= '0'; > elsif rising_edge(clk) then > if (clken = '1') and (csnot = '1') then > CTS <= whatever; > end if; > end if; > end process CTSReg; > > The point, of course, is that the synth tool may or may not do what you > expect regarding the flop's clock enable. And it probably doesn't > matter, assuming the logic is correct. Oh, but it does matter, very much if you want to run at >50 MHz with SPIRiseClkEn driving the CE to boost your top clock speed. This is a common technique to operate much of a design at multiple clock cycles rather than in a single cycle. Often only a small portion of a design needs to run at the full rate and this lets you back off on the timing constraints for the other sections. I don't have the full tools yet, so I can't test it. But I remember from my previous experience with FPGA Express that if you want a CE, you need to put in in a separate IF with no ELSE clause as the outermost IF, just inside the clock test IF. Did that make sense? But of course I need to test that with the current tools. Actually, I seem to remember that I had a lot of trouble getting Express *not* to use the CE. I think it may have used the CE on *every* IF that had no ELSE. I chose to include the CTS in the same process since the logic is related and I think a separate section for a single FF is not always warranted. I am not worried about the startup state of CTS since it follows the state of the register. So it will not have a problem being unknown on startup in the simulation. The default in a chip is reset. But really, I forgot... thanks. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26363
Andy Peters wrote: > > rickman wrote: > > > > Andy Peters wrote: > > > Project I'm working on: Classified. > > > When am I going to buy parts: 2010. > > > How many I am going to buy: one. > > > > Andy, you are just *not* a fun guy!!! > > > > Ya' know, reps are people too! It doesn't really hurt to talk to them > > once in awhile does it? You might be surprised at what they can do for > > you sometime. > > Actually, I spoke to ours last week! She gave me some good leads on the > fast ethernet stuff I've been looking for. > > I think most of us would agree, though, that if we're just "surfing" for > potential parts, we'd rather not be bothered by salespersons. That may be your ideal situation, but if you get a phone call asking your level of interest, you can easily just say, I'm only window shopping and I have no project and no chance of funding. They are calling you because they have to fill out reports and project sales estimates. It is a little like a cop giving a ticket. They don't necessarily like it a whole lot either. But it is part of their job. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26364
Hi,
i use a Xilinx fifo and devider core in my design and want to simulate it
functionally.
What have i done?
1. I compiled the XilinxCoreLib with ModelSim
2. include all parts of the .VHO file also the configuration
but while compiling the top level ModelSim give the folowing Warnings:
# WARNING[1]: .....vhd(1021): No default binding for component:
"div_21_14si1". (No entity named "div_21_14si1" was found)
# WARNING[1]: .....vhd(1054): No default binding for component:
"fifo_1023_32". (No entity named "fifo_1023_32" was found)
and when loading the design there are this warnings:
** Warning: Component dividerxp is not bound.
# Time: 0 ns Iteration: 0 Region: /unidaq2
# ** Warning: Component divideryp is not bound.
# Time: 0 ns Iteration: 0 Region: /unidaq2
# ** Warning: Component pfifo0 is not bound.
# Time: 0 ns Iteration: 0 Region: /unidaq2
So i'm not sure if the configuration is ok
configuration cfg_SHC of U2 is
for SHC
-- synopsys translate_off
for all : fifo_1023_32 use entity
XilinxCoreLib.async_fifo_v2_0(behavioral)
generic map(
c_wr_err_low => 0,
c_has_rd_count => 0,
c_has_rd_ack => 0,
c_wr_ack_low => 0,
c_has_wr_count => 0,
c_has_wr_ack => 0,
c_has_almost_full => 0,
c_has_almost_empty => 0,
c_wr_count_width => 2,
c_rd_count_width => 2,
c_has_rd_err => 0,
c_data_width => 32,
c_has_wr_err => 0,
c_rd_ack_low => 0,
c_rd_err_low => 0,
c_fifo_depth => 1023,
c_enable_rlocs => 0,
c_use_blockmem => 1);
end for;
for all : div_21_14si1 use entity XilinxCoreLib.dividervht(behavioral)
generic map(
signed_b => 1,
divclk_sel => 1,
fractional_width => 14,
fractional_b => 0,
divisor_width => 14,
dividend_width => 21);
end for;
-- synopsys translate_on
end for;
end cfg_SHC;
Is there someone who can help ?
Thanks !
Uwe
Article: 26365Hi, I have Xilinx Virtex chips and I use Synopsys FPGA Express for synthesis. But I am new and have some questions. What's the different between FPGA Express, Compiler II, Synopsys DC? I am looking for good books which deal with synthesis especially with Xilinx and FPGA Express. I found *) VHDL Design Representation and Synthesis (James R. Armstrong) *) VHDL: Coding and Logical Synthesis with Synopsis at www.amazon.com Is one of them the right book for me? Suggestions? Thx & Greetings, Franz Hollerer -- Institut fuer Hochenergiephysik Nikolsdorfer Gasse 18 1050 Wien Austria Tel: (+43-1)5447328/50Article: 26366
Franz Hollerer wrote: > > Hi, > > I have Xilinx Virtex chips and I use Synopsys FPGA Express for > synthesis. > But I am new and have some questions. > > What's the different between FPGA Express, Compiler II, Synopsys DC? FPGA compiler II is a extended version of FPGA express, with a better quality of results aditionional functionnalities (retiming for ex). In practice (i.e. after P&R) they give very similar results (unless you manage to use the retiming feature of fc2, which is not easy) Synopsys DC is the scripting language used in older versions of synopsys tools (but which can still be used in fc2) > > I am looking for good books which deal with synthesis especially with > Xilinx and FPGA Express. Yous hould have a look to http://toolbox.xilinx.com/docsan/3_1i/ there is a section about VHDL for FPGAs. Steven > > I found > *) VHDL Design Representation and Synthesis (James R. Armstrong) > *) VHDL: Coding and Logical Synthesis with Synopsis > at www.amazon.com > > Is one of them the right book for me? Suggestions? > > Thx & Greetings, > Franz Hollerer > > -- > Institut fuer Hochenergiephysik > Nikolsdorfer Gasse 18 > 1050 Wien > Austria > > Tel: (+43-1)5447328/50Article: 26367
Hi Steven, it seems you know a lot about FPGA Compiler II and FPGA Express. I have a problem with the timing constraints in FPGA Compiler 2: How can I set them more flexibel - inputs are set to be before clock and outputs are set to be after clock; this seems not very comfortabel to me. Do you know how do change these automatically settings ? with regards, Georg Heinrich Steven Derrien wrote: > Franz Hollerer wrote: > > > > Hi, > > > > I have Xilinx Virtex chips and I use Synopsys FPGA Express for > > synthesis. > > But I am new and have some questions. > > > > What's the different between FPGA Express, Compiler II, Synopsys DC? > > FPGA compiler II is a extended version of FPGA express, with a better > quality of results aditionional functionnalities (retiming for ex). In > practice (i.e. after P&R) they give very similar results (unless you > manage to use the retiming feature of fc2, which is not easy) > > Synopsys DC is the scripting language used in older versions of synopsys > tools (but which can still be used in fc2) > > > > > I am looking for good books which deal with synthesis especially with > > Xilinx and FPGA Express. > > Yous hould have a look to http://toolbox.xilinx.com/docsan/3_1i/ there > is a section about VHDL for FPGAs. > > Steven > > > > > I found > > *) VHDL Design Representation and Synthesis (James R. Armstrong) > > *) VHDL: Coding and Logical Synthesis with Synopsis > > at www.amazon.com > > > > Is one of them the right book for me? Suggestions? > > > > Thx & Greetings, > > Franz Hollerer > > > > -- > > Institut fuer Hochenergiephysik > > Nikolsdorfer Gasse 18 > > 1050 Wien > > Austria > > > > Tel: (+43-1)5447328/50 -- mail from: Georg Heinrich mailto:georg@eas.iis.fhg.de http://www.xgeorg.deArticle: 26368
Georg Heinrich wrote: > > Hi Steven, > it seems you know a lot about FPGA Compiler II and FPGA Express. > I have a problem with the timing constraints in FPGA Compiler 2: > How can I set them more flexibel - inputs are set to be before clock and > outputs are set to be after clock; > this seems not very comfortabel to me. > Do you know how do change these automatically settings ? Sorry, I don't. But you might be able to do it using the scripting tools and some variables to store your clock period input/output delay constraints. Steven > > with regards, > Georg Heinrich > > Steven Derrien wrote: > > > Franz Hollerer wrote: > > > > > > Hi, > > > > > > I have Xilinx Virtex chips and I use Synopsys FPGA Express for > > > synthesis. > > > But I am new and have some questions. > > > > > > What's the different between FPGA Express, Compiler II, Synopsys DC? > > > > FPGA compiler II is a extended version of FPGA express, with a better > > quality of results aditionional functionnalities (retiming for ex). In > > practice (i.e. after P&R) they give very similar results (unless you > > manage to use the retiming feature of fc2, which is not easy) > > > > Synopsys DC is the scripting language used in older versions of synopsys > > tools (but which can still be used in fc2) > > > > > > > > I am looking for good books which deal with synthesis especially with > > > Xilinx and FPGA Express. > > > > Yous hould have a look to http://toolbox.xilinx.com/docsan/3_1i/ there > > is a section about VHDL for FPGAs. > > > > Steven > > > > > > > > I found > > > *) VHDL Design Representation and Synthesis (James R. Armstrong) > > > *) VHDL: Coding and Logical Synthesis with Synopsis > > > at www.amazon.com > > > > > > Is one of them the right book for me? Suggestions? > > > > > > Thx & Greetings, > > > Franz Hollerer > > > > > > -- > > > Institut fuer Hochenergiephysik > > > Nikolsdorfer Gasse 18 > > > 1050 Wien > > > Austria > > > > > > Tel: (+43-1)5447328/50 > > -- > > mail from: Georg Heinrich > mailto:georg@eas.iis.fhg.de > http://www.xgeorg.deArticle: 26369
Hi everybody! In my design I have to implement a couple of 8x8 bit multipier. One coefficient is constant. Since I have to change this constant coefficient in runtime (partial reconfig. of the Virtex chip) the easiest way would be a implementation just with LUTs (so I know the exact location of the LUTs and can change them). Has somebody an idea how I can handle this?? Thank you! LarsArticle: 26370
In the ATA spec., (for IDE hard disk drives), a parallel implementation of a
simple CRC generator polynomial is given.
Does anyone out there know how the serial->parallel conversion is done?
Cheers,
Bren
Article: 26371Have you tried the program KCM_VGEN available from Xilinx? It generates KCMs as netlists including RLOC information. Otherwise you could use the structure shown in the libraries guide under MULT_AND to implement the adders needed in the multiplier, and then use these adders to implement the KCM. Assigning the LUTs to specific locations can be done using the LOC and RLOC attributes. Dines -- -------------------------------------------- Dines Justesen // dcj@rescom.dk -------------------------------------------- "Lars" <Lotzen@intersci.com> wrote in message news:ee6e46a.-1@WebX.sUN8CHnE... > Hi everybody! > > In my design I have to implement a couple of 8x8 bit multipier. One coefficient is constant. > Since I have to change this constant coefficient in runtime (partial reconfig. of the Virtex chip) the easiest way would be a implementation just with LUTs (so I know the exact location of the LUTs and can change them). Has somebody an idea how I can handle this?? > > Thank you! > > LarsArticle: 26372
Does anyone know a source of an 8 pins DIP 17512 5V serial EEPROM - PROM?. Thank you GiuseppeArticle: 26373
Lars wrote: > > Hi everybody! > > In my design I have to implement a couple of 8x8 bit multipier. One coefficient is constant. > Since I have to change this constant coefficient in runtime (partial reconfig. of the Virtex chip) the easiest way would be a implementation just with LUTs (so I know the exact location of the LUTs and can change them). Has somebody an idea how I can handle this?? > > Thank you! > > Lars Four options. You can use the LUTs in RAM mode rather than as ROMs, and then wire through data buses, address lines etc. It adds more logic to your multiplier, since you need a mux on the inputs to the LUTs. If you take a look at my paper at FCCM this year, I show how you don't take a huge performance hit (I can send it you if you want). Second option is to use LUTs as ROMs and use JBits to change the LUT contents at run-time. Again, my FCCM paper shows how you do this. Third option is to use Xilinx app note XAPP151 to reveal the location of the LUTs, and do the same as option 2, but without JBits. Dont do that :-) Fourth option is to use the LUTs as SRL16 elements and serially stream in new values. Again, we have a paper showing how you do this. IMHO, if you are changing the constant fairly frequently, I suggest you use RAMs. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 26374
Hi, I am working on a design involving an FPGA which could be either a Xilinx or an Altera. I know Altera is about to propose a 5V compatible APEX without any glue outside and I was wondering if Xilinx has a similar part in the Virtex family. Thanks in advance for your time and information.
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