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Hi everyone.
I have written a vhdl design which I cannot fit in an Altera
flex10k100a-1 because of limited or problematic internal global signal
resources (I believe).
My design description:
I supply two external clocks to my design called clk and clk_half (one
is half the frequency of the other). The design processes some data using
internal counters and other operations, and, based on some conditons,
generates two other internal clocks using a 2-bit counter supplied by clk.
The genrated clocks are named clk_gen and clk_gen_half, where the frequency
of clk_gen equals that of clk_half, but its phase is offset by at most 2
cycles of clk, and clk_gen_half is half the frequency of clk_gen.
My problem is the following:
I compile my design in leonardo spectrum without any problems (my
design also compiles correctly in synplify). I then bring my design to
Altera maxplus2 and that's when the problems begin. Based on my description
description, I would like to assign the two internally generated clocks to
internal global signal resources. Based on the Altera databook and some
Atlas solution notes from the Altera web site, Altera claims that 4 internal
global resources can be allocated, in addition to the two dedicated clock
inputs. However, for each internal global used, a dedicated input is lost.
The flex10k100a has 2 dedicated clock inputs and 4 dedicated inputs.
I assign my external clk and clk_half to the dedicated clock pins and
assign the internally
generated clk_gen and clk_gen_half to two global primitives. This means
that I should still have 2 global resources free for other things (however,
they are not used). My assignments are done using an Altera constraints
file (.acf). I then run maxplus2 which fails during the fitter stage.
maxplus2 reports that design cannot fit. I let maxplus2 try the auto device
selection and the add devices as needed, but it stil cannot fit my design
(which only occupies 30 out of 4992 logic cells (LCs)).
I have tried many different combinations of global assignments (auto,
manually fored in acf, etc.), and the only one that maxplus2 can finish
succesfully is the one with only a single internal global assignment (clk
and clk_half are external globals, clk_gen is an internal global and
clk_gen_half uses internal logic. I also have an external reset but it
makes no difference if I assign to a global or not, either automatically or
manually). Even assigning globals to the 2 internal clocks and set
everything else to use standard routing fails the fit (only one internal
gloga succeeds).
I have read that I can route the generated clocks to output pins and
feed them back in to the chip using a dedicated input. However, Altera
claims that flex10k devices can use the dedicated resources directly from
within the chip without the need for external connections. Also, in my
current development board setup, I cannot connect an output pin to the input
pin because the board has alreay been designed and modifications are not
possible.
I am using maxplus2 ver9.64 (I have also tried ver9.60 but the
behavior is identical persists))
I have contacted Altera tech support but they have not answered my
question yet. That's why I decided to ask the vhdl/fpga community. I will
post their solution if they can solve this problem.
In the meantime, if anyone can provide some information from their
experience or some other source, I would greatly appreciate it.
Thanks in advance for your help and thanks for being so patient while
reading this long post.
Nestor
Article: 25076Thanks for your help. I guess I will need to add extra ports and open them in the final design... NestorArticle: 25077
"Ray Andraka" <ray@andraka.com> wrote in message news:39A66250.3090DD1B@andraka.com... > For this type of inquiry, I use the FPGA editor to see if something will work in > the architecture before I even start to code it. If you had done so, it would > have become immediately obvious that the silicon doesn't support what you were > trying to do. Thank you, I think this is very good advice. I already spend a lot of time in FPGA Editor! See also my piece on "The Knowledge" at <http://www.fpgacpu.org/xsoc2/log.html#the-knowledge>. However, in this case, it is neither obvious, nor documented, whether the slice latches are open when clk is high or when clk is low (independent of whether said clock is inverted). Point taken on the F6MUX of two dprams, oh well. Jan Gray Gray Research LLCArticle: 25078
Peter Alfke <peter.alfke@xilinx.com> writes: > "S. Ramirez" wrote: > > > Yoram, > > This is a side note to your question. Earlier, someone claimed that > > this newsgroup is dominated by Xilinx. Since it is an FPGA newsgroup, I > > would like to see Altera, Actel, Lucent, Quicklogic, Atmel, Lattice and > > others post what they have to answer Yoram's question. There is nothing > > stopping these vendors from posting various messages explaining what they > > have or answering questions and offering clarification. > > Well, Altera has a little self-inflicted problem. > They claim that even their big parts are not FPGAs, but rather CPLDs. > My theory is that they therefore think they need to ignore us here. Good point. Would you throw in the XCVxxxE in the discusion, if it had taken lpace in the comp.arch.cpld group? Or would you have bragged about your largest 9000-series? > I agree that the newsgroup would be better off with a free exchange of ideas > and comments. > As long as we avoid breast-beating and advertising... ... and snide remarks, even when followed by a smiley. :-) Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 25079
What's the problem? XCV300E has 32 BlockRAMs, each can be used as 512 x 8. So if you use all BlockRAMs,you have an array that is 512 deep and 256 wide. That's more than you need, and you have almost all CLBs left over to do interesting things :-) ( Virtex-E is just "better" than Virtex!) Peter Alfke,Xilinx Applications =============================================== Gerhard Griessnig wrote: > Gerhard Griessnig wrote: > > I need a RAM with a deep of 480 (impossible with virtex V300 - so i use for my project the half :240) and a width of 200 bits for implementing a switch for a realtime LAN. > The LAN is developed by us and has a special protokol which requiers 200 bits width packages. > > Is it possible to get all 200 bits into a 200 bit shift register in one Cycle (timing)? > > THANKS Gerhard > > Vhdlcode ? > > > I need to create a RAM in a XILINX-Virtex V300 with the XILINX Foundationtool. > > > > My problem is that my RAM has a width of 200 bits. > > > > Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a complex addressing.Article: 25080
"Nestor" <nestor@ece.concordia.ca> news:7pwp5.187831$Gh.3453711@news20.bellglobal.com... > Hi everyone. > > I have written a vhdl design which I cannot fit in an Altera > flex10k100a-1 because of limited or problematic internal global signal > resources (I believe). I suppose FLEX10K has only 2 global clock distribution network. Some confirmation you can gather from description of ClockLock and ClockBoost features. In general FLEX10K has many implicit restrictions, for example you can't place both input and output DFF into the same IOE. So I think you have to submit requirements and limitations generated by Maxplus2 (which of course based on real FLEX10K architecture). > > > My design description: > > I supply two external clocks to my design called clk and clk_half (one > is half the frequency of the other). The design processes some data using > internal counters and other operations, and, based on some conditons, > generates two other internal clocks using a 2-bit counter supplied by clk. > The genrated clocks are named clk_gen and clk_gen_half, where the frequency > of clk_gen equals that of clk_half, but its phase is offset by at most 2 > cycles of clk, and clk_gen_half is half the frequency of clk_gen. > > > My problem is the following: > > I compile my design in leonardo spectrum without any problems (my > design also compiles correctly in synplify). I then bring my design to > Altera maxplus2 and that's when the problems begin. Based on my description > description, I would like to assign the two internally generated clocks to > internal global signal resources. Based on the Altera databook and some > Atlas solution notes from the Altera web site, Altera claims that 4 internal > global resources can be allocated, in addition to the two dedicated clock > inputs. However, for each internal global used, a dedicated input is lost. > The flex10k100a has 2 dedicated clock inputs and 4 dedicated inputs. > > I assign my external clk and clk_half to the dedicated clock pins and > assign the internally > generated clk_gen and clk_gen_half to two global primitives. This means > that I should still have 2 global resources free for other things (however, > they are not used). My assignments are done using an Altera constraints > file (.acf). I then run maxplus2 which fails during the fitter stage. > maxplus2 reports that design cannot fit. I let maxplus2 try the auto device > selection and the add devices as needed, but it stil cannot fit my design > (which only occupies 30 out of 4992 logic cells (LCs)). > > I have tried many different combinations of global assignments (auto, > manually fored in acf, etc.), and the only one that maxplus2 can finish > succesfully is the one with only a single internal global assignment (clk > and clk_half are external globals, clk_gen is an internal global and > clk_gen_half uses internal logic. I also have an external reset but it > makes no difference if I assign to a global or not, either automatically or > manually). Even assigning globals to the 2 internal clocks and set > everything else to use standard routing fails the fit (only one internal > gloga succeeds). > > I have read that I can route the generated clocks to output pins and > feed them back in to the chip using a dedicated input. However, Altera > claims that flex10k devices can use the dedicated resources directly from > within the chip without the need for external connections. Also, in my > current development board setup, I cannot connect an output pin to the input > pin because the board has alreay been designed and modifications are not > possible. > > > I am using maxplus2 ver9.64 (I have also tried ver9.60 but the > behavior is identical persists)) > > I have contacted Altera tech support but they have not answered my > question yet. That's why I decided to ask the vhdl/fpga community. I will > post their solution if they can solve this problem. > > In the meantime, if anyone can provide some information from their > experience or some other source, I would greatly appreciate it. > > > Thanks in advance for your help and thanks for being so patient while > reading this long post. > > Nestor Valery Serebryansky. Novosibirsk State University.Article: 25081
--------------FDC03E1975523D87CC6224C2 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Rick Collins, Very good. An obvious reason why I want names is that if you have a complaint about a company and express the complaint it helps to know what company you are complaining about. As to an assertion that no one is reading the thread, I would say that fewer people are contributing to the thread. As to whether they are reading it I could not say, except if you are assuming a correlation of contributing with reading. You have implied some reason associated with me as to why they are not reading. If you have an argument to make, make it. It would appear there are areas of agreement, which at first may seem hard to find, between many of us--even you and I--such that a recommended policy that would be supported by most of us could be given. E.g., I would agree, as a part of the policy, to Jon's and other's recommendations that all documents a company requests to be signed be read carefully and not signed if there were sufficiently undesirable aspects to them of which some we may wish to detail. Also a marking of those documents for modifi- cations and corrections could be done. I think there may be better ways and additional considerations that may be addressed for this issue, but I will sign-on to that policy. Regards, Neil Nelson --------------FDC03E1975523D87CC6224C2 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <tt></tt> <br><tt>Rick Collins,</tt><tt></tt> <p><tt>Very good. An obvious reason why I want names is that if you</tt> <br><tt>have a complaint about a company and express the complaint it</tt> <br><tt>helps to know what company you are complaining about.</tt><tt></tt> <p><tt>As to an assertion that no one is reading the thread, I would</tt> <br><tt>say that fewer people are contributing to the thread. As to</tt> <br><tt>whether they are reading it I could not say, except if you</tt> <br><tt>are assuming a correlation of contributing with reading. You</tt> <br><tt>have implied some reason associated with me as to why they are</tt> <br><tt>not reading. If you have an argument to make, make it.</tt><tt></tt> <p><tt>It would appear there are areas of agreement, which at first</tt> <br><tt>may seem hard to find, between many of us--even you and I--such</tt> <br><tt>that a recommended policy that would be supported by most of us</tt> <br><tt>could be given. E.g., I would agree, as a part of the policy,</tt> <br><tt>to Jon's and other's recommendations that all documents a company</tt> <br><tt>requests to be signed be read carefully and not signed if there</tt> <br><tt>were sufficiently undesirable aspects to them of which some we</tt> <br><tt>may wish to detail. Also a marking of those documents for modifi-</tt> <br><tt>cations and corrections could be done. I think there may be</tt> <br><tt>better ways and additional considerations that may be addressed</tt> <br><tt>for this issue, but I will sign-on to that policy.</tt><tt></tt> <p>Regards, <p>Neil Nelson</html> --------------FDC03E1975523D87CC6224C2--Article: 25082
Magnus Homann wrote: > Peter Alfke <peter.alfke@xilinx.com> writes: > > Would you throw in the XCVxxxE in the discusion, if it had > taken lpace in the comp.arch.cpld group? Or would you have bragged > about your largest 9000-series? > I think we can do without hypothetical arguments. This newsgroup is called comp.arch.fpga, and XCV3200E is the largest FPGA. I wanted to point out, as I have done before, that it is a disgrace for Altera to be totally absent from this newsgroup. The world considers their larger parts to be FPGAs. Politics and semantics cannot change that.. I don't want to have a monopoly on representing our industry. In this forum here, we can ventilate technical issues and ignore the marketing messages. Note that I used the conservative data for our chip. I'll be gone for a few weeks. Have fun without me. Peter AlfkeArticle: 25083
"K. Orthner" wrote: > I've received my copy of the Xilinx 3.1i software, and installed it this > morning. > > It seems to me that it doesn't support multiple entities in a single file! > I just want to check to see if anyone's run into the same thing. This is > what I did: > > 1. Installed it. > 2. Created new project (Since it doesn't seem to read 2.1i projects) > 3. Added all my source files from an old project. this includes "Ram.vhd", > which has a bunch'o'entities for different RAM constructs. > 4. Looked at the "Modules" window, where I found only the last entity in > any given file was displayed. You are getting the "default configuration" for the last entity/architecture in the file. This is a VHDL rule. You need to write and compile specific configurations for the specific entity/arch combinations you want to use. Then you can put everything in one file if you like. Otherwise, you need separate files for each default configuration. -- mike.treseler@flukenetworks.com or -- tres@tc.fluke.comArticle: 25084
Jens Hildebrandt wrote: > I have a problem with the names Synopsys_1999.10 uses for multiple > instances of a component created using the VHDL "generate" construct. > For instance, when using a construct like > > for i in 0 to 7 generate > instance_name: component_name port map ( > ... > ); > end generate; You need a label. It should have been a syntax error without one. MY_LABEL:for i in 0 to 7 generate ... end generate MY_LABEL; -- mike.treseler@flukenetworks.com or -- tres@tc.fluke.comArticle: 25085
Simon, Funny thing happened on the way to the forum: every time we make "the next monster FPGA" we say to ourselves: no one could possible use this much logic. Ten years ago, there was a presentation at a conference that was made that said, "if FPGA's had a million gates, they would be used instead of ASIC's...." Now, recently they said, "if FPGA's had ten million gates, they would be used instead of AISC's...." and, we are on our plan to meet and exceed that goal. Of course, the ASIC suppliers have raised the bar again, and brought up mixed signal, more gates, and other reasons why they should remain in business. ASIC designers are being told more and more often by their company management that they can either: A) start writing verilog for an FPGA, or B) look for employement elsewhere. It is very very very expensive to do deep-sub micron design. Risky, too. Imagine, if you will, that you need XX million gates to solve your problem (3G wireless is a good example). You can either buy existing FPGA's and prototype the product to get the contract and tell your boss that it is someone else's problem to cost reduce the design, or you can write really big company checks to try to get an ASIC to work and miss the market because all of your competition used FPGA's to get there ahead of you. Oh, cost reduction happens with FPGA's, too. We get better at making them, and the prices go down. Eventually they can be sold for under $10 each (Spartan). Austin Lesea, Xilinx "S. Ramirez" wrote: > Ben, > First of all, I didn't write what's below. Peter Alfke of Xilinx wrote > that. > Second, your question "what is the best cost/performance ratio?" is a > good question, but there is still a fringe need for costly chips that do a > lot. I guarantee you that someone is going to use those chips. It may not > be their best seller, but it will sell and it will help drive Xilinx's > technology down the road to even bigger chips that cost less per gate. As > Peter said, die shrinks will ensure that this happens. > -Simon Ramirez, Consultant > Synchronous Design, Inc. > > "Ben Franchuk" <bfranchuk@jetnet.ab.ca> wrote in message > news:39A5D6FC.2D7D3286@jetnet.ab.ca... > > "S. Ramirez" wrote: > > > > It's around 25 mm square, or an inch for you non-metric folks. > > > > Bragging about large chip size always gives me a creepy feeling. > > > > Here we have a bunch of engineers and layout designers who sacrificed > their > > > > lunch, their sleep, and their family life to squeeze the design as > small as > > > > they possibly could do it. > > > > And then somebody brags about how BIG the chip is. :-( > > > > But the real question is what is the best cost / performance ratio. > > Big chips cost TOO much. Small chips do TOO little. Plus the price > > of Sockets (What you want fix a computer board by replacing a defective > > chip - ha ha ha !) and the PCB complexity and clock speed all are factors. > > Ben. > > -- > > "We do not inherit our time on this planet from our parents... > > We borrow it from our children." > > "24 bit CPU's R us" http://www.jetnet.ab.ca/users/bfranchuk/index.html > >Article: 25086
"Ben Franchuk" <bfranchuk@jetnet.ab.ca> wrote in message news:39A62956.9F65459E@jetnet.ab.ca... > I wonder how much sleep the FPGA device engineers lose at > night from reading how pushed to the limit his designs are. They surely don't lose any sleep on my account. (So far my work has directly sold perhaps some dozens of inexpensive parts, but that may change.) Andraka, Freidin, Von Herzen, and their kin, now those guys really push the devices. But it is good to discuss these matters, maybe they will make a difference some day. A few years back, after pondering the utility of triple (!) ported embedded RAMs, I did hear from an FPGA designer -- praying that such things never come to pass. And while probably not cause-and-effect, Altera did address my 1997 concerns about implementing RISC cores in a 10K, through quadrupling the bandwidth to EABs in their 10KE family <http://www.fpgacpu.org/usenet/altera_cpus_dual_port_EABs.html>. > If he ever decided to form his own company and build FPGA's > his would be a very hot product. Nope, few have the requisite talents, and I are not one. Do not underestimate what a massive investment the Xilinxes and Alteras of the world have made. No, those high wizards trained in the mysterious arts of very deep sub-micron circuit design, those Ph.D.s in the tools groups, and their lawyers :-), have nothing to fear. Like so many others, I am content to frolic in the happy low-skew-clock, buffered-interconnect, perfect digital world abstraction provided by FPGAs. Jan Gray Gray Research LLCArticle: 25087
I have an application that requires the connection of a large amount of I/O between multiple FPGAs on a single PCB. The application requires one type of device to fan in/out to 8 each of a second type of device. Each connection requires about 6.4 Gbit of bandwidth in each direction. One connection scheme could use two 32 bit buses (one bus in each direction) between each of the eight devices and the one device. The bus bits would each run at 200 Mb/s. That's 64 single ended drivers/receivers on each of the eight devices and 512 single ended drivers/receivers on the other device. Does anyone have any experience with anything similar to the above and/or large amounts of high-speed interconnect between chips? What type of I/O was used (LVTTL, LVDS, HSTTL, etc.) What, if any type of terminations were used? Any other suggestions? I would like to avoid external terminations and reduce as much as possible the number of physical routes between the devices because of PCB real estate limitations.Article: 25088
Hello, I am considering using a PCI macro in an FPGA either Xilinx or Altera. I have no experience of macros but what I heard about the specific PCI macros is that there is no support for them that is if it fails (possible ???) nobody can help. If anyone has some experience with PCI macros I would be glad to know about it : what chip was used, was it difficult to use, were there unpleasant surprises (or good ones !?!). Thank you in advance. J.F. HassonArticle: 25089
elynum@my-deja.com wrote: > > Can someone tell me how I would proram a xilinx fpga with an 8052 using > a eeprom. Xilinx has a app note but it doesn't tell you a whole lot. I > was just wondering how I would use that setup with a serial port? > Was it XAPP058? Have you tried XAPP098, It's for Spartan FPGAs and it uses the "normal" configuration signals instead of JTAG Though I haven't tried it myself I think it does look like it tells you all you need to know to configure a Spartan (and perhaps other) FPGAs I haven't used the 805x but I guess it may be possible to use the serialport in mode 0, it may be easier to just use four/five port pins and bit-bang the signals --Lasse (+)--------------------------(+) | Lasse Langwadt Christensen | | Aalborg, Denmark | (+)--------------------------(+)Article: 25090
In article <39A5653F.476D642A@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > That should be reasonably easy to compare, at least relative to other marketing > parameters. I think right now that honor goes to the Altera APEX EP20K1500E. > That metric, however isn't really all that useful. If you just want memory Beleive me Ray, To my application this metric is useful. extarnal ram just does'nt fit. > without regard to the logic capabilities, then why not just use memory. Xilinx > devices have the ability to use the CLBs as memory as well as the block RAMs. > That, and the cell structure can make a xilinx design occupy less than half the > LUTs of an equivalent designin ALtera. Given equal number of LUTs, that could > be an awful lot of distributed RAM cells which could tip the balance the other > way. In evaluating a part, you really need to look at the whole picture, > including the tools and how they fit into your purchasing plans. > > yorams70@my-deja.com wrote: > > > > Hi. > > I would like to know what is the largest fpga in the industry in > > terms of internal RAM. (and I mean RAM that it's usage will not > > come on the cost of logic cells use). > > > > ThankX, > > Yoram. > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25091
This is on a similar thread running earlier (and now!).
If Actel and QuickLogic anti-fuse technology so small and quick, why
aren't these two companies leapfrogging each other to make the biggest FPGA
in the world? I read in an Actel book once that anti-fuses are cheap,
small, easy to make and very quick timing-wise. These are all very good
reason why they should be the biggest FPGAs out there.
Maybe anti-fuse technology has limitations that I don't know about.
I still stand by my statement that IO density and packaging will
ultimately limit the non-reprogrammable market to the smaller devices. This
is because FBGAs are too hard to remove/replace and very dense sockets are
relatively unreliable. Maybe this is the REAL reason that Actel and
Quicklogic aren't progressing as fast as Xilinx and Altera.
If there is an Actel or Quicklogic expert or representative in this
newsgroup, maybe you can enlighten me on why these two companies have not
dominated the "largest FPGA in the world" market.
Article: 25092This is a multi-part message in MIME format. --------------A59AB11E775DBAA9C0021A7C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit What is the idea of making the read data outputs of the Virtex BlockRAM registered by the clock? This seems to be a time waster when using the BRAM as storage for an asynchronous fifo (or other possible applications). Consider the case where we use one port to write, and the other to read. If I write data in one side, then on the read side I must wait, not only until I've registered that there is data available in the memory, but an entire extra clock cycle after that, to apply a read clock to the device in order to get the data out of the memory. The app note, XAPP130, states: "7 The output ports are latched with a self timed circuit to guarantee a glitch free read. The state of the output port will not change until the port executes another read or write operation." I'd like to see the read port change when the write port operates, like the distributed ram behaves. Why is it necessary to latch the output ports for a 'glitch free read'? Shouldn't a stable read address be enough? In a dual port ram, there is no way to guarantee that a read at a given location will be completely valid if there is a simultaneous write to same location on the other port. (See arbitration/metastability discussions) So why not allow the read data to get out faster? Why hide it for a clock cycle behind an output register? I can see that having the registers built-in on the BlockRAM device may allow faster system clock, and thus greater throughput for some apps. But latency counts for something too. The registered output adds one clock cycle of latency, when the read address is already set-up. This may degrade applications (like fifos, or interprocess semaphores) where latency might be as important (or more so) than throughput. I'm sure the app note would mention it if there was, but ask the group anyway: Is there any way to put the Virtex BlockRAM into a direct read mode? Registering the output data is something that should be optional, available to the designer either through a configuration option for the ram, or via regular CLB registers (how do the Virtex II BlockRAMs handle this?). ( The main reason I ask is that a co-worker is trying to reproduce an obsolete discrete fifo, where the output data appeared after the write pulse, before any read command is issued. I suggested he could use the distributed ram rather than the block ram, but yet I want to eat my cake, and still to have it: it would be nice if the BRAM had direct outputs! I suppose BRAM throughput was the prime driver for the registered only outputs) Thanks all for listening, John --------------A59AB11E775DBAA9C0021A7C Content-Type: text/x-vcard; charset=us-ascii; name="jsmith.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="jsmith.vcf" begin:vcard n:Smith;John L. tel;work:858-320-4102 x-mozilla-html:FALSE url:http://www.visicom.com org:Visicom;Imaging Products adr:;;10052 Mesa Ridge Court;San Diego;CA;92121;USA version:2.1 email;internet:jsmith@visicom.com title:Principal Engineer x-mozilla-cpt:;30864 fn:John L. Smith end:vcard --------------A59AB11E775DBAA9C0021A7C--Article: 25093
Since there was some confusion: For large on-chip memories,Xilinx has a specialized subfamily, called Virtex-EM with only two members: XCV405E and XCV812E. XCV812E has 280 BlockRAMs, each 4K bits with true dual-ported access. lus a lot of potential RAM bits in the distributed RAM (16 bits per LUT = 64 bits per CLB) The largest member of the "normal" ( not memory-heavy) Virtex-E family is XCV32000E with 208 BlockRAMs, and significantly more CLBs and thus distribuetd RAM. Data sheets are on the web. TheXC3200E is also covered in the printed 2000 data book since it is "just" the largest member of the established Virtex-E family. Both parts are available, the XC812E is "older", smaller, and less expensive. Peter AlfkeArticle: 25094
I had explicit experience with an american and an indian company when we have been looking for a USB fpga core for a camera design - both good and bad. I would like to exchange thoughts with someone who also experienced (or is in the stage of searching) a USB fpga core in his / her design. Thanks for any response. Matthias m.monhart@freesurf.chArticle: 25095
S. Ramirez wrote: > > This is on a similar thread running earlier (and now!). > If Actel and QuickLogic anti-fuse technology so small and quick, why > aren't these two companies leapfrogging each other to make the biggest FPGA > in the world? I read in an Actel book once that anti-fuses are cheap, > small, easy to make and very quick timing-wise. These are all very good > reason why they should be the biggest FPGAs out there. > Maybe anti-fuse technology has limitations that I don't know about. > I still stand by my statement that IO density and packaging will > ultimately limit the non-reprogrammable market to the smaller devices. This > is because FBGAs are too hard to remove/replace and very dense sockets are > relatively unreliable. Maybe this is the REAL reason that Actel and > Quicklogic aren't progressing as fast as Xilinx and Altera. > If there is an Actel or Quicklogic expert or representative in this > newsgroup, maybe you can enlighten me on why these two companies have not > dominated the "largest FPGA in the world" market. I can think of three reasons : ISP, Testing, and Yields ? Last time I looked anti-fuse devices were not ISP, and had quite slow pgm times. I can imagine it's quite easy (well, fast) to test a RAM based device, but how do you test your brand new, OTP device ? PGM a bundle with a swag of test patterns .. Then you have fault analysis issues - was that a one-0ff fail, or do we need to fix the mask. Lastly, I believe the really big SRAM devices are getting some form of redundancy, to help yields. With an OTP device, you cannot test it until you pgm it, so you have only yield indicators, and the customer handles your yield fall out.. -jgArticle: 25096
Hello all, I've downloaded Brian's test case and logged a CR for this Map bug. Eventually, Xilinx solution #10026 will contain information about when this problem will be fixed. If only every test case that came my way were so well documented. :-) Regards, Bret Wade Xilinx Product Applications brian_m_davis@my-deja.com wrote: > on 8/6/00, Jan Gray wrote: > > >I am working on optimized processor cores for Virtex > >and I have a strange result, perhaps a bug in the tools. > >This problem is with F2.1i SP6. > > <snip description of latch/write clock polarity problems> > > I hadn't used Virtex/Spartan-II CLB latches before; > after experimenting with them for a while, I'd say it's > definitely a bug. > > Problem Summary: > > The problem occurs in both 3.1i SP2 and 2.1i SP6. > > MAP and PAR have their clock polarity packing rules > backwards: when packing latches with clocked memory > elements, they reject the valid combinations and > allow the invalid ones. > > In the resulting hardware, the latches have the > polarity that was specified, but the clock sense of > the RAM or SRL16 elements is inverted. ( Verified > both by simulation and in hardware using a XC2S100 ). > > More Info: > > ftp://members.aol.com/fpgastuff/ > > latch_bug1.txt more info on problem and test cases > > latch_bug1.zip: > latch_bug1.txt > ram_test\ design using RAM's > srl_test\ design using SRL16's > > Brian Davis > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 25097
But he's not using a 300E, he's using a 300. In that case he's only got 16 BRAMs, which only gets him to a depth of 256. My point was if he's not using all the logic, he could use it to make up the deficit. He'll use up about 1/3 of the CLB's but if that logic is not otherwise used, who cares? Peter Alfke wrote: > > What's the problem? > XCV300E has 32 BlockRAMs, each can be used as 512 x 8. > So if you use all BlockRAMs,you have an array that is 512 deep and 256 wide. > That's more than you need, and you have almost all CLBs left over to do interesting things :-) > ( Virtex-E is just "better" than Virtex!) > > Peter Alfke,Xilinx Applications > =============================================== > Gerhard Griessnig wrote: > > > Gerhard Griessnig wrote: > > > > I need a RAM with a deep of 480 (impossible with virtex V300 - so i use for my project the half :240) and a width of 200 bits for implementing a switch for a realtime LAN. > > The LAN is developed by us and has a special protokol which requiers 200 bits width packages. > > > > Is it possible to get all 200 bits into a 200 bit shift register in one Cycle (timing)? > > > > THANKS Gerhard > > > > Vhdlcode ? > > > > > I need to create a RAM in a XILINX-Virtex V300 with the XILINX Foundationtool. > > > > > > My problem is that my RAM has a width of 200 bits. > > > > > > Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a complex addressing. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25098
On Fri, 25 Aug 2000 19:31:08 GMT, "Jan Gray" <jsgray@acm.org> wrote: >Like so many others, I am content to frolic in the happy low-skew-clock, >buffered-interconnect, perfect digital world abstraction provided by FPGAs. I agree, except that I don't understand what the word "Frolic" means. Folic is the brand my dogs favourite snack. However I do like low skew clocks. / Jonas ThorArticle: 25099
At those rates you'll probably want to be doing single source and singel destination on all the signals, and even then you'll want to be careful about trace impedances. Steven DeLong wrote: > > I have an application that requires the connection of a large amount of > I/O between multiple FPGAs on a single PCB. The application requires one > type of device to fan in/out to 8 each of a second type of device. Each > connection requires about 6.4 Gbit of bandwidth in each direction. > > One connection scheme could use two 32 bit buses (one bus in each > direction) between each of the eight devices and the one device. The bus > bits would each run at 200 Mb/s. That's 64 single ended > drivers/receivers on each of the eight devices and 512 single ended > drivers/receivers on the other device. > > Does anyone have any experience with anything similar to the above > and/or large amounts of high-speed interconnect between chips? What type > of I/O was used (LVTTL, LVDS, HSTTL, etc.) What, if any type of > terminations were used? Any other suggestions? > > I would like to avoid external terminations and reduce as much as > possible the number of physical routes between the devices because of > PCB real estate limitations. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
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