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Hi, "Nestor" <nestor@ece.concordia.ca> wrote in message news:JIUm5.141833$1h3.2697602@news20.bellglobal.com... > Hi Everyone. > > My problem is how to access signals internal to that UUT. I am able to > access these internal signals within the simulator's graphical view, but I > cannot export that information in a readable format using the simulator's > menus. Is there a way to achieve what I want using the VHDL syntax directly > within the VHDL testbench? The straight forward answer would be a "NO" especially if you don't intend to touch your design under test. (Putting signals in package, or adding those in the entity.. - I don't prefer these 2 solutions, and I would prefer NOT to change my design in order to verify it). Having said that, in your case as far as I understand you could do it possibly with your Simulator's scripting language (WHich simulator are you using?). For instance Cadence's NC-Sim has TCL interface and you could probe signals with probe -create ... -vcd Else you could also do a "watch" on these signals and "re direct" the outputs to a file and use PERL to extract. Another elegant option could be to develop a simple C-program to dot his task and integrate it via the C-API of your simulator. Again this is Simulator specific. Finally as a remainder, with the Simulator's interface you have access to the complete design and not just the interface. Good Luck. SriniArticle: 24776
In article <399C8D39.3B03241D@yahoo.com>
spamgoeshere4@yahoo.com "rickman" writes:
> "Paul E. Bennett" wrote:
> > Anyway, that is the jist of it. I have seen some agreement documents which
> > look like they need many man-years of Harvard Law School training just to
> > be able to read them. You should be able to compose the fully legitimate
> > terms into a one or two page document at most.
>
> Your summary of an NDA is general, but not always accurate. Each one is
> unique and may contain some very different clauses. For example, the one
> that I made the modification to very clearly indicated that the company
> not only was not willing to keep my sensitive information confidential,
> and that I would not disclose any sensitive information to them. This
> keeps me from ever pursuing a suit against them.
In which case you are better off not signing them and took the right
course of action. In English Law (UK) a contract that is binding "HAS
TO BE FAIR". In other words it has to offer protection to both parties.
> Further, the modification I wanted to make was to document the the
> sensitive information. It would be in their interest not to document
> this as they could later claim any information was part of the
> interview.
I supose you could have really flummoxed them by saying that as their
NDA document was so one-sided that they should sign yours instead. I
suppose you would have had the same result though.
> This was a very one-sided agreement which was done to protect the
> company at the expense of the interviewee. This is not unusual.
As I said, agreements should be seen to be fair to both parties.
--
********************************************************************
Paul E. Bennett ....................<email://peb@amleth.demon.co.uk>
Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/>
Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE......
Tel: +44 (0)1235-814586 .... see http://www.feabhas.com for details.
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Article: 24777I'm reading above posts, about accepting Non Disclosure Agreements or not with great interest. And i was wondering if people outside the US had the same kind of experiences. I never had much to deal with such kind of paperwork in Europe, even when visiting competitors or doing interviews at their facilities. Probaly they are out here, for sure in higly competetive markets. (and maybe i'm not very much into these) And if the situation overhere is different for the moment, it will one day come as far as in the US... Anyone some experience , story's about such situations outside the US. StijnArticle: 24778
On Sun, 13 Aug 2000 14:59:21 -0700, Peter Alfke <peter@xilinx.com>
wrote:
>I don't understand how "Gray encoding" would work in a general-purpose state
>machine. Gray means ( to me at least ) that only one bit changes on any
>transition. That works very nicely in a counter, which is a specialized state
>machine with only one "next state" for every state. ( Well, two for an up-down
>counter )
>But it is inherently impossibel to have a single-bit change in a state machine
>where, depending on control inputs, the code might jump in many ways.
>So, what's the meaning of a "Gray-encoded" state machine?
You're right, of course, but to be fair to Synplify, the original
poster stated that he was using a "state encoding" of Gray, which
isn't actually the same as having a "gray-encoded state machine" -
this was a red herring introduced later.
Here's how it works in Spectrum - I'm not sure about Synplify, but I'm
pretty sure it's the same. In VHDL, you declare an enumerated type,
and give it an attribute which tells the synth to encode the type
with, among other things, a Gray code. You can do much the same in
Verilog using a synthesis directive to emulate an enumerated type. For
example:
type my_state_type is {S0, S1, S2, S3, S4};
attribute TYPE_ENCODING_STYLE of my_state_type : type is GRAY;
instructs the synth to create a new type which has the 5 values 000,
001, 011, 010, 110, for S0 through S4 respectively. What you do with
the type is up to you. For example, you could declare a signal of this
type and use the signal as a state register in an FSM. However, the
synth won't do *any* fancy analysis of your FSM, and certainly can't
create a Gray-coded FSM. If you happened to code your FSM such that it
went through the states S0 -> S1 -> S0, then you'd have made your own
Gray-coded FSM.
This isn't quite the complete story. There's a way to create
'implicit' FSMs in VHDL and Verilog, which requires you to specify
every clock transition sequentially and explicitly inside your process
(with multiple wait statements), which gives you an easy way to code
very simple machines. The advantage to the synth is that it can now
explicitly see the transitions in the FSM. Spectrum claims that it can
now use Gray coding for the FSM, but I haven't tried it. This is
probably just a curiosity - I wouldn't use it in real code.
Evan
Article: 24779Hi! You can also use PRINT SCREEN, and then you have a BMP that you can convert easily to gif/jpeg GabrieleArticle: 24780
On Thu, 17 Aug 2000 11:04:53 GMT, eml@riverside-machines.com.NOSPAM wrote: >On Thu, 17 Aug 2000 04:21:45 GMT, Peter Alfke <palfke@earthlink.net> >wrote: > >>Remember also, in Xilinx you can use a bigger part to do the job of a smaller >>part, without a speed penalty. > >I thought this had been fixed in Apex, by putting in segmented >routing. Anyone know for sure? Sometimes you can be fortunate and the bigger Apex part runs faster because the critical path fits all in one row nicely. Other times you can get unlucky and the routing across rows can really get in the way. Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 24781
stijn@easynet.be (Stijn Vanorbeek) writes: > Anyone some experience , story's about such situations outside the US. The only experience I have with NDAs is European and Australian : a) In Ireland, I was asked to sign an NDA before being told the details of an idea one employer had for a start-up company. The ideas, at that time, were not patent-protected and so the prospective employer needed the more specific form of protection that an NDA gives. As I ended up taking this job offer, it was not really a big deal... my employment contract contained much more restrictive conditions on any intellectual property that I might generate or come into contact with while being employed. b) In Europe and Australia: As a first step to forming a technical or business relationship with another company (or group), we have had them sign complementary NDAs with us. To a large extent it is the signing and the good faith that this entails, rather than the NDA itself, that is of interest. Ciao, Peter K. -- Peter J. Kootsookos Wb: www.clubi.ie/PeterKArticle: 24782
Some quotes from Synplify user guide: "Steps to instantiating a black box 1. Create an interface for the macro with no contents(you could have contents, but they will be ignored by Synplify). The interface only declares the ports and the port directions. You specify that Synplify should ignore the contents by putting the black_box synthesis directive just before the semicolon ';' in the module declaration." My Example: module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST) /* synthesis black_box */; output [15:0] DO; input [7:0] ADDR; input [15:0] DI; input EN; input CLK; input WE; input RST; endmodule "2. Make an instance for the stub in your design (just as you would do with any other module). 3. Compile the stub along with the module containing the instantiation of the stub." After synthesis the synthesis result file will contain a reference to the module name (RAMB4_S16) The rest is up to the Xilinx P&R tool. Good luck! Thomas Sedat NISANCI wrote: > > Hi. > I did not make an implementation with Xilinx devices and also > Symplify before.So, this is the problem: > > How can I instantiate the Block SelectRAMs (or any other blocks > inside device) in Verilog Code? > > Thanks, > SEDATArticle: 24783
"Vladislav Vasilenko" <vlad@comsys.ntu-kpi.kiev.ua> wrote in message news:399BF819.BB6DB61B@comsys.ntu-kpi.kiev.ua... > Where can I find techical information about this Atmel EEPROM ? > Best regards, Vlad. > The FPGA Configurators are available at: http://www.atmel.com/atmel/products/prod22.htm -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel SwedenArticle: 24784
hi , everybody have make a decoder MP3 with an FPGA ?Article: 24785
Don't you mean Atmel, not Actel? "B. Joshua Rosen" wrote: > > Xilinx has a serial prom that's made for the purpose. Actel also offers > Xilinx compatible serial proms. > > Ramy wrote: > > > > Hello, > > > > I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?) > > > > Also, If any of you know some web-sites that could provide information on programming FPGAs with PROM that would be helpful too. > > > > Thanks, > > Ramy -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24786
Ben Franchuk wrote: > > > I've finished programming my FPGA and the system is ready to be used. However, I must reprogram the FPGA after each power-up. I would like to implement a quick and simple solution to "save" the information...such as using a PROM. The FPGA I'm programming is the XC4010E-4PG191I chip using the XCHECKER cable via the serial port. Is there anyway to connect the PROM here instead? (or something else simple?) > > What I would like to see is a low cost development board > using Nonvol SRAM. The chips that look like core memory - on power > down they save to EEPROM and power up they restore to ram. > While the chips are slow 150ns and low density 64k bit they > would have the advantage for both programing FPGA's and use > as memory in CPU designs. You load both sets of chips from > the host computer and then take your board off to use else where. > Ben. What is the advantage of using such a nonvolatile SRAM chip over using an EEPROM or Flash? How does the SRAM add anything to the equation? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24787
Thomas Karlsson wrote:
>
>
> My Example:
> module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST) /* synthesis
> black_box */;
> output [15:0] DO;
> input [7:0] ADDR;
> input [15:0] DI;
> input EN;
> input CLK;
> input WE;
> input RST;
> endmodule
>
>
> After synthesis the synthesis result file will contain a reference to
> the module name (RAMB4_S16)
> The rest is up to the Xilinx P&R tool.
>
> Good luck!
> Thomas
Thanks al lot.Every thing is fine.
SEDAT
PS:For the Synplify v6.0 directive is syn_block_box.
module ..... /* synthesis syn_black_box */;
Article: 24788In article <399D0F1A.AC6339A0@emw.ericsson.se>, Thomas Karlsson <thomas.karlsson@emw.ericsson.se> wrote: >Some quotes from Synplify user guide: > >1. Create an interface for the macro with no contents(you could have <snip> > > My Example: > module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST) /* synthesis >black_box */; > output [15:0] DO; > input [7:0] ADDR; > input [15:0] DI; > input EN; > input CLK; > input WE; > input RST; > endmodule This module, and many others, are in virtex.v (virtexe.v), included with synplify. Maybe this is new? You may also wish to read the synplify help page on _inferring_ RAMS. This only works if the ram is single port, or dual port with common clock. It does make resizing the ram easy. Gyles. -- gyles@nortelnetworks.com All opinions expressed are my own, not those of Nortel Networks.Article: 24789
eml@riverside-machines.com.NOSPAM wrote: > > On Wed, 16 Aug 2000 16:30:45 -0500, Paul Smith <ptsmith@indiana.edu> > wrote: > > >It looks like the Mentor FPGA Advantage suite (Renoir, ModelSim, and > >Leonardo) will work for me. Anyone out there have experience with this > >toolset for the Spartan II target? > > > >I assume I also need the Xilinx Alliance software? > > You can't go wrong with ModelSim and Spectrum but, as for Renoir, > forget it unless you're a masochist and you've got lots of spare time. > If you need schematics, try to find a proper schematic tool you can > fit into your design flow. You'll need Foundation or Alliance as well. > > Evan > > PS: Ok, Mr. Mentor, that wasn't too bad, was it? I trust you won't be > mailing me about this.... :) I take it from the PS that you have gotten mail from someone at Mentor about your newsgroup postings? Have you had unpleasant experiences using the Mentor toolset? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24790
I have a number of exciting opportunities for IC Designers in the UK. If you have analogue or digital design experience and are seriously considering moving to the UK, my clients are able to help with work permits and visas. For further information, please email me your resume www.tom@goldgroup.co.uk or call Tom at Gold on +44 1444 884222 I have positions all over the UK and look forward to hearing from you.Article: 24791
John and Matthew,
Thank you for the information. I will certainly take a look at the data
sheet as well as the two books.
Artur
8.18.2000
Matthew Donadio wrote:
> "John B. Sampson" wrote:
> > Artur Leung wrote in message <399B5718.F6498094@REMOVEittc.ukans.edu>...
> > > I am working on a digital QPSK demodulator and run into problems of
> > >designing an all-digital phase-locked loop (ADPLL) for the carrier
> > >recovery circuitry.
> > >...
>
> > You might want to have a look at the data sheet for Intersil's Digital
> > Costas Loop IC. I think this IC implements much of what you want, and the
> > data sheet has lots of details on how it works.
> > ...
> > http://www.intersil.com/data/fn/fn3/fn3652/fn3652.pdf
>
> In addition to the datasheet for the HSP50210, these two books may be of
> some use:
>
> @Book{dig-sync,
> author = "Umberto Mengali and Aldo N. D'Andrea",
> title = "Synchronization Techniques for Digital Receivers",
> publisher = "Plenum Press",
> year = 1997,
> address = "New York",
> series = "Applications of Communications Theory"
> }
>
> @Book{sync-v2,
> author = "Heinrich Meyr and Marc Moeneclaey and Stefan A. Fechtel",
> title = "Digital Communication Receivers: Synchronization, Channel
> Estimation, and Signal Processing",
> publisher = "Wiley-Interscience",
> year = 1998,
> series = "Wiley Series in Telecommunications and Signal
> Processing",
> address = "New York"
> }
>
> --Matt Donadio (m.p.donadio@ieee.org)
--
--------------------------------------------------------------------------
Artur Leung aleung@ittc.ukans.edu
Research Engineer
Information and Telecommunication Technology Center
University of Kansas
Nichols Hall -- West Campus
2291 Irving Hill Road
Lawrence, Kansas 66044-7541
U.S.A. http://www.ittc.ukans.edu/~aleung
--------------------------------------------------------------------------
Article: 24792Here is a sample of some of the posts I am trying to fill in the UK. All of my clients are prepared to offer sponsorship for visas and work permits provided that you have enough experience. IC MASK DESIGNERS Perform challenging analog and mixed-signal IC mask layout on high-frequency Bipolar and BiCMOS technologies. Knowledge of UNIX, Sun Workstations, Cadence/Virtuoso, Avant! LTL and Hercules desirable. Must be hard working, work well in a team environment, and have excellent communication skills WIRELESS/RF IC DESIGN ENGINEERS Design and develop ICs for the wireless communications market. These ICs include transceivers, low-noise amplifiers, mixers, VCOs, synthesizers, IF circuits and RF power amplifiers at up to 6GHz operating frequency. Be responsible for product development from initial specification through circuit design, characterization, and product introduction. You must have experience in designing RF ICs in bipolar, BiCMOS, or CMOS technologies. LAYOUT ENGINEER Working within the Design group, you will be responsible for the layout of custom digital and analog circuit designs, using state-of-the-art design tools and techniques. You will be expected to assimilate design information from other developments, and to be a major influence on existing and future architectures that will shape solutions for the future. IC DESIGN ENGINEERS The specification, design, simulation and verification of next generation smartcard products. Interaction with customers and functional groups (e.g. Product Engineering, Marketing, Wafer Fabrication, Development Systems, Applications Engineering, Technical Publications). Analog and mixed signal design Custom circuit design Digital IC design Design for testability. SENIOR ENGINEER You will work on schematics generation, circuit and logic verification, product characterization, layout supervision, tapeout documentation, and mask checking for SRAM-based products. Prior experience working with HSPICE, schematic capture, logic verification, LPE, LVS, and DRC tools. A strong background in circuit, logic, and device physics. Written design documentation, presentation, and verbal communication skills. For further information, please contact tom@goldgroup.co.uk or call Tom at Gold on +44 1444 884222 I look forward to hearing from you.Article: 24793
"Paul E. Bennett" <peb@amleth.demon.co.uk> wrote in message news:966555960snz@amleth.demon.co.uk... > In article <8ngv2n$o0l$1@news.drenet.dnd.ca> > qn42@hotmail.com "Darren Kuhn" writes: > > > > I find this all kinda interesting considering I find myself on the opposite > > end of the scale, if I was to go for an interview I wouldn't be able to talk > > much about my abilities/areas of work because of the security issues > > involved in my present work...and I doubt they would sign a NDA from me. > > Should you be talking about such issues without authorisation from your > current employer? So, if you cannot talk about your current work how do > you convince someone else you are worth employing? > I wouldn't know as I haven't been looking for a change of venue. What I do know is that I can tell you the software/hardware systems that I work on, just not what I do with them.Article: 24794
Although most people like to lump Canada in with the US, in this case, it's true. There are NDA's used here in Canada, in the interview process. I can't say how wide-spread it is, but of the couple people I've talked to, they've all had to sign them. Stijn Vanorbeek <stijn@easynet.be> wrote in message news:399cf829.1984974@news.easynet.be... > I'm reading above posts, about accepting Non Disclosure Agreements or > not with great interest. > > And i was wondering if people outside the US had the same kind of > experiences. > > I never had much to deal with such kind of paperwork in Europe, even > when visiting competitors or doing interviews at their facilities. > Probaly they are out here, for sure in higly competetive markets. (and > maybe i'm not very much into these) > > And if the situation overhere is different for the moment, it will one > day come as far as in the US... > > Anyone some experience , story's about such situations outside the US. > > > > Stijn > >Article: 24795
Darren Kuhn wrote: > > "Paul E. Bennett" <peb@amleth.demon.co.uk> wrote in message > news:966555960snz@amleth.demon.co.uk... > > In article <8ngv2n$o0l$1@news.drenet.dnd.ca> > > qn42@hotmail.com "Darren Kuhn" writes: > > > > > > > I find this all kinda interesting considering I find myself on the > opposite > > > end of the scale, if I was to go for an interview I wouldn't be able to > talk > > > much about my abilities/areas of work because of the security issues > > > involved in my present work...and I doubt they would sign a NDA from me. > > > > Should you be talking about such issues without authorisation from your > > current employer? So, if you cannot talk about your current work how do > > you convince someone else you are worth employing? > > > > I wouldn't know as I haven't been looking for a change of venue. What I do > know is that I can tell you the software/hardware systems that I work on, > just not what I do with them. I have done a lot of government work over the last 20 years and I have never been restriced in discussing the technical issues of my job. Only the application and system level issues which may reveal application details. This is in contrast to the commercial jobs I have had where the high level stuff is very much open and the details are often confidential. To Paul, Darren said NDA, not NSA ;') -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24796
> > > > I wouldn't know as I haven't been looking for a change of venue. What I do > > know is that I can tell you the software/hardware systems that I work on, > > just not what I do with them. > > I have done a lot of government work over the last 20 years and I have > never been restriced in discussing the technical issues of my job. Only > the application and system level issues which may reveal application > details. > > This is in contrast to the commercial jobs I have had where the high > level stuff is very much open and the details are often confidential. Very true, one the one hand you say, here are the specs of the hardware I'm using, but I can't tell you what I use it for, and on the other, here is what I'm doing, here's our blackbox. > To Paul, > Darren said NDA, not NSA ;') I'm north of the 49th parallel...so it's definately NDA....or is it N(AFT)A?Article: 24797
In article <399B9AF2.1411B4A4@rsd.bel.alcatel.be>, Christophe Heyert <heyertc@rsd.bel.alcatel.be> wrote: > Hi all, > > I was wondering if it is possible to use the Virtex Dll's to create a > clock multiplied by a factor 8. > The application notes only discuss clocks multiplied by 2 or 4. > Thanks... > > Christophe > The answer is NO. There are four DLLs in Virtex devices, but to multiply by 2 you need at least two BUFGs (if the source clock is external, one could be IBUFG). Because the CLKIN input of CLKDLL must be driven by a BUFG, you can only drive one more CLKDLL and you are out of BUFGs. Also keep in mind, that the frequency range for CLKIN of CLKDLL is 25-90MHz and for CLKDLLHF is 60-180MHz. Don't forget also the fact, that you can only use BUFGs to connect to CLKDLLs from the same side of the chip. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24798
Hi, I've been working a couple of designs and have heard that "your design really should be fully contrained" to acheive the best results. Can someone give me a good definition of what fully constrained means? Are they implying that I should provide timing contraints for every net in my design? Thanks Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24799
<p.kootsookos@remove.ieee.org> schreef in berichtnieuws ubsysl3ol.fsf@remove.ieee.org... > rickman <spamgoeshere4@yahoo.com> writes: > > > The funny part was that on the way out they asked me to complete the > > signout procedure. While doing that they noticed that I had not signed > > the mini-NDA. This was pointed out. I pointed out that it was an NDA. I > > was asked to sign it by the HR person. I could not help but laugh a bit. > > It sounds like that company has been following procedures which were > laid out in the dim and distant past and that no-one remembers why. It > also seems that the people internal to the company have been doing it > for so long, they cannot understand why others might baulk at it. Brainless puppets on strings.... -- Met vriendelijke groeten, Frank Bemelman (reageren per email ? verwijder dan de 'x' uit mijn emailadres)
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