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On Tue, 22 Aug 2000 08:27:01 -0700, Neil Nelson <n_nelson@pacbell.net> wrote: >Your plan of action seems to be a recommendation that in the >case where a company requests written agreement to an NDA at >the interview that we do not take the interview. No. Not quite the way I'd say it. If a company recommends an NDA agreement at the first interview, I'd recommend a careful reading of exactly what the NDA says. If you don't feel you understand it, it if isn't clear and simple, then don't sign it. In most cases, I'd guess that a careful reading *cannot* be properly done on a short moment's notice. So they need to be prepared to give you a fair opportunity to read and understand its details and accept questions and discussion on its points. I wouldn't do a single further thing with them until that was completed. Nothing. When I am faced with these, I stop everything. We talk about the reasons that motivate it. If they are reasonable and I garner a good understanding of what it is they are concerned about, from direct discussions with them, I then reread the NDA with that new understanding. If it fails to achieve what I perceive they told me, then I confront those elements with them. In the end, a correctly written NDA that I believe properly reflects their legitimate interests can be achieved. But it usually takes some work. In the interim, I sign nothing at all. If it is a blanket NDA offered to all and sundry on their first contact (and to me without any particular regard) and contains nothing regarding the position in mind and pertinent discussions we expect to have, then there is no reason to sign at all. It's just them taking what they can from others without a care. It's silly to sign such legal documents. I'd think most rational people would agree that anytime you sign a legal contract that you do so with care and thought. The last time this happened, I spent the morning working with the company's attorney directly and we restructured the agreement to be fair and balanced before I signed it. It took less than an hour of his time and he was very, very reasonable about the process. He agreed with my comments and furiously struck out sections and reworded some to meet my needs. Why should anyone sign a blanket NDA on first contact, where the NDA takes nothing about the individual or their circumstances into account?? You still haven't bothered to answer that question, in spite on my bring it up several times. Frankly, I'm beginning to believe you cannot. >After having identified a primary objective and an initial >solution path, frequently we find that the identified solution >path is too weak in the likelihood of reaching the objective >or is against other desirable objectives such that we lose >elsewhere in making an advance here--we rob Peter to pay Paul. >This was a thrust of my prior post. > >But fortunately a single objective can be usually obtained in >a variety of ways such that we can search the different solution >paths to maximize the likelihood and efficiency of reaching the >objective while minimizing, say, collateral damage. That reads just as convoluted as it is, with only the most vague allusions contained in it. It's just scare tactics, though you may not have intended such. A company has no valid reason, none whatsoever, in confronting each and every person walking into their first interview, with an NDA to sign and worse, a blanket and non-specific NDA. End of story. JonArticle: 24951
Darin Johnson, I am not seeing anything particularly difficult about typing in a company name and short complaint with concrete details and posting it to the newsgroup. If I think some company has a problem with their interview procedure, why don't I save other people the hassle of going on the interview and finding it out for themselves? Why are these people so interested in not disclosing names, dates, and details? Why are we afraid to speak up? What happens when the job market (economy) goes against the job seeker; is it just tough luck? Regards, Neil NelsonArticle: 24952
Peter Alfke wrote:
> rk wrote:
>
> > I don't think the cost of prototype parts is a major issue, independent of the
> > technology, for many jobs.
>
> Yes, but the pain of unsoldering and re-soldering BGA parts is.
Agreed. Again, I haven't thoroughly tried out the socketing solution for these.
From the construction of some types, it doesn't look like the signal quality will be
hurt too badly. Anyone have any good hands-on experience with these? They have
little pins that stick out of the bottom onto the pads on the PCB and if I remember
correctly, little fuzz buttons on top to contact the balls. Currently, I haven't
used any BGAs except for a small test. Mostly I use flatpacks, PGA's, PLCC's, and
PQFP's.
I note that even flat packs (such as those used in military and aerospace
applications) take the care of an experienced technician and good equipment for
removal and replacement. After a number of cycles, pad damage starts to becomes an
issue, even with a good, careful technician. Some people like to use sockets to
avoid this problem that are surface mount on the bottom, PGA on top, for easy
removal and replacement; I personally don't prefer that approach.
==================================
> And isn't it nice to be able to change something on-the-fly, even in a complete
> system.
Of course. I think I said the following in the previous post:
I have to say I like the concept of the non-volatile, reprogrammable,
single chip,"instant-on" type of device.
There are of course trade-offs with any technology. Perhaps of interest to some,
there is a group, working with the Air Force Research Lab, working on the "holy
grail" memory technology. They were written up in the last issue of the AIAA
Aerospace America. They also have a paper at MAPLD 1999:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon99/Papers/P21_Tyson_P.PDF
=======================================
> But these arguments have been made over and over again,
> and many of us have an obvious axe to grind.
> (That includes me.)
I think I'll stick with what I said before, it seems reasonable, and perhaps not
even doing any grinding:-)
I agree that all different types will be kicking around for a while;
Xilinx, Altera, Actel, Quicklogic have all been around for a few years and
I haven't heard rumors that any of the them are close to closing up shop.
and
I think the device's characteristics and available tools and IP for the
particular application is more of a driver.
The point I made is that I don't think going through parts is a major issue, most of
the time, based on my experience. For projects that have trouble definining the
system, it can be an issue at times, independent of the care taken in the design and
analysis. If the project is very poorly planned and executed, that can be a
significant issue. That seems to be more the exception than the rule; usually
things are just poorly planned. :-)
Have a nice evening,
rk
Article: 24953
Peter Alfke wrote:
> <snip> >
> Now the good news:
> I have high hope (almost confidence) that, within a few months, I will
> have access
> to chips that allow me again to measure metastable delays easily, and
> thus re-issue the
> old exponential graphs with fresh data.
> Let's hope by Xmas...
Does that mean these chips are getting worse / degraded to the point
you are then able to measure metastable events again ;-)
( I know it's not what you meant, but it's {almost} what you said )
Article: 24954Yes, I am familiar with ERT. I read a lot in comp.dsp where the mere mention of his name is accompanied by horses whinnying (like Frau Brucher in "Young Dr. Frankenstein"). But sometimes it is fun to bait the troll... Simpleton Greives wrote: > > rickman wrote: > > I don't know where you got your information. > I would have to pass some information onto you: ERTisdale is somewhat known > around the net as a nonsense person. I personally don't know why and had > (until now) no personal reasons to believe one way or another, but there's > certain notoriety to his name. By looking at his response, I begin to > believe that these reports are not entirely without foundation. Really, > where did he get his information? Not from you original post, that's > fersure. OK, I'll go away now. > > -- > .-'~~~-. > .'o oOOOo`. > :~~~-.oOo o`. > `. \ ~-. oOOo. > `.; / ~. OO: > .' ;-- `.o.' > ,' ; ~~--'~ > ; ; > _\\;_\\//_ > nosedive. 4 all your munging needs -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24955
I am not trying to keep this thread alive, but I have received another per-interview packet from company C that I think just blows away the concerns I had with the previous Company A. Some of this may be because this interview is for a project management position for which the company may feel it is more important to properly evaluate a potential hire. But this is what they want me to bring to the initial interview. A completed application, A "consumer report" (otherwise known as a credit check) authorization, A Background questionnaire release form, Then they want me to leave behind a urine sample for drug testing. I can see the potential need for all of these things even if I don't agree that they should be used for employment screening. But I strongly disagree with the requirement to authorize them prior to an interview. And more importantly, I will not provide such an authorization to use this information without an opportunity for me to dispute any erroneous information contained in these reports. In fact I am not given any idea of how the information will be evaluated. Finally the company retains the right to perform further checks in the future (if hired) for "deciding whether to continue your employment", and " when making other employment related decisions directly affecting you". I have heard of people who were fired from their jobs based on incorrect credit information from fradulent use of their identities by other people. I am sure that this will get responses both pro and con to the reasons that a company may feel the need to "protect" themselves against harm from an employee. But these agreements go far beyond "protecting" a company and can very easily be used against an employee to permit dimissal without recourse or even explanation. Jeeze, I have gotten jobs with DOD contractors where I had to get a security clearance and did not have to submit any paperwork until *after* I was hired. At least with DOD, I knew that I would be given a chance to respond to any "anomalies" that they found. Maybe I really am paranoid... but that does not mean they are out to get me!!! William, if you are reading this, I enjoyed lunch today and I liked the company. Your company is one of two so far that I would like to get an offer from. (The other is company B). > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24956
Bob Perlman wrote: > > Hi - > > The way I remember the distinction: > > - Moore: outputs are a function of current state > - Mealy: outputs are a function of current state and inputs > > In other words, Moore is Less :-) Thanks, I will remember this! > I like Moore FSMs, and also like the idea of including outputs in the > state vector. But what I do is a bit different. If an output is > supposed to be HIGH during states FRED and WILMA, I generate a signal > whenever the next state is going to be either FRED or WILMA, and pass > that signal through a flip-flop. Strictly speaking, the output isn't > part of the state vector, but the result is the same: either way, > outputs occur concurrent with the change of state, without additional > state decode delay or decoder glitches. Not that designers of > synchronous systems care about decoder glitches... This is a modified Moore machine. The outputs are registered versions of the outputs and are calculated by performing the output function on the next state function rather than doing it on the current state with no register. > Mealy machines are useful, too. Sometimes a state machine has to > respond to an input by asserting an output signal in the same cycle, > and Mealy is more or less mandated. I like to think of this as a signal that is outside of the state machine. If the input and output signals are not registered then they are asynchronous (potentially) to the FSM. I find it easier to design the FSM with all synchronous logic and handle other signals as random logic using the FSM outputs. Just my preference... -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24957
Bob Perlman wrote: > > Hi - > > I'd like to respond, but the fact of the matter is that I no longer > have any idea what we're arguing about. > > Bob Perlman If you let a simple thing as that stop you from arguing a point, you should not be posting to newsgroups!!! ;) -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24958
I don't mean to nitpick, but I would like to request that you do something with your posting software to wrap your lines at some reasonable length such as 70 or 80 characters. Your post is very hard to read with all the horizontal scrolling required. Thanks, Robert Sturm wrote: > > Hi all- > > I'd like to apologize for the registration problems some of you were experiencing with our online case management tool on support.xilinx.com. We manually review each and every access request to WebSupport before granting a customer clearance to this utility. Security is a big concern for many of our customers and we want to do everything in our power to protect the intellectual property of our users. > > Recently, a spike in the number of WebSupport requests has delayed the processing of a typical submission. We've added a few resources to address this deludge and turnaround times should be greatly reduced within a few business days. Please note that users who try to login before their request has been approved will be redirected back to the registration page. Undoubtedly, this was what was happening in Ray's situation. Users who have been granted access will receive an email notification that they can start using the tool. > > We've deployed WebSupport to help you become more productive. This utility allows you to add notes, track changes, and manage cases without picking up the phone. Please don't hesitate to let us know how we can make you more efficient. > > Thanks for your patience. > > Robert Sturm > support.xilinx.com -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24959
My parents are going to lose their home if I cannot raise $1,000 by next week! I would appreciate if everyone could donate money to me by sending a donation through paypal to shocker1@nurb.com! If you could do this for me I would be so greatful! If you cant send me some money, atleast join up under shocker1@nurb.com at www.paypal.com and I'll get $5 for everyone who joins under me. Please help me save my family. If you do this I'll be eternally greatful and will return the favor once my family gets in better financial condition! P.S. If you send me any money through papyal, email me afterwards and when I get back on my feet I'll be glad to repay you what you lent me!Article: 24960
Jon Kirwan wrote to me: > Why should anyone sign a blanket NDA on first contact, where the NDA > takes nothing about the individual or their circumstances into > account?? You still haven't bothered to answer that question, in > spite on my bring it up several times. Frankly, I'm beginning to > believe you cannot. I think I have said that NDAs for the purpose of an interview are of little material relevance one way or the other such that it should not be a critical factor in interviewing with a company. I.e., if I understood that the NDA was for the purpose of the interview I would sign it. The issue is one of overall relevance of the NDA to the purposes of the interview. I might be irritated by, say, a person's tie or any number of things, but to raise these very small issues when there are likely more relevant things to discuss seems a waste of time or confusion of purpose. If we instead wish to speak of long term agreements, I think that would depend on the specific agreement and circumstance. I would not be able to say anything directly about those. And I would recommend the kinds of approaches you have been giving in these longer contract cases. Clearly when there is more at stake, a correspondingly greater consideration would be given. Now I have been giving a suggesting/question of which the response is as yet absent: why do we not post the company names with the behavior we have a problem with? Regards, Neil NelsonArticle: 24961
Gentlemen, I encountered a problem with Synopsys FPGA-Express 3.4.0.5124 and Xilinx Spartan-II. The synthesizer infers a SRL16E component, but does not create entity/ architecture declarations for it when exporting the netlist as VHDL. Everything worked fine with FPGA-Express 3.3, though. It looks like replacing the SRL16E.dsn file from lib/virtex folder with the "3.3" version restores the original functionality. Does anybody know what the purpose of those dsn files is? Do they affect synthesis? If it's something like an encoded VHDL template, what's the format of these files? Xilinx support suggested using the EDIF netlist and running it through ngdbuild and ngd2vhdl to create a VHDL model. But the model will then make use of simprims, which conflicts with my *functional* (not timing!) simulation. Any comments very much appreciated, thanks for your help, best regards Felix Bertram Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24962
--------------1E5FBE9BD0643BD71260FF83 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit I need to create a RAM in a XILINX-Virtex V300 with the XILINX Foundationtool. My problem is that my RAM has a width of 200 bits. Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a complex addressing. Futhermore i tryed to create a RAM with the XILINX Coregenerator but i got an error message Error L-44/C0 : #0 Error: D:/programs/xilinx/active/projects/grieda02/ram.vhd line -44 Library logical name XILINXCORELIB is not mapped to a host directory. (VSS-1071) (FPGA-dm-hdlc-unknown) Error L48/C0 : #0 Error: D:/programs/xilinx/active/projects/grieda02/ram.vhd line 48 No selected element named C_MEM_SP_BLOCK_V1_0 is defined for this prefix. (VSS-573) 2 error(s) 0 warning(s) found Does anyone has an idea, or does anyone has a vhdlcode ? THANKS Gerhard --------------1E5FBE9BD0643BD71260FF83 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> I need to create a RAM in a XILINX-Virtex V300 with the XILINX Foundationtool. <p>My problem is that my RAM has a <b>width of 200</b> bits. <p>Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a complex addressing. <p>Futhermore i tryed to create a RAM with the XILINX Coregenerator but i got an error message <p>Error L-44/C0 : #0 Error: D:/programs/xilinx/active/projects/grieda02/ram.vhd line -44 Library logical name XILINXCORELIB is not mapped to a host directory. (VSS-1071) (FPGA-dm-hdlc-unknown) <br> Error L48/C0 : #0 Error: D:/programs/xilinx/active/projects/grieda02/ram.vhd line 48 No selected element named C_MEM_SP_BLOCK_V1_0 is defined for this prefix. (VSS-573) <br> 2 error(s) 0 warning(s) found <p>Does anyone has an idea, or does anyone has a vhdlcode ? <p>THANKS Gerhard <br> </html> --------------1E5FBE9BD0643BD71260FF83--Article: 24963
Jimmy Roberts wrote:
> Is it always possible to encode the states so that the outputs are in the
> state vector?
> I do not think so...
Of course! If you have states with equal output bits, just add enough dummy
bits to distinguish them.
One advantage we saw comparing all those implementation methods is, that with
this approach you only have one comb. logic block. This normally results in
smaller (and therefore) faster logic.
Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Article: 24964Regarding functinoal simluations that fail, but timing simulations that pass; there may be another problem. (I ran into this a while back, and had to scratch my head for quite a while to figure it out.) Often, the libraries that come with a simulator for a given target part contain minimum timing delays. An example is the "Unisim" library that comes with the Aldec VHDL simulator, for Xilinx parts. In many cases, it assumes a "minimum" delay of 0.01 ns, or something. If you happen to instantiate some parts, but infer others, you can run into problems with your functional simulation. In my case, I inferred an IBUFG for my clock inputs, but just left the other inputs as regular inputs, letting the place-and-route software add the IBUF/OBUFs automatically. When I ran my simulation, my data would arrive inside the chip 0.01 ns before my clock signals. If I did the post-timing simulation, it was okay, since at that time, all of the inputs used IBUFs with non-zero delays. I solved this by recompiling a copy of the unisim library with all of the timing parameters set to zero, and then using *that* library when simulating. I hope this helps. -KentArticle: 24965
"S. Ramirez" wrote:
> It seems to me that "placing outputs in the state vector" would not be
> a problem logically if 1)one-hot encoding is not used, and 2) it will route.
> Timing should not be a problem, because by definition, the outputs are bits
> of the state vector, which are register outputs, i.e., minimal clock to out
> times.
True. A full-synchronous design, eases the job of the synthesis guy ;-)
> I myself am a proponent of the Moore FSM "outputs decoded in parallel
> registers" design technique. Not only does it separate the state vector
> from the output vector, but it also generates glitch free minimal clock to
> out timed signals.
You mean:
state(reg) = f(inputs, state), and also
outputs(reg) = f(inputs, state)?
Well, this is almost the same as 'Simple-Moore'. You just separate the regs.
Could result in a few more regs, but hey, we have lots of'em, right ;-) And
makes changes easier, yes. Which one to use is a 'matter of taste'. Both result
in a FSM, which is full synchronous and reacts within one cycle. Thats the point.
The problem with 'traditional' Mealy/Moore machines is, when you register their
outputs, you have a two-cycle latency: 1.cyc for the new state, 2.cyc for the
new outputs. Thats hard to handle...
Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Article: 24966
In article <39A375B6.1BC937B9@pacbell.net>
n_nelson@pacbell.net "Neil Nelson" writes:
> I think I have said that NDAs for the purpose of an interview are of
> little material relevance one way or the other such that it should not
> be a critical factor in interviewing with a company. I.e., if I
> understood that the NDA was for the purpose of the interview I would
> sign it.
Many legally binding documents have a much longer term associated than
you realise. My legal guides always tell me to read the document and
understand its implications before I sign it. If the terms do not seem
fair to both parties then do not sign the document until it has been
corrected to reflect such fairness.
We as logicians (I would hope all of us here are anyway) we can often
be better placed than legal counsel at spotting when the logic of an
agreement is broken. As I stated before, I live just 3 miles from one
establishment where the visitors register contains a (very fair) NDA.
I have no problem signing theirs when visiting them (I still read it
every time before signing though). I have, however, massively carved
other NDA's about when the emphasis was too much in favour of the other
party. So that is the test. Is the document fair to both parties.
--
********************************************************************
Paul E. Bennett ....................<email://peb@amleth.demon.co.uk>
Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/>
Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE......
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Article: 24967
Well, the max width for any given BlockRAM is 16 bits, so 200 bits requires
13 BlockRAMs. (well, 12 and a half; you'll have to waste 8 bits.)
Looking in the Databook shows that the XCV300 has 16 of them, so you should
be okay. I would suggest instantiating them manually in your VHDL code if
the core generator isn't working for you.
(I've never come to really like the Core generator Myself.)
I've stuck some VHDL code at the bottom of thie post. It's what I used to
create a generic-width RAM structure using BlockRAMs.
All standard disclaimers in effect.
Note: The unisim_nodel library that it refers to is the standard unisim
library, but with all the delays ripped out so that it will simulate
nicely.
Hope it helps.
-Kent
Gerhard Wrote:
>I need to create a RAM in a XILINX-Virtex V300 with the XILINX
>Foundationtool.
>
>My problem is that my RAM has a width of 200 bits.
>
>Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?)
>without a complex addressing.
>
>Futhermore i tryed to create a RAM with the XILINX Coregenerator but i
>got an error message
>
>
>THANKS Gerhard
>
>
--
-- 256 Deep Dual Port RAM based on Xilinx|Virtex BlockRAM
-- Generic WIDTH must be a multiple of 16
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
-- SYNOPSYS TRANSLATE_OFF
library UNISIM_NODEL;
use UNISIM_NODEL.all;
-- SYNOPSYS TRANSLATE_ON
entity BR_DPRAM is
generic (
WIDTH: integer := 16
);
port (
RST: in STD_LOGIC;
-- FIRST port
P0CLK: in STD_LOGIC;
P0ADDR: in STD_LOGIC_VECTOR(7 downto 0);
P0WE: in STD_LOGIC;
P0EN: in STD_LOGIC;
P0DATA_IN: in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
P0DATA_OUT: out STD_LOGIC_VECTOR(WIDTH-1 downto
0);
-- DUAL port
P1CLK: in STD_LOGIC;
P1ADDR: in STD_LOGIC_VECTOR(7 downto 0);
P1WE: in STD_LOGIC;
P1EN: in STD_LOGIC;
P1DATA_IN: in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
P1DATA_OUT: out STD_LOGIC_VECTOR(WIDTH-1 downto
0)
);
end BR_DPRAM;
architecture BR_DPRAM_ARCH of BR_DPRAM is
-- Component declaration of the "RAMB4_S16_S16(RAMB4_S16_S16_V)" unit
-- File name contains "RAMB4_S16_S16" entity: .\src\unisim_VITAL.vhd
component RAMB4_S16_S16
port(
DIA : in std_logic_vector(15 downto 0);
DIB : in std_logic_vector(15 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic;
RSTA : in std_ulogic;
RSTB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
ADDRA : in std_logic_vector(7 downto 0);
ADDRB : in std_logic_vector(7 downto 0);
DOA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector(15 downto 0));
end component;
-- SYNOPSYS TRANSLATE_OFF
for all: RAMB4_S16_S16 use entity
unisim_nodel.RAMB4_S16_S16(RAMB4_S16_S16_V);
-- SYNOPSYS TRANSLATE_ON
signal LOGIC_1: STD_LOGIC;
begin
-- SYNOPSYS TRANSLATE_OFF
assert((WIDTH mod 16) = 0 );
-- SYNOPSYS TRANSLATE_ON
BR_RAM_GEN:
for i in 0 to ((WIDTH / 16)-1) generate
BR_DPRAM_COMP: RAMB4_S16_S16
port map (
-- Port A
DIA => P0DATA_IN( ((i*16)+15) downto (i*16)),
ENA => P0EN,
WEA => P0WE,
RSTA => RST,
CLKA => P0CLK,
ADDRA => P0ADDR,
DOA => P0DATA_OUT( ((i*16)+15) downto (i*16)),
-- Port B
DIB => P1DATA_IN( ((i*16)+15) downto (i*16)),
ENB => P1EN,
WEB => P1WE,
RSTB => RST,
CLKB => P1CLK,
ADDRB => P1ADDR,
DOB => P1DATA_OUT( ((i*16)+15) downto (i*16))
);
end generate;
LOGIC_1 <= '1';
end BR_DPRAM_ARCH;
Article: 24968Something I forgot to mention: I'm assuming that the blocks are always enabled, and so on and so forth. but I'm sure that you can fix it up for your own application. -Kent korthner@hotmail.nospam.com (K. Orthner) wrote in <8F99B20A4korthnerhotmailcom@158.202.232.7>: >I've stuck some VHDL code at the bottom of thie post. It's what I used >to create a generic-width RAM structure using BlockRAMs. > >All standard disclaimers in effect. >Note: The unisim_nodel library that it refers to is the standard unisim >library, but with all the delays ripped out so that it will simulate >nicely. >Article: 24969
"rk" wrote : > Peter Alfke wrote: > > Yes, but the pain of unsoldering and re-soldering BGA parts is. > > Agreed. Again, I haven't thoroughly tried out the socketing solution for these. > From the construction of some types, it doesn't look like the signal quality will be > hurt too badly. Anyone have any good hands-on experience with these? They have > little pins that stick out of the bottom onto the pads on the PCB and if I remember > correctly, little fuzz buttons on top to contact the balls. Currently, I haven't > used any BGAs except for a small test. Mostly I use flatpacks, PGA's, PLCC's, and > PQFP's. > > I note that even flat packs (such as those used in military and aerospace > applications) take the care of an experienced technician and good equipment for > removal and replacement. After a number of cycles, pad damage starts to becomes an > issue, even with a good, careful technician. Some people like to use sockets to > avoid this problem that are surface mount on the bottom, PGA on top, for easy > removal and replacement; I personally don't prefer that approach. > I've had some problems using BGA sockets (TrueBGA series from Advanced Interconnections http://www.advintcorp.com) in conjunction with a Xilinx BGA560 package. The sockets were a bit too tightly dimensioned, i.e. the package would in some cases be resting on the corner guide posts, not he pogo pins themselves. My card manufacturer also had problems getting the solder process correct. These things requires *a lot* of heat. I've got better results by "hand-soldering" these with a hot-air gun (....yes, the paint stripper type!!!!). Not production quality process, but have worked OK for prototypes... The hot-air gun was originally my cheap flat pack desoldering tool (could remove a flat pack in 3-4 minutes including pre-heating), but has also proven useful for BGA soldering. Usually I run it at 250-270C during reflow, but also have some thermometers on the PCB to track the temperature profile. In retrospect, I would have preferred to avoid the sockets. But it was not too appealing to solder an expensive FPGA to an untested prototype card. (I didn't have access to a BGA reballing service at that time.......) Regards, - OlafArticle: 24970
On Tue, 22 Aug 2000 23:56:54 -0700, Neil Nelson <n_nelson@pacbell.net> wrote: >I think I have said that NDAs for the purpose of an interview are of >little material relevance one way or the other such that it should not >be a critical factor in interviewing with a company. If the NDAs are "of little material relevance" then why should they be a problem? Just remove them from the discussion and the issue simply goes away. If the company insists, then I assert that they are not "of little material relevence" -- at least, the company doesn't think so, since they are insisting. If they insist, then it's worth a good reading. The logical thing, if the NDA is a minor matter, is for the company to simply drop the issue. It's as simple as that. >I.e., if I >understood that the NDA was for the purpose of the interview I would >sign it. First, the people assuring you that it "is for the purpose of the interview" aren't attorneys, usually, and when they are they aren't representing you. If you accept the banal assurances of all and sundry as to your legal position, you aren't being wise. Now, if you are knowledgable about NDAs and can read them well enough, then read them. If acceptable, sign. If not, talk. But I wouldn't ever recommend taking the advice of the first interviewer or the lobby secretary or any other random person at the company as to your better understanding of the document. You must understand it yourself, from your own reading of it, and agree that you clearly know what they are getting at. If you rely on the assurances of others at the company insisting on the NDA, without really knowing why or what, you are acting very unwisely. Frankly, I don't think the average interviewee is competent enough to look over an NDA quickly enough to get started with the regular interviewing on schedule, unless time was planned in advance. I certainly would *not* recommend just walking in and then signing the NDA paperwork with little other than the wan smiles of your first interviewer who is telling you "not to worry about it." No NDA is that inert. >The issue is one of overall relevance of the NDA to the >purposes of the interview. Of course. No one would argue. But again, do you really, honestly, truly believe that a company should be disclosing proprietary information on their first contact with each and every applicant, such that they need to include verbage in their visitor log as well as asking all of them to sign an NDA upon meeting their 1st interviewer?? Give me a break, please! >I might be irritated by, say, a person's >tie or any number of things, but to raise these very small issues >when there are likely more relevant things to discuss seems a waste >of time or confusion of purpose. This is an irrelevant point, so far as I can tell. The fact that some things aren't important, bears not at all on whether or not an NDA is important. Whether it's a small issue to "be irritated" over a tie (or not) has absolutely nothing whatsoever to do with whether signing an NDA is a small issue. I've no idea why you said that. >If we instead wish to speak of long term agreements, I think that >would depend on the specific agreement and circumstance. I would >not be able to say anything directly about those. And I would >recommend the kinds of approaches you have been giving in these >longer contract cases. Clearly when there is more at stake, a >correspondingly greater consideration would be given. When there is more at stake, such as when both sides have decided they are seriously interested in each other, that is the time to be discussing these things and getting more into details that may need protecting. But then, both sides are ready at this point to invest a little more, too. A perfect time to discuss such things. >Now I have been giving a suggesting/question of which the response is >as yet absent: why do we not post the company names with the behavior >we have a problem with? You want to start? JonArticle: 24971
On Wed, 23 Aug 2000 01:25:53 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >I am not trying to keep this thread alive, but I have received another >per-interview packet from company C that I think just blows away the >concerns I had with the previous Company A. It just keeps getting better, eh? >Some of this may be because this interview is for a project management >position for which the company may feel it is more important to properly >evaluate a potential hire. But this is what they want me to bring to the >initial interview. > >A completed application, Sounds common enough. >A "consumer report" (otherwise known as a credit check) authorization, I've heard of this, never been asked of me, though. The point seems to be that the company is worried that you might be in deep debt and that, being so badly in need of cash you might accept illegal or legal bribes, presents, and other considerations in exchange for information you become privy to when working for the company. My opinion is that this kind of permission should only be granted once, if you do so at all, only as a condition of employment. It should NOT be given until they have made a firm commitment in writing to you and where the results are a condition in that written commitment. If you pass and you want to join, they should have to employ you at that point without further power on their side to refuse. Before that point, giving this authorization isn't wise. They may argue that they don't want to waste time thinking about you, if you are going to fail on the basis of bad debts. But I wouldn't care much for it. There's a lot of things I'd like to know about them, too, before getting hired that I doubt they'd like to tell me about up front. It's a two way street. Don't sign it until you have a firm offer. And even then, don't sign anything they can use more than 3 months down the road. Give it a clear and firm "sunset" that expires in the near future and cannot be revived by them without another agreement from you. >A Background questionnaire release form, Release form for exactly what? >Then they want me to leave behind a urine sample for drug testing. As a condition of employment, this has gotten to be quite common. I've been through that several times, although I keep reminding myself how much I absolutely love poppy seed strudel at about this time. I keep wondering if the rumors are true... But before you have completed negotiations??? No offer? No pee. Their only argument is, once again, they'd like to save time on you if you fail. Frankly, I don't care. They will just have to invest a bit in me and expect the best. >I can see the potential need for all of these things even if I don't >agree that they should be used for employment screening. But I strongly >disagree with the requirement to authorize them prior to an interview. Exactly. >And more importantly, I will not provide such an authorization to use >this information without an opportunity for me to dispute any erroneous >information contained in these reports. They probably don't even have a policy, other than not continuing discussions. The two times I asked, I was told that they do NOT provide another opportunity to be tested and that the results, false positive or otherwise, are invariably accepted as final. But never was this asked as part of the interview. >In fact I am not given any idea >of how the information will be evaluated. > >Finally the company retains >the right to perform further checks in the future (if hired) for >"deciding whether to continue your employment", and " when making other >employment related decisions directly affecting you". Odds are, you'll have a devil of a time scoping that out, too. Often, there is no clear policy in place and different managers at different times may make different choices, some you may not appreciate at all. If the company does have a solid, clear, and inflexible policy in place that has all the ear-marks of being sensibly written, I think that would argue well for the company. Chances are, there's nothing to hang your hat on, so you just take whatever they decide to do when they decide to do it. >I have heard of people who were fired from their jobs based on incorrect >credit information from fradulent use of their identities by other >people. Hopefully, this isn't too serious of a problem. I've heard those stories, too. Probably on some "news" program. <snip> JonArticle: 24972
This is exactly what I mean, Lars. Thanks for the clarification. -Simon Ramirez, Consultant Synchronous Design, Inc. > You mean: > state(reg) = f(inputs, state), and also > outputs(reg) = f(inputs, state)? > Well, this is almost the same as 'Simple-Moore'. You just separate the regs. > Could result in a few more regs, but hey, we have lots of'em, right ;-) And > makes changes easier, yes. Which one to use is a 'matter of taste'. Both result > in a FSM, which is full synchronous and reacts within one cycle. Thats the point. > The problem with 'traditional' Mealy/Moore machines is, when you register their > outputs, you have a two-cycle latency: 1.cyc for the new state, 2.cyc for the > new outputs. Thats hard to handle... > > LarsArticle: 24973
Olaf Birkeland wrote: > I've had some problems using BGA sockets (TrueBGA series from Advanced > Interconnections http://www.advintcorp.com) in conjunction with a Xilinx > BGA560 package. The sockets were a bit too tightly dimensioned, i.e. the > package would in some cases be resting on the corner guide posts, not he > pogo pins themselves. > > My card manufacturer also had problems getting the solder process correct. > These things requires *a lot* of heat. I've got better results by > "hand-soldering" these with a hot-air gun (....yes, the paint stripper > type!!!!). Not production quality process, but have worked OK for > prototypes... The hot-air gun was originally my cheap flat pack desoldering > tool (could remove a flat pack in 3-4 minutes including pre-heating), but > has also proven useful for BGA soldering. Usually I run it at 250-270C > during reflow, but also have some thermometers on the PCB to track the > temperature profile. > > In retrospect, I would have preferred to avoid the sockets. But it was not > too appealing to solder an expensive FPGA to an untested prototype card. (I > didn't have access to a BGA reballing service at that time.......) Thanks for the story. The socket that I have on the board didn't require any soldering at all; it had 4 screws, if I remember correctly, and was a press fit. I don't recall the manufacturer's name off hand but I can look it up. For the case of the BGA560, was the socket or the package out of spec? Or were the specs not fully consistent? Again, Thanks for the story, rkArticle: 24974
I sent mail on Xilinx XDOCS E-mail Document Server (mail: xdocs@xilinx.com), but received message "User unknown " :( . Is this service available ? Thank in advance. Best regards, Vlad.
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