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Olaf Birkeland wrote: > Guess Peter would recommend buying the smallest package > compatible device.... ;-) > No, I would recommend getting "dummies" ( mechanical samples) from the manufacturer. The problem is getting hold of somebody who can expedite this. I don't know the formal method, but your salesperson or FAE should. But the "smallest device" also works... Peter AlfkeArticle: 25026
No, you can address the column. To be precise: you can even adress the frame within the column. Peter Alfke, Xilinx Applications mok wrote: > In a Xilinx application note, it is said that Virtex series have a column > oriented partial reconfiguration feature. Does that mean that configuration > data is shifted column by column until it reaches the desired column. Does > that mean that if you wanna dynamically reconfigure a particular logic in > Column 'N', you have to keep all 'N-1' columns that come before column N, > empty???Article: 25027
Rick Collins wrote: > P.S.: There may be good arguments for not giving company names but some- > one needs to make them. What are you asking company names for? So that we have concrete examples to work with, or is your point that we should name names to alert others to the practices of the named employers? If I go to the police and say, ``There is a bad man who does bad things'', and describe generally what this bad man does without saying who the bad man is, what do we expect the police to do about this unnamed bad man? Perhaps the point in leaving the bad man unnamed is that we are making a general statement about men where anyone of them may be be bad such that we wish the police to be on the look-out for men as a class of individuals where anyone of them can be bad. This may seem like a clearly useless way to proceed, but we now have racial- profiling by many police departments (e.g., the Los Angeles police) where if you are a black man, you are likely to be stopped when you are driving on the street and questioned merely because you are black because, according to the justification for racial profiling, black men are significantly more likely to be involved in a crime than other races. (Perhaps if the police were not so busy looking at black men they may find more crime associated with other racial men, or perhaps if the police were not harassing black men, those men would not feel motivated to behave in a manner the police dislike. And so on.) And so a key point in asking for names is that we do not indict a large class of individuals, by merely rough association, with behaviors of a small number of that class. I.e., the general tone of the opposing argument, because it is not specific, is that we need to be suspicious of _all_ employers because at heart they are bad as can be seen in some unnamed cases. Well if a good number of them are not bad and we can apply effective corrective action against the specific bad behaviors of specific employers, I hope we will agree that we will have a better solution path. Besides, it seems to me that this is the fair thing to do. We do not want to suggest that someone is bad unless we have clear evidence that that is the case. This point of getting names appears to have several positive qualities of which the previous is only one. Regards, Neil NelsonArticle: 25028
Vikram Pasham wrote: > In the make file you can use > "set_pad_register" constraint to use IOB registers. The syntax for using this constraint is > > set_pad_register TRUE net_name > > You can do a "man" on this constraint in FE_SHELL to get all the details. I did some investigation yesterday on FE_SHELL commands and ran across the one you mention. What I didn't like about that is the number of net names that I would have to do that command on. The odds of missing one is huge. Instead, I created a FPGA Express constraint file and did the following command: import_constraint -file synth_constraints.exc The constraint file was essentially empty with the exception of setting the default value for IOFF's to TRUE. This seems to have worked. Now I can correctly compile my code, I can give some preliminary results. Under F2.1i+SP6, on a Spartan-II 50k gate -5 speed grade: 736 Slices (96%), 101 MHz, approx 10 minutes for PAR. Same as above, but on F3.1i+SP2: 699 Slices (91%), 102.5 MHz, approx 25 minutes for PAR. So I can say, with certainty, that run times have more than doubled for _THIS_ design, but with marginal improvements in speed and size. Ray A.: No floorplanning. Just VHDL with a basic *.UCF. David Kessner davidk@free-ip.comArticle: 25029
Hi all Does anyone have any idea why I get this error message: "ERROR:basmm:227 - LUT3 symbol "int/I_reg_clr" (output signal=int/N31) has an equation that uses an input pin connected to a trimmed signal. Make sure that all the pins used in the equation for this LUT have signals that are not trimmed (see trim report for details on which signals were trimmed)." when the trim report says: "The signal "int/N31" is unused and has been removed." ? -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 25030
Hi there ! I just tried to get Spartan II chips (xc2s100 and 200). The guys from Insight told me that there is no xc2s100 (in sight) and for delivery of the xc2s200 I'll have to wait about 12 weeks. Now whats the problem ??? Spartan 2 was announced a long time ago... Whats about the xc2s100 will it ever be produced or is he already cancelled. When will Spartan II be available ???? RupertArticle: 25031
Rupert,
I hope that you just tried to get Spartan II chips before you started
the design instead of afterward. I don't know about you or the other guys
in this newsgroup, but I NEVER start a design unless I ping the
distees/manufacturers and verify that they can in fact deliver silicon. If
they can't, then I consider it unobtainium and I simply don't do the design.
So far this strategy hasn't cost me anything on the leading edge of
technology. It applies to all silicon vendors, not just the famous Xilinx
that dominates this newsgroup (and the market pie!).
I have been bitten by other related factors, though. I started a
XC4036XL design because I could get silicon and the devices implemented dual
port RAMs that I needed for small FIFOs and DPRAMs. What I didn't know at
the time was that the software that generated the dual port RAMs wasn't done
yet, and I couldn't generate them. Xilinx jumped on the speedwagon to fix
it, but nonetheless it caused my schedule to slip. It was either 1) use
Xilinx XC4KXL, 2) talk Altera into changing their 10K just for me, 3) go to
a bigger board or 4) cancel the project.
So checking to make sure that the software implements everything you
want should be added to the list.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Rupert Glaser" <Rupert.glaser.@infineon.com> wrote in message
news:8o3fer$hkg$1@mosquito.HL.Siemens.DE...
> Hi there !
> I just tried to get Spartan II chips (xc2s100 and 200). The guys from
> Insight told me that there is no xc2s100 (in sight) and for delivery of
the
> xc2s200 I'll have to wait about 12 weeks.
> Now whats the problem ???
> Spartan 2 was announced a long time ago...
> Whats about the xc2s100 will it ever be produced or is he already
cancelled.
> When will Spartan II be available ????
> Rupert
>
>
Article: 25032Origional post follows: My Virtex 400 design that placed and routed in 2 - 2.5 hours with 2.1i (on a 350 mhz PC) is now taking 4 - 5 hours with 3.1i (with service pack 2 installed). The routing delays and timing look no better or no worst than 2.1i. Is anyone else seeing these longer run times? Here's whats going on: The design was constrained too tightly in the .UCF file so timing was never met. (I do a lot of my designs this way, figuring PPR will give me its best shot and then I use timing analyzer to exclude a few bogus paths and a few non critical nets). Apparently 3.1i will spend A LOT more time trying to squeek out the last ns than 2.1i did. Once I excluded my non-critical nets in the .UCF file the design met timing and ran in 1/2 hour. I'm happy. Thanks to all who helped. DanArticle: 25033
Now that you describe the problem that way, Yes I've noticed that too. I had been doing comparisons with designs that were already placed and that I knew met the constrained timing. I have seen where 3.1 takes quite a bit longer trying to meet timing before it throws in the towel. Dan Kuechle wrote: > > Origional post follows: > > My Virtex 400 design that placed and routed in 2 - 2.5 hours with 2.1i (on > a 350 mhz PC) is now taking 4 - 5 hours with 3.1i (with service pack 2 > installed). The routing delays and timing look no better or no worst than > 2.1i. > Is anyone else seeing these longer run times? > > Here's whats going on: > The design was constrained too tightly in the .UCF file so timing was never > met. > (I do a lot of my designs this way, figuring PPR will give me its best shot > and then I > use timing analyzer to exclude a few bogus paths and a few non critical > nets). > Apparently 3.1i will spend A LOT more time trying to squeek out the last ns > than 2.1i did. Once I excluded my non-critical nets in the .UCF file the > design > met timing and ran in 1/2 hour. I'm happy. Thanks to all who helped. > > Dan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25034
Hi. I would like to know what is the largest fpga in the industry in terms of internal RAM. (and I mean RAM that it's usage will not come on the cost of logic cells use). ThankX, Yoram. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25035
Neil Nelson wrote: > > Rick Collins wrote: > > > P.S.: There may be good arguments for not giving company names but some- > > one needs to make them. > > What are you asking company names for? So that we have concrete examples > to work with, or is your point that we should name names to alert others > to the practices of the named employers? > > If I go to the police and say, ``There is a bad man who does bad things'', and > describe generally what this bad man does without saying who the bad man is, > what do we expect the police to do about this unnamed bad man? Perhaps the > point in leaving the bad man unnamed is that we are making a general statement > about men where anyone of them may be be bad such that we wish the police to > be on the look-out for men as a class of individuals where anyone of them can > be bad. > > This may seem like a clearly useless way to proceed, but we now have racial- > profiling by many police departments (e.g., the Los Angeles police) where if > you are a black man, you are likely to be stopped when you are driving on the > street and questioned merely because you are black because, according to the > justification for racial profiling, black men are significantly more likely to be > > involved in a crime than other races. (Perhaps if the police were not so busy > looking at black men they may find more crime associated with other racial men, > or perhaps if the police were not harassing black men, those men would not > feel motivated to behave in a manner the police dislike. And so on.) > > And so a key point in asking for names is that we do not indict a large class of > individuals, by merely rough association, with behaviors of a small number of > that class. I.e., the general tone of the opposing argument, because it is not > specific, is that we need to be suspicious of _all_ employers because at heart > they are bad as can be seen in some unnamed cases. Well if a good number > of them are not bad and we can apply effective corrective action against > the specific bad behaviors of specific employers, I hope we will agree that > we will have a better solution path. Besides, it seems to me that this is the > fair > thing to do. We do not want to suggest that someone is bad unless we have > clear evidence that that is the case. > > This point of getting names appears to have several positive qualities of > which the previous is only one. > > Regards, > > Neil Nelson Your answer is completely unclear. Let me make it simpler. You want company names so that A) We will have concrete examples to discuss with all the pertinate details. or B) You wish to alert others to the practices of these particular companies. Your answers seem to me to be much more confusing that the original topic of discussion. :) -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25036
Simon is of course right, in general. But Spartan-II is a special case: It is derived from "good old Virtex", which has been around for well over a year. From a software point ov view, there is no big difference. The speedsfile numbers differ, there is no temp-measuring diode in Spartan-II, and, perhaps most importantly for your projects, the packages differ. And Spartan-II extends the Virtex family downwards to '30 and '15, devices that will never exist in Virtex. "Besides that..." there is no difference. So you can definitely start the software portion of your design without any worry. I have tried to get a realistic availability answer out of Spartan marketing. Let's see. Peter Alfke, Xilinx Applications ============================ "S. Ramirez" wrote: > Rupert, > I hope that you just tried to get Spartan II chips before you started > the design instead of afterward. I don't know about you or the other guys > in this newsgroup, but I NEVER start a design unless I ping the > distees/manufacturers and verify that they can in fact deliver silicon. If > they can't, then I consider it unobtainium and I simply don't do the design. > So far this strategy hasn't cost me anything on the leading edge of > technology. It applies to all silicon vendors, not just the famous Xilinx > that dominates this newsgroup (and the market pie!). > I have been bitten by other related factors, though. I started a > XC4036XL design because I could get silicon and the devices implemented dual > port RAMs that I needed for small FIFOs and DPRAMs. What I didn't know at > the time was that the software that generated the dual port RAMs wasn't done > yet, and I couldn't generate them. Xilinx jumped on the speedwagon to fix > it, but nonetheless it caused my schedule to slip. It was either 1) use > Xilinx XC4KXL, 2) talk Altera into changing their 10K just for me, 3) go to > a bigger board or 4) cancel the project. > So checking to make sure that the software implements everything you > want should be added to the list. > -Simon Ramirez, Consultant > Synchronous Design, Inc. > > "Rupert Glaser" <Rupert.glaser.@infineon.com> wrote in message > news:8o3fer$hkg$1@mosquito.HL.Siemens.DE... > > Hi there ! > > I just tried to get Spartan II chips (xc2s100 and 200). The guys from > > Insight told me that there is no xc2s100 (in sight) and for delivery of > the > > xc2s200 I'll have to wait about 12 weeks. > > Now whats the problem ??? > > Spartan 2 was announced a long time ago... > > Whats about the xc2s100 will it ever be produced or is he already > cancelled. > > When will Spartan II be available ???? > > Rupert > > > >Article: 25037
--------------DFCF1D587E22119B14023A45 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Paul Tiseo wrote: > In article <39A48C40.2345C315@pacbell.net>, n_nelson@pacbell.net says... > > Paul Tiseo wrote: > > > Have you had the experience--not envisaged (imagined), as we may > > envisage quite at odds with the facts--of some unethical behavior by an > > employer in or closely related to the issues we are discussing? At the > > Yes, but I am not at liberty to discuss them in the excruciating > details you seem to require. :) > > > moment we have various vague claims that they happen, but factual details > > (as in the name of the company involved, Jon) are conveniently missing. I > > think if we want to have an accurate statistical study, that we take care to > > have accurate, credible data with which to make a statistical assertion. > > Sure, but my assertion was that you are *appear* to be minimizing > the actual *and* potential harm done by companies that do just what many > are discussing in this thread. Comparisons to meteorites do not hide the > fact that, unless there is an equal and opposing force to corporate mass > paranoia and subsequent measures, that we could potentially suffer much > more than some of us already do. It really was just my impression of > your tone that I was relating, not a statement on the accuracy of > inaccuracy of your statements. I do not see a company name as an excruciating detail. Maybe some of the excruciating aspects could be removed by using an anonymous remailer. Here is an interesting quote from the Los Angeles Times article mentioned yesterday, bottom, p. A16. But Jay Chapman, vice president and personnel director of the 750-store company, said workers are free to look for jobs elsewhere if they do not want to sign agreements. This sounds very close to the current suggested course of action for the, say, anti-employer faction. I.e., we are doing what the opposition would prefer us to do. And for some curiously unsaid and widespread reason, we are not willing to communicate sufficient details to apply coordinated pressure to problems areas. E.g., in the Gulf War the initial objective of the Allied forces was to destroy command and control and their means so that Saddam could not respond in a coordinated fashion to any Allied concentrated attacks. One of Napoleon's favorite strategies when opposed by a superior force was to divide that force into portions that were each smaller than his total force and then destroy each opposing portion in turn. This is a strategy used by labor unions of American automobile manufacturers who will concentrate their bargaining efforts on a single likely weak company and perhaps strike against it, and when that company yields take the resulting contract to the next company who not only faces a concentrated force but has a precedent from the other losing company to deal with. If you want an equal opposing force, you will need to do better than having a strategy that is every man for himself and a prohibi- tion against the communications required to obtain coordinated and concentrated action. It is as if your strategy was designed by the opposition. But the ultimate mass to deal with are all the people whoever they may be and if they see something they, in general, do not like in, say, the the press, pressures against it will overcome any opposi- tion. This is the basis of democracy. We now have our own press: the newsgroups. You need to focus your argument to the point of a sharp knife (what specific company, what specific action) and let the public know. Saying vaguely some company and some action dissipates the energy of your purpose. An anonymous remailer should allow you, if used carefully, to get the necessary information across to obtain a concentrated result without letting the opposition destroy you in detail (Napoleon). It must be objective, to the point, and accurate. Not giving one's name requires a higher standard of credibility for the remaining argument components. Regards, Neil Nelson --------------DFCF1D587E22119B14023A45 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Paul Tiseo wrote: <blockquote TYPE=CITE>In article <39A48C40.2345C315@pacbell.net>, n_nelson@pacbell.net says... <br>> Paul Tiseo wrote: <p>> Have you had the experience--not envisaged (imagined), as we may <br>> envisage quite at odds with the facts--of some unethical behavior by an <br>> employer in or closely related to the issues we are discussing? At the <p> Yes, but I am not at liberty to discuss them in the excruciating <br>details you seem to require. :) <p>> moment we have various vague claims that they happen, but factual details <br>> (as in the name of the company involved, Jon) are conveniently missing. I <br>> think if we want to have an accurate statistical study, that we take care to <br>> have accurate, credible data with which to make a statistical assertion. <p> Sure, but my assertion was that you are *appear* to be minimizing <br>the actual *and* potential harm done by companies that do just what many <br>are discussing in this thread. Comparisons to meteorites do not hide the <br>fact that, unless there is an equal and opposing force to corporate mass <br>paranoia and subsequent measures, that we could potentially suffer much <br>more than some of us already do. It really was just my impression of <br>your tone that I was relating, not a statement on the accuracy of <br>inaccuracy of your statements.</blockquote> <tt>I do not see a company name as an excruciating detail. Maybe some</tt> <br><tt>of the excruciating aspects could be removed by using an anonymous</tt> <br><tt>remailer.</tt><tt></tt> <p><tt>Here is an interesting quote from the Los Angeles Times article</tt> <br><tt>mentioned yesterday, bottom, p. A16.</tt><tt></tt> <p><tt> But Jay Chapman, vice president and personnel director of</tt> <br><tt> the 750-store company, said workers are free to look for</tt> <br><tt> jobs elsewhere if they do not want to sign agreements.</tt><tt></tt> <p><tt>This sounds very close to the current suggested course of action for</tt> <br><tt>the, say, anti-employer faction. I.e., we are doing what the</tt> <br><tt>opposition would prefer us to do. And for some curiously unsaid</tt> <br><tt>and widespread reason, we are not willing to communicate sufficient</tt> <br><tt>details to apply coordinated pressure to problems areas. E.g., in</tt> <br><tt>the Gulf War the initial objective of the Allied forces was to</tt> <br><tt>destroy command and control and their means so that Saddam could not</tt> <br><tt>respond in a coordinated fashion to any Allied concentrated attacks.</tt><tt></tt> <p><tt>One of Napoleon's favorite strategies when opposed by a superior</tt> <br><tt>force was to divide that force into portions that were each smaller</tt> <br><tt>than his total force and then destroy each opposing portion in turn.</tt> <br><tt>This is a strategy used by labor unions of American automobile</tt> <br><tt>manufacturers who will concentrate their bargaining efforts on a</tt> <br><tt>single likely weak company and perhaps strike against it, and when</tt> <br><tt>that company yields take the resulting contract to the next company</tt> <br><tt>who not only faces a concentrated force but has a precedent from the</tt> <br><tt>other losing company to deal with.</tt><tt></tt> <p><tt>If you want an equal opposing force, you will need to do better</tt> <br><tt>than having a strategy that is every man for himself and a prohibi-</tt> <br><tt>tion against the communications required to obtain coordinated and</tt> <br><tt>concentrated action. It is as if your strategy was designed by the</tt> <br><tt>opposition.</tt><tt></tt> <p><tt>But the ultimate mass to deal with are all the people whoever they</tt> <br><tt>may be and if they see something they, in general, do not like in,</tt> <br><tt>say, the the press, pressures against it will overcome any opposi-</tt> <br><tt>tion. This is the basis of democracy.</tt><tt></tt> <p><tt>We now have our own press: the newsgroups. You need to focus your</tt> <br><tt>argument to the point of a sharp knife (what specific company,</tt> <br><tt>what specific action) and let the public know. Saying vaguely some</tt> <br><tt>company and some action dissipates the energy of your purpose.</tt><tt></tt> <p><tt>An anonymous remailer should allow you, if used carefully, to get</tt> <br><tt>the necessary information across to obtain a concentrated result</tt> <br><tt>without letting the opposition destroy you in detail (Napoleon).</tt> <br><tt>It must be objective, to the point, and accurate. Not giving one's</tt> <br><tt>name requires a higher standard of credibility for the remaining</tt> <br><tt>argument components.</tt><tt></tt> <p><tt>Regards,</tt><tt></tt> <p><tt>Neil Nelson</tt></html> --------------DFCF1D587E22119B14023A45--Article: 25038
That should be reasonably easy to compare, at least relative to other marketing parameters. I think right now that honor goes to the Altera APEX EP20K1500E. That metric, however isn't really all that useful. If you just want memory without regard to the logic capabilities, then why not just use memory. Xilinx devices have the ability to use the CLBs as memory as well as the block RAMs. That, and the cell structure can make a xilinx design occupy less than half the LUTs of an equivalent designin ALtera. Given equal number of LUTs, that could be an awful lot of distributed RAM cells which could tip the balance the other way. In evaluating a part, you really need to look at the whole picture, including the tools and how they fit into your purchasing plans. yorams70@my-deja.com wrote: > > Hi. > I would like to know what is the largest fpga in the industry in > terms of internal RAM. (and I mean RAM that it's usage will not > come on the cost of logic cells use). > > ThankX, > Yoram. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25039
Coregen will give you what you need to make this very very easy. -Joe In article <8nj9vp$9d$1@qnsgh006.europe.nortel.com>, gyles@nortelnetworks.com (Gyles Harvey) wrote: > In article <399D0F1A.AC6339A0@emw.ericsson.se>, > Thomas Karlsson <thomas.karlsson@emw.ericsson.se> wrote: > >Some quotes from Synplify user guide: > > > >1. Create an interface for the macro with no contents(you could have > <snip> > > > > My Example: > > module RAMB4_S16(DO, ADDR, DI, EN, CLK, WE, RST) /* synthesis > >black_box */; > > output [15:0] DO; > > input [7:0] ADDR; > > input [15:0] DI; > > input EN; > > input CLK; > > input WE; > > input RST; > > endmodule > > This module, and many others, are in virtex.v (virtexe.v), included with > synplify. Maybe this is new? > > You may also wish to read the synplify help page on _inferring_ RAMS. This only > works if the ram is single port, or dual port with common clock. It does make > resizing the ram easy. > > Gyles. > > -- > gyles@nortelnetworks.com > All opinions expressed are my own, not those of Nortel Networks. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25040
--------------868DF314B5295A3B108C589E Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Rick Collins wrote: > Your answer is completely unclear. > > Let me make it simpler. You want company names so that > > A) We will have concrete examples to discuss with all the pertinate > details. > > or > > B) You wish to alert others to the practices of these particular > companies. > > Your answers seem to me to be much more confusing that the original > topic of discussion. You ask me why I wanted names. I can go with (A) and (B) and the several other reasons I have been giving. But however confusing I am, it is not that confusing that no one has given an argument as to why they are not giving the names of the companies they say are not behaving appropriately. I.e., you may wish me to explain my reason for asking and say that it is confusing, but still no names have been given and no reason has been given for not giving names. The original topic was one that dealt with not disclosing. Why are we not disclosing names? Which it would seem we must know if we say there is in fact a company behaving poorly? Regards, Neil Nelson --------------868DF314B5295A3B108C589E Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Rick Collins wrote: <blockquote TYPE=CITE>Your answer is completely unclear. <p>Let me make it simpler. You want company names so that <p>A) We will have concrete examples to discuss with all the pertinate <br>details. <p>or <p>B) You wish to alert others to the practices of these particular <br>companies. <p>Your answers seem to me to be much more confusing that the original <br>topic of discussion.</blockquote> <tt>You ask me why I wanted names. I can go with (A) and (B) and the</tt> <br><tt>several other reasons I have been giving. But however confusing</tt> <br><tt>I am, it is not that confusing that no one has given an argument</tt> <br><tt>as to why they are not giving the names of the companies they</tt> <br><tt>say are not behaving appropriately. I.e., you may wish me to</tt> <br><tt>explain my reason for asking and say that it is confusing, but</tt> <br><tt>still no names have been given and no reason has been given for</tt> <br><tt>not giving names. The original topic was one that dealt with not</tt> <br><tt>disclosing. Why are we not disclosing names? Which it would seem</tt> <br><tt>we must know if we say there is in fact a company behaving poorly?</tt><tt></tt> <p><tt>Regards,</tt><tt></tt> <p><tt>Neil Nelson</tt> <br><tt></tt> </html> --------------868DF314B5295A3B108C589E--Article: 25041
Can someone tell me how I would proram a xilinx fpga with an 8052 using a eeprom. Xilinx has a app note but it doesn't tell you a whole lot. I was just wondering how I would use that setup with a serial port? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25042
I experienced a similar problem and managed to solve it after some fiddling. Check the following: 1) The two chipscope cores must be at the top level of the design 2) The clock for the ILA core is working (Not sure what your source is for it). One way to trouble shoot this is to use the Help menu and choose "About ILA Core". If everything is working then it will provide some information, otherwise it will give you the comm error. I also found support to be pretty good but you may have to purchase the tool for that. Andy Daixun <daixun.zheng@ee.surrey.ac.uk> wrote in message news:ee6dadf.-1@WebX.sUN8CHnE... > I wonder if anyone can help me solve my problem. > > I am trying the Demo program of Chipscope. But I got the problem when I want to set up Trigger. The error message is "ILA Unit communication Failed" > > The following is the situation: > > Software: Chipscope Hardware: Multilinx Prototyping board Connection Mode: Slave serial mode Target Device: Virtex-800hq240 > > The steps: > > 1. Regenerate the MCS file of V800hq240 for Slave-serial mode. > 2. Connect the Multilinx cable with the board through Slave-serial mode. > 3. Run chipscope, create the project > 4. open the serial communication port,Baudrate is auto. > 5. Setting up Boundary scan chain to 'One target device, alone in the chain' > 6. Configuring device to slave-serial mode and download MCS file to V800 FPGA. The DONE status appears at the lower right corner of the window. > > 7.(At this step, I got error message) Then I set up trigger, select data>trigger setup. The message 'Init cable for JTAG' is displayed. At last, I got 'ILA Unit communication Failed' > > Thanks! > > DaixunArticle: 25043
Let me describe the biggest FPGA that Xilinx is shipping now ( and I mean shipping today to paying customers ): The Virtex XCV3200E has a 104 x 156 array of CLBs. That makes it 16,224 CLBs, each with four Logic Cells. That means there are 64,896 Logic Cells, each consisting of a 4-input look-up table plus a flip-flop. You can use each LUT as either logic (ROM), as 16-bit RAM, or as 16-bit shift register. ( Altera can use the LUT only as logic (ROM). Independent of these CLBs, there are 208 BlockRAMs, each with 4096 bits and two completely independent access mechanisms ( true dual-ported). That makes it 851,968 bits of RAM, not counting the RAMs in the LUTs. I am sure that this is bigger than Altera's biggest device. This is today's situation. next year, there will be significantly larger devices from Xilinx. But the question was: What's shipping today? Answer: the XCV3200E. The numbers above are honest engineering numbers, no smoke or mirrors. All the other goodies, like multiplexers, carry logic, digital delay-locked loops, and versatile I/Os are not counted, they are "free". Peter Alfke, Xilinx Applications =============================== Ray Andraka wrote: > That should be reasonably easy to compare, at least relative to other marketing > parameters. I think right now that honor goes to the Altera APEX EP20K1500E. > That metric, however isn't really all that useful. If you just want memory > without regard to the logic capabilities, then why not just use memory. Xilinx > devices have the ability to use the CLBs as memory as well as the block RAMs. > That, and the cell structure can make a xilinx design occupy less than half the > LUTs of an equivalent designin ALtera. Given equal number of LUTs, that could > be an awful lot of distributed RAM cells which could tip the balance the other > way. In evaluating a part, you really need to look at the whole picture, > including the tools and how they fit into your purchasing plans. > > yorams70@my-deja.com wrote: > > > > Hi. > > I would like to know what is the largest fpga in the industry in > > terms of internal RAM. (and I mean RAM that it's usage will not > > come on the cost of logic cells use). > > > > ThankX, > > Yoram. > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.comArticle: 25044
I think the real problem you're gonna face is processing those 200 bits... Routing those 200 lines from the block Rams to the CLBs for processing is going to be no mean feat. What are you doing that you need all 200 bits at once? That said, I can't really think of a way around the problem unless you can do with accessing the data in chunks (in which case you don't really need a 200 bit wide RAM in the first place). Just something to consider... Steve > Gerhard Griessnig wrote: > > > > I need to create a RAM in a XILINX-Virtex V300 with the XILINX Foundationtool. > > > > My problem is that my RAM has a width of 200 bits. > > > > Can i use the ONBOARD-RAM (only in Virtex-Series? max width is 16?) without a > > complex addressing.Article: 25045
I was too hasty on this one. The XCV3200E has nearly twice the ram of the EP20K1500E not counting the CLB RAM, and as I've previously stated has a more capable LUT structure for DSP apps at least. Just goes to show you, you really need to look at the data sheets to figure out which is the biggest advertised. Then you need to contact the disties to figure out if it is a real chip yet. Ray Andraka wrote: > > That should be reasonably easy to compare, at least relative to other marketing > parameters. I think right now that honor goes to the Altera APEX EP20K1500E. > That metric, however isn't really all that useful. If you just want memory > without regard to the logic capabilities, then why not just use memory. Xilinx > devices have the ability to use the CLBs as memory as well as the block RAMs. > That, and the cell structure can make a xilinx design occupy less than half the > LUTs of an equivalent designin ALtera. Given equal number of LUTs, that could > be an awful lot of distributed RAM cells which could tip the balance the other > way. In evaluating a part, you really need to look at the whole picture, > including the tools and how they fit into your purchasing plans. > > yorams70@my-deja.com wrote: > > > > Hi. > > I would like to know what is the largest fpga in the industry in > > terms of internal RAM. (and I mean RAM that it's usage will not > > come on the cost of logic cells use). > > > > ThankX, > > Yoram. > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25046
In article <39A58F57.1CCFF7D5@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > I was too hasty on this one. The XCV3200E has nearly twice the ram > of the EP20K1500E not counting the CLB RAM, and as I've previously > stated has a more capable LUT structure for DSP apps at least. Just > goes to show you, you really need to look at the data sheets to > figure out which is the biggest advertised. Then you need to > contact the disties to figure out if it is a real chip yet. I don't know about the XCV3200E, but the XCV2000E is out, we have a defective-die delidded as a cute little demo in our office window. And that sucker is HUGE, at least 19mm on a side! -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 25047
In article <39A58E60.5054A94B@xilinx.com>, Peter Alfke <peter.alfke@xilinx.com> wrote: > The Virtex XCV3200E has a 104 x 156 array of CLBs. That makes it > 16,224 CLBs, each with four Logic Cells. That means there are 64,896 > Logic Cells, each consisting of a 4-input look-up table plus a > flip-flop. You can use each LUT as either logic (ROM), as 16-bit > RAM, or as 16-bit shift register. ( Altera can use the LUT only as > logic (ROM). Well, we have a defective, delidded XCV2000E in our office window, and that thing is a monster. Just how big is the die on the 3200E? -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 25048
Yoram,
This is a side note to your question. Earlier, someone claimed that
this newsgroup is dominated by Xilinx. Since it is an FPGA newsgroup, I
would like to see Altera, Actel, Lucent, Quicklogic, Atmel, Lattice and
others post what they have to answer Yoram's question. There is nothing
stopping these vendors from posting various messages explaining what they
have or answering questions and offering clarification. And there is
nothing stopping engineers from posting problems and questions related to
these other vendors.
Please post and add more information wealth to this newsgroup.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
<yorams70@my-deja.com> wrote in message news:8o3ld7$185$1@nnrp1.deja.com...
> Hi.
> I would like to know what is the largest fpga in the industry in
> terms of internal RAM. (and I mean RAM that it's usage will not
> come on the cost of logic cells use).
>
> ThankX,
> Yoram.
Article: 25049It's around 25 mm square, or an inch for you non-metric folks. Bragging about large chip size always gives me a creepy feeling. Here we have a bunch of engineers and layout designers who sacrificed their lunch, their sleep, and their family life to squeeze the design as small as they possibly could do it. And then somebody brags about how BIG the chip is. :-( I wish it were smaller, then it would be both faster and cheaper. But this size was the smallest we could make it, of course only until we shrink it next year.... But, hats off to the fab ( in Taiwan ) who can produce such monster chips without any defect, and to the guys who can stuff it into a package and bond more than a thousand wires.. Isn't it almost a miracle ? Peter Alfke ============================================== "Nicholas C. Weaver" wrote: > In article <39A58E60.5054A94B@xilinx.com>, > Peter Alfke <peter.alfke@xilinx.com> wrote: > > The Virtex XCV3200E has a 104 x 156 array of CLBs. That makes it > > 16,224 CLBs, each with four Logic Cells. That means there are 64,896 > > Logic Cells, each consisting of a 4-input look-up table plus a > > flip-flop. You can use each LUT as either logic (ROM), as 16-bit > > RAM, or as 16-bit shift register. ( Altera can use the LUT only as > > logic (ROM). > > Well, we have a defective, delidded XCV2000E in our office > window, and that thing is a monster. Just how big is the die on the > 3200E? > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu
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