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Many years ago I was told that the DEC PDP-11 had some patented instructions (subroutine call through the top element of the stack) and that this gave them control over any efforts to clone their machines.Article: 25601
The decoupling is four .1uF caps. One at each corner of a QP240. I plan to make a new PCB with a .1uF at each power pin. When the device is drawing minimum power, shouldn't four decoupling caps be enough ? DanArticle: 25602
This is a multi-part message in MIME format. --------------0981A683501ED964A766CDF1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit (Hawker, have you seen the thread on 'Clock skew in XILINX CPLD' where we've been talking about some XC9500 issues? Maybe your note here would have been more appropriate there, instead of attached to a thread on XCV50 problem) Nevertheless, I'm intensely interested in this issue too, as we have XC9500 parts going into mission critical H/W. When you say 'noise', this doesn't say much. Is this a decoded clock that is being generated, and you get decoding glitches depending on whether some cover logic is being reduced? If this is the case, not a worry, experienced designers should know to look out for and how to handle that, and you've just had your experience. Much more worrisome is if your output clock is simply a copy of an input clock pin, and noise is induced depending on routing. Hawker, which was the case for you? Usual comments on ground and VCC planes, de-coupling, termination of high speed edges, everything else Howard Johnson covers in his very good book. Sorry, here's the rant... I know that 9500 followed much different development path than Xilinx ram based FPGAs. But the S/W should make further attempts at convergence. Specifically, with the 4000's and Virtex, you get the wonderful FPGA 'viewer' (uhh, editor), that lets you see whatever damage the S/W hath wrought. You can see the routing, you can check the logic. When a circuit doesn't work, you can go right into the part to bring out a test point by hand if necessary (and the XLA embedded logic analyser is NOT going to change the desirability of this feature!, Xilinx, never give up on that editor, it is one of the better tools you have, I forgive the way it _used_ to crash!). With the 9500, you have no tool that compares. What is it with CPLDs that vendors don't want to release any kind of routing viewer? The Lattice parts had this problem, I was told they didn't want to release routing details for fear of giving up valuble architectural secrets. The first time I had a design with those parts that exhibited a failure mode due to moving things around, I decided to drop them. Also, what good is it if you can't see inside the part enough to know whether you even have a reasonable shot at routing it before you start? Do the design first and then find out there's no way it will rout? Give me a break!! I haven't used the Lattice stuff in at least 4 years, just because they were so secretive about what's inside. Don't even know if they're still around. It is getting close to that point with the XC9500 series. I have no idea what the detailed routing looks like, and why there are failures showing up that come or go depending on position/existance of totally unrelated circuits in the part. It is getting close to the point where I may recommend company wide boycot of these devices. CPLD vendors, open up your routing details. Afraid to give away trade secrets? Surely you're big enough to invest in a patent for your precious architectures if they are that valuable. The real value is in giving engineers tools and parts they can use without head scratching. My scalp is getting thin. Hawker wrote: > > Ya know I'm having that problem with of all things a > XC95108. You can even see the noise on the clock output pin. > I changed the synth to not "demorgan" or whatever it does to reduce space > and problem went away.. course design needs 33% more space! > These tool sets are annoying me to no end! > If PADS PCB (the other EDA software I use regularly) had > as many issues it would never have made it to where it has... > Thank god Xilinx does not make chips like they make there toolsets! > > Hawker > > Dan wrote: > > > > I have a XCV50 design with internal noise. CLBs changing state when they > > shouldn't. > > > > Could this be caused by noise from unused IOBs. Do the unused IOBs need to > > be configured in a certain way ? If so how ? > > --------------0981A683501ED964A766CDF1 Content-Type: text/x-vcard; charset=us-ascii; name="jsmith.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for John L. Smith Content-Disposition: attachment; filename="jsmith.vcf" begin:vcard n:Smith;John L. tel;work:858-320-4102 x-mozilla-html:FALSE url:http://www.visicom.com org:Visicom;Imaging Products adr:;;10052 Mesa Ridge Court;San Diego;CA;92121;USA version:2.1 email;internet:jsmith@visicom.com title:Principal Engineer x-mozilla-cpt:;30864 fn:John L. Smith end:vcard --------------0981A683501ED964A766CDF1--Article: 25603
In article <8prsfo$1oj$1@agate.berkeley.edu>, nweaver@boom.CS.Berkeley.EDU says... > >In article <39BDE627.FF408617@no-spam.calweb.com>, >Peter Hanely <hanelyp@no-spam.calweb.com> wrote: >>My impression is that you can't patent an instruction set. Then again, >>a lot of patents have been granted that are plain stupid. >>In your favor, there are several Intel clone chips, that Intel would love >>to shut down if they could. > > I believe Intel has some patents on the IA64 ISA, but then >there are some significant new and novel features on it. >-- >Nicholas C. Weaver nweaver@cs.berkeley.edu Intel also managed to get a patent on something published by another company several years earlier and thereby could be considered as common knowledge. (And now some people think we europeans should get the same patent rules as the US. It's IMHO better to do the reverse, but on the other hand that would get a lot of US lawyers (people who manipulate the law) out of work, and that could be dangerous) regards /Björn Lindgren * These opinions are my personal ones *Article: 25604
On Thu, 14 Sep 2000 23:29:34 +0100, sergio oyaga <larrion@euskalnet.net> wrote: >Hi! > >I'm a student of Mondragon University and I=B4m working with Xilinx >Foundation. I want to practice boundary scan, and I don=B4t know if I can= > >do it with a Paralle Download III cable. > >Can anybody help me,please? > > What is it you are trying to practice? Does it have to be Xilinx specific? I seem to remeber that Texas Instruments did a JTAG simulator program that had all the basics. HTH David.Article: 25605
Ben, > > One thing I found useful is to print out a copy of > data sheet of the family of FPGA's you are using and any data > libraries and data macro function descriptions. sadly the Atmel website is a bit lacking in .PDF files for these chips.. Im hopeingtheres stuff onthe CD with the IDS software I have. > Also if your software is time limited it might be wise to > wait until you got back and you install the software on a virgin > PC. > Its not time limited, and Ive not installed it yet.. I panic everytime I install new software incase it screws up my PC. > > Many FPGA's are similar in design so general design ideas apply > to many devices. FPGA's in general don't map well to wide simple > gates like a 12 input NAND gate but map better to functions of 3 > or 4 variables like a 2 input multiplexer or ripple carry adder > cell.Registers are often free with every logic cell as well. > Small ram like 16xN may have to synthesized taking up a large > number of logic blocks. the Atmel has distributed RAM so Im hopeing I can use that... > The other thing is to understand the design you are creating > well in advance.Some logic layouts don't work well and others do > often with re thinking of the layout. KISS allways works best. > (Keep It Simple Stupid ). Good luck on your project. > Ive done the design I want using discrete logic, but its 26 odd logic chips mostly 4 bit adders and latchs (with a bit of SRAM).. I like to keep stuff simple, it helps when it comes to debugging! Thanks for the advice Paul > Ben. > -- > "We do not inherit our time on this planet from our parents... > We borrow it from our children." > "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchukArticle: 25606
Hello, has anybody out there experience with PCI designs on a Virtex/Virtex-E? I'm going to develop a PCI board (33Mhz/32Bit) on one of these devices. My idea is to have a lot of space left in my FPGA beside the PCI-Interface. Is there a core (or better a complete VHDL-Programming) aviable from Xilinx (or anybody else)? Does it work well and are any features of the PCI-Bus not supported? Is there a free version aviable on the internet? O.k., I'm sorry that my idea is not very concrete - I'm just looking for first information. Thanks for Your good tips Marc ReinertArticle: 25607
Marc Reinert wrote:
> I'm going to develop a PCI board (33Mhz/32Bit) on one of these devices.
> My idea is to have a lot of space left in my FPGA beside the
> PCI-Interface.
> Is there a core (or better a complete VHDL-Programming) aviable from
> Xilinx (or anybody else)? Does it work well and are any features of the
> PCI-Bus not supported? Is there a free version aviable on the internet?
Hi Marc,
Xilinx has the logiCORE PCI macrocell, which is a customizable
33/66/32/64 PCI interface. Check the Xilinx website for it, it's
price is around $5000, i guess.
Since you are a University, you might consider to join the Xilinx
Univ. Prg. XUP. There you can also apply for a donation of the core.
I tried that, but never got any reply on several emails/faxes.
But maybe you have more luck ;-)
Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Article: 25608
Dan,
I have not read Xilinx's notes on power coupling for the CPLD you are
using. I think that four .1uF caps should suffice, at least minimally, for
this application. Do you have good ground and power planes on your board?
Planes will help with this minimal decoupling.
When you say "minimum power," are you speaking of the average power?
The real issue here is the dynamic or instantaneous current draw, and that
is what the caps are for. If the device switches very fast and there are a
lot of FFs switching, then you will need more caps, regardless of the
average minimum power dissipated.
There is a lot of variables here Keep feeding us information, and the
group (which includes you!) will eventually get to the bottom of this.
These problems are interesting.
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
"Dan" <daniel.deconinck@sympatico.ca> wrote in message
news:8miw5.261590$1h3.5258160@news20.bellglobal.com...
> The decoupling is four .1uF caps. One at each corner of a QP240. I plan to
> make a new PCB with a .1uF at each power pin.
>
> When the device is drawing minimum power, shouldn't four decoupling caps
be
> enough ?
>
> Dan
>
>
>
>
>
Article: 25609On Thu, 14 Sep 2000 20:47:34 GMT, "S. Ramirez" <sramirez@deleet.cfl.rr.com> wrote: >Andy, > The ultimate and most elegant fix is to switch to Synplicity. >-Simon Ramirez, Consultant >-Synchronous Design, Inc. Except that, last time I looked, Synplify didn't know that Virtex had a sync reset. This can really mess up your CLB calculations. Don't know if this has been fixed. Anyone feel brave enough to run up a web page comparing different synthesisers?Article: 25610
"S. Ramirez" wrote: > > Thomas, > Of course I still call my company Synchronous Design! Parallel > synchronizers are simply a no-no design technique of synchronous design. Simon, What techniques do you use for synchronising parrallel data that is being generated asynchronously? Nial.Article: 25611
Hello Jean Paul, I'm working for BULL company in the servers division. We are currently designing a new I/O channels attachement for the Company's proprietaray mainframe line. The key for this new channel is the PCI (64 bits/ 66 MHz). We have 2 PCI agents to design: - The first one is a MASTER/TARGET PCI agent in a VIRTEX V600E chip. For this one, we use the PCI core and if I remenber correctly we paid $1995 for this core. - The second chip is a TARGET only agent. We need to have the PCI already configured at power on. So we couldn't use FPGA solution. The idea was to use a CPLD (the biggest of XC9500 family) and design by ourself the PCI TARGET interface. If your are interrese in more details, let me know by e-mail...Article: 25612
Well I have a phase output at 250HZ that XORS with a 1hz clock to pulse a ":" point in an LCD readout. I also have a bunch of slow clocks output from the CLPD (a 0.5 HZ, 1HZ, 250HZ, 2.048MHZ, 15hz) most VERY slow and 2.048MHZ is not to slow. Well whenever the 250HZ !$ 1HZ was high it put a big (1V) spike on both the 2.048MHz and 250HZ clock bringing it over 5V.. I also saw lots of random noise on the clock. Looked like noise bleeding into the clock line. Changing synthesis settings changed all this (and fixed a broken ABEL script that it trashed). As for grounding etc. issues.. it could be.. the target board was a kludged board I made to test the design b4 I went to glass. I have a "surf" board with thick ground traces (used solder braid) running close, short and tight. I tried to use good proto-practice but it's no substitute for the good 4 layer PCB this will be in the end. Still the design works now and I feel if it can survive my less than ideal proto environment then it will definitely survive the real world circuit board (back to PADS to finish this puppy). Hawker "John L. Smith" wrote: >> When you say 'noise', this doesn't say much. > Is this a decoded clock that is being generated, and you get > decoding glitches depending on whether some cover logic is > being reduced? If this is the case, not a worry, experienced > designers should know to look out for and how to handle that, > and you've just had your experience. > > Much more worrisome is if your output clock is simply a copy of > an input clock pin, and noise is induced depending on routing. > Hawker, which was the case for you? > >Article: 25613
Hello all,
What is the best way to set up timing constraints. I am using xilinx
3.1li software.
The desing is targeting a spartan II XC2S150-5PQ208, running at 50 Mhz
and using both clock edges. Standard the timing constraints involve only
the OFFSET in BEFORE clock and OFFSET out after clock, and the clock
frequency.
How do i figure out what timing constraints to set. Do i need any
special constraints because i am using the rising and falling edge.
For instance :
process (clock, reset)
begin
if (reset = '1') then
elsif (falling_edge (clock)) then
if (input_x = '1') then
A;
else
B;
end if;
end if;
end process;
suppose input_x is set on the rising_edge of the clock, it is used in an
equation on the falling edge, so it should be there before the clock
does. I presume that i must set up a timing constraint. But what kind of
constraint, and how do i do it.
the standard constraints are :
--------------------------------------------------------------------------------
Constraint | Requested | Actual |
Logic
| | |
Levels
--------------------------------------------------------------------------------
TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO | 20.000ns | 12.767ns |
4
TIMEGRP "PADS" 20 nS | | |
--------------------------------------------------------------------------------
* TS_clock = PERIOD TIMEGRP "clock" 20 nS | 20.000ns | 20.526ns |
5
HIGH 50.000 % | | |
--------------------------------------------------------------------------------
OFFSET = IN 20 nS BEFORE COMP "clock" | | |
--------------------------------------------------------------------------------
OFFSET = OUT 20 nS AFTER COMP "clock" | | |
--------------------------------------------------------------------------------
OFFSET = IN 10 nS BEFORE COMP "clock" | 10.000ns | 9.287ns |
5
--------------------------------------------------------------------------------
* OFFSET = OUT 10 nS AFTER COMP "clock" | 10.000ns | 15.832ns |
4
--------------------------------------------------------------------------------
What excactly do the offset = in and offset = out mean. Do they mean
that a signal must be valid X ns BEFORE the clock signal arives, and
that a signal is Y seconds AFTER the clock has arived stable?
Richard
--
Quest Innovations
tel: +31 (0) 227 604046
http://www.quest-innovations.com
Article: 25614
If I am remember right, I though Xilinx will provide a free Demo PCI
64 core on their website for use.
http://www.xilinx.com/products/logicore/pci/pcicorge.htm
This may help or not help you.
On Fri, 15 Sep 2000 11:27:59 +0200, Lars Rzymianowicz
<larsrzy@ti.uni-mannheim.de> wrote:
>Marc Reinert wrote:
>> I'm going to develop a PCI board (33Mhz/32Bit) on one of these devices.
>> My idea is to have a lot of space left in my FPGA beside the
>> PCI-Interface.
>> Is there a core (or better a complete VHDL-Programming) aviable from
>> Xilinx (or anybody else)? Does it work well and are any features of the
>> PCI-Bus not supported? Is there a free version aviable on the internet?
>
>Hi Marc,
>
>Xilinx has the logiCORE PCI macrocell, which is a customizable
>33/66/32/64 PCI interface. Check the Xilinx website for it, it's
>price is around $5000, i guess.
>Since you are a University, you might consider to join the Xilinx
>Univ. Prg. XUP. There you can also apply for a donation of the core.
>I tried that, but never got any reply on several emails/faxes.
>But maybe you have more luck ;-)
>
>Lars
>--
>Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
>Tel: +(49) 621 181-2716, Fax: -2713
>email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
>Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Return Email Address is:
ralphwat dot home at excite dot com
Article: 25615
Dan,
Ignore the previous post. You are using a Virtex XCV600. Xilinx has
an app note that tells you how much decoupling to use. I do not have it in
front of me, but I know that it requires big capacitors, and I think these
big capacitors are overkill. It does require more caps that what you told
us about; however, at the company I work at we collectively decided that
they are not enough. We think that 0.1uF or 0.01uF caps are required for
every pin. This assumes ground and power planes.
Your problem, though, may involve something other than power quality.
I would involve the Xilinx FAE on this one.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Dan" <daniel.deconinck@sympatico.ca> wrote in message
news:8miw5.261590$1h3.5258160@news20.bellglobal.com...
> The decoupling is four .1uF caps. One at each corner of a QP240. I plan to
> make a new PCB with a .1uF at each power pin.
>
> When the device is drawing minimum power, shouldn't four decoupling caps
be
> enough ?
>
> Dan
>
>
>
>
>
Article: 25616Robert Posey wrote: > [snip] > > There should be no threat of people patenting > existing algorithms, since unless a person can prove they invented something > first and started the patent process with reasonable dispatch, the patent > is invalid. So I can't patent Quick Sort and A*, there goes that easy > trillion bucks. The flaw in this logic is that in order to patent something, all I have to do is to convince a patent examiner that I have developed something novel. Only if the examiner can find prior patents or examples of prior art will my patent be denied. [snip] > > Until Americans acknowledge that the Government needs truly qualified people > and that to get them will cost real money these problems will continue. You > can't expected an agency forced to staff its offices with engineers that > are paid 20-30% less than private industry, and got C's in school to be > able to monitor the volume of patent applications they receive. I don't think that any system that depends on a small group of patent examiners, no matter how smart or well paid they are, can keep up with developments in all areas of industry. Alot of 'prior art' exists but is not known well enough outside of a specific industry where an examiner might be aware of it. In some cases, someone may have incorporated some technique or idea into a product for years without considering it to be patentable. Now, unaware of this (or worse yet, with full knowledge) a competitor 'discovers' this idea and applies for a patent. If the prior use of this isn't obvious to an outsider (you might have to reverse engineer a product or examine a manufacturing process), the first person has no defense in our patent system unless he(she) is lucky enough to intervene in the application prior to its final decision. -- Paul Hovnanian | (here) mailto:hovnania@bcstec.ca.boeing.com Software Conflagration | (there) mailto:Paul@Hovnanian.com Control | (spam) mailto:postmaster@mouse-potato.com -----------------------+--------------------------------------------- They say that if you have an infinite number of monkeys typing at an infinite number of keyboards for an infinite period of time, you will get the collected works of Shakespeare. If you get the source code to Microsoft Windows, you need to add more monkeys.Article: 25617
Rick, The increased current draw occurs at about 0.6 to 0.8 Vdc in Virtex. It occurs at the POR trip point in 4K (see respective data sheets). The differences between the virtex and 4k power up cleanout circuits are not something I can discuss. While a supply is ramping up, it is driving the filter capacitors to the intended output voltage, and the supply is often current limited (can't supply any more current than it already is) while doing this, and hence the power ramp up time is constrained (i.e. not instant, by I=C*dV/dt). If I had 2000uF of capacitance, and it rises in 2 ms (typical of a really fast power ramp), that is 2.5V into 2,000uF in 2 ms, or I=2.5A. If I had 2000uF of capacitance, and the device suddenly requires 500 mA, you can see what the dV/dt would be. But, nothing is sudden, and the voltage and current interact. Even hot swap PCI has a rise time due to the resistance and inductance of the pcb traces to the bypass capacitors of usually no faster than 1 ms. You can think of Virtex as being a really big non-linear capacitor. It actually draws less current as the ramp slows down. This makes this a chicken and egg problem: how does the power ramp? Is the part connected? they affect one another. We test to make sure that if a power supply could supply no more than 500 mA (in Virtex C grade), the device would be ready for configuration and the vccint is at the power supply vccint (not sagging, or collapsed). The Virtex part may put a flat spot in the ramp up, but that is just fine (we just don't like to see it foldback, and dip which is the case with a power supply that is arranged for a foldback response -- datasheet recommends against this kind of behavior!). We have noted that if you could only supply 100 mA, the ramp might be really long (~100 ms), but the part would clean out, and start to configure. Virtex is not going to be characterized for low current startup, as most designs require more than 500 mA while operating (no market push to do this). Spartan2 on the other hand will be considered (is now being characterized) for lower current startup as the markets are different for the two parts (there is a push to do this). I hope this answers the first question, and I hope you understand that I can not discuss the internal circuit design and operation here required to answer you second question, Austin rickman wrote: > That was not the question. *When* does the high current draw happen. Is > this as the Vdd ramps up, or is this after the chip is fully powered and > starts the configuration? Supplying a high current after the supply is > up is one thing. Suppling the high current while the supply is coming up > is a different matter. > > Specifically, what is it that you are saying is *different* between the > 4K series and the Virtex series??? > > Austin Lesea wrote: > > > > Rick, > > > > Virtex I parts require a 2A minimum current limited power supply if you > > intend to start up at -40C. > > > > Austin > > > > rickman wrote: > > > > > Austin Lesea wrote: > > > > > > > > Henryk, > > > > > > > > The INIT holdoff warning applies to 4K only. It does not apply to > > > > Virtex, and Virtex architecture derivatives. > > > > > > > > I am sorry for the confusion. > > > > > > > > In 4K, holding INIT and preventing clean out does not make the device > > > > HOT -- it may be that the 4K device is in contention from the Vcc not > > > > going down below a few hundred millivolts, and then the Vcc returns, > > > > and the 4K device is in a partially configured state, and drawing > > > > current. So the device is already HOT and getting hotter, and INIT > > > > prevents the clean out. > > > > > > ********************* This bit right here > ******************************** > > > > Again, Virtex, Virtex E, Spartan2 do not have this behavior. The > ********************* This bit right here > ******************************** > > This is the statement I am asking you to clarify. Tell us about the > difference noted above. > > Perhaps I am not familiar with the INIT holdoff warning in the first > place. My understanding was that pulling PRGM low started the clearing > of the configuration memory. This proceeded until PRGM was released. > Once complete, the INIT pin was released to indicate that configuration > could procede. But if the INIT was held low externally, the FPGA would > wait. > > How does this cause high current consumption? The configuration memory > should have been cleared at this point and the supply current should be > under control. What am I missing? > > > > > design is such that the means of contention that were caused by memory > > > > contents which occurred in 4K do not exist in Virtex. > > > > > > Can you be a little more specific as to what behaviour you are talking > > > about? The Virtex data sheet claims it needs up to 2 Amps of current for > > > startup. So I assume that you are saying that the Virtex does not > > > continue to draw heavy current when INIT is held low? Is that right? > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 25618
Doug, Good points re: filters. That is why I used the crystal based filter. As for the patent, it still provides revenues for the company I worked for from licensing fees. It was even challenged by another company. I remember hearing about the engineer at that company who cursed me up and down the halls....he was too lazy to have documented the "invention" in his notebook or else he could have shown prior art, and been free to use it, and saved his company a ton of money. "Obvious" has a legal meaning. Ever see that nose strip that holds your nostrils open while you exercise? The patent on that is quite valid, and makes someone a whole lot of money. Austin doug wrote: > Filters are a bad idea except under very special conditions. You need > to have a fixed frequency and that frequency needs to be in a special > relationship with the clock. If you are near a binary divisor of the clock > frequency, the jitter will produce sidebands too near the carrier to be > removed by any filter that makes reasonable sense. The D/A makes > a tuneable filter and it works well. > I did extensive computer simulations of this when I made all digital plls > nearly 20 years ago (probably long predating any patents on the obvious > idea) and found that with a careful choice of frequency, the spurs could > be avoided in some small range. However, making a broad range source > did not justify the effort to try to skip the D/A. Sine lookup table are > not > necessary. > Companies like Analog Devices have made the discussion moot with their > line of cheap and versatile DDCs. They work very well and are easy to use > and do not require much in the way of external parts. > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:39BD6DE1.2F8CC8DC@xilinx.com... > > You are correct in stating that a filter is required to reduce jitter, > > > > A bandpass filter with high Q is what is needed. The PLL with VCXO has a > Q of > > millions. A good tank circuit works also, but less well (Q ~100). > > > > Guess what happens when you put the square wave MSB) into the same band > pass > > filter? Pop: out comes the fundamental (for less money). > > > > I always get a kick out of all of those expensive sine wave lookups tables > and > > A/D's doing nothing. > > > > If a low Q filter is used, there is some tiny improvement in the lookup > table > > conversion method due to the sideband power not adding to the overall > phase > > noise. > > > > Don't take my word for it, use a good spectrum analyzer to analyze the > sidebands > > at each point in the circuit. Take out the D/A and see what changes. It > > usually makes the jitter less because of D/A noise issues, reference nosie > > issues, and comparator noise issues. > > > > "The common wisdom is neither common, nor wise." anon. > > > > Austin > > > > rickman wrote: > > > > > You are not totally correct Austin. If you want a square wave without a > > > lot of jitter, then you do need the sine wave which can be filtered to > > > produce a wave of just the fundamental. This is then compared to a fixed > > > voltage to produce a square wave with no jitter. > > > > > > If you don't do this, you will have a time jitter equal to your master > > > clock period as you noted. This is often not acceptable and the sine > > > wave lookup, DAC and filter can be less circuitry than the VCXO, phase > > > comparator and filter. In fact you can get the whole shebang in one chip > > > less the filter. > > > > > > Austin Lesea wrote: > > > > > > > > Nestor, > > > > > > > > A DDFS (direct digital frequency synthesizer) is an adder/accumulator. > > > > They have been around for perhaps 30 years now. I have used them for > > > > years in FPGAs. The sine look up table is only used if you want a > sine > > > > wave. I have seen people use a sine look up table, a D/A, and then > follow > > > > that mess with a comparator -- TO GET A SQUARE WAVE! Think about it. > The > > > > MSB of the DDFS was already the signal they wanted! > > > > > > > > So, if you don't want a sine wave, don't add all that junk. > > > > > > > > The p-p jitter is the clock period used, and the Fout < 1/2 Fclock. > > > > > > > > I would use the highest frequency I could get away with. If you > require > > > > even less jitter, the output can be passed through a single simple > VCXO > > > > used in a PLL loop with an XOR phase detector and an external RC to > remove > > > > practically all of the jitter if the frequency output range is narrow > > > > enough. > > > > > > > > Placing the DDFS in a locked loop, results in a complete digital > locked > > > > loop (Patented -- look it up, under my name). > > > > > > > > There are many nice parts out there that package the whole thing, and > are > > > > inexpensive, so you need to evaluate what it is going to be used for, > and > > > > decide if you want to build it in, or not. > > > > > > > > Also look at: > > > > > > > > http://www.xilinx.com/xcell/xl31/xl31_32.pdf > > > > > > > > for fractional synthesis,and other NCO's. > > > > > > > > Austin Lesea > > > > > > > > Nestor wrote: > > > > > > > > > Hi. > > > > > > > > > > Does anyone know any manufacturer who fabricates > > > > > numerically-controlled crystal oscillators (NCXO), also known as > > > > > digitally-controlled crystal oscillators (DCXO) which are suitable > for > > > > > digital phase-locked loop designs in VHDL and FPGAs? > > > > > > > > > > Although these blocks resemble a numerically-controlled oscillator > > > > > (NCO), they differ in that the NCXO is not oversampled to generate > the > > > > > required output signal (an NCO needs to be oversampled by at least > > > > > 8-times in order to have an acceptable low jitter output). Rather, > a > > > > > digital input word is fed to the NCXO and it synthesizes the > required > > > > > output frequency using a standard, low-cost crystal oscillator. The > > > > > output is also a square wave, just like the standard crystal. In > > > > > general, the NCXO has a narrow tuning range similar to a > > > > > voltage-controlled crystal oscillator (VCXO), e.g. +/-150ppm > relative > > > > > to a frequency in the MHz range. > > > > > > > > > > The NCXO technology is fairly recent from what I understand, but > > > > > allows one to replace a circuit composed of a digital-to-analog > > > > > converter (DAC) and a VCXO by one chip that performs the exact same > > > > > task will less design hassles. The DCXO is ideal for custom-made > > > > > phase-locked loop (PLL) circuits using digital sections that can be > > > > > implemented in VHDL and FPGAs. > > > > > > > > > > Since I haven't been able to find any NCXO manufacturers over the > web, > > > > > I am now looking to the knowledgeable engineers, designers and > friends > > > > > that frequent these newsgroups for some potential referrals and/or > > > > > links. > > > > > > > > > > Thanks in advance for your help. > > > > > > > > > > Nestor > > > > > > -- > > > > > > Rick Collins > > > > > > rick.collins@XYarius.com > > > > > > Ignore the reply address. To email me use the above address with the XY > > > removed. > > > > > > Arius - A Signal Processing Solutions Company > > > Specializing in DSP and FPGA design > > > > > > Arius > > > 4 King Ave > > > Frederick, MD 21701-3110 > > > 301-682-7772 Voice > > > 301-682-7666 FAX > > > > > > Internet URL http://www.arius.com > >Article: 25619
Simon, I would bug anyone until I make a four layer board. If the problem is still there, I'll post details. I once heard the both a .01 and a .1 cap should be used at each power pin. Is that correct. My limited knowledge tells me they would be equal to one cap of .11. However I realize there behaviour is more complex than that. Is such a recomendation useful ? DanArticle: 25620
Hey, Could someone of you explain me PHYSICALLY why the path delay between two synchronous components is considered as the maximum clock period. The logic levels are1 and 0. so if i send a pulse 1 and later 0 in less than the path delay, from where comes the problem dV=-E.dx, and the electrons have the same speed, so why the conflict occurs? --Erika Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25621
This is a multi-part message in MIME format. --------------BCC250B07A5312AD1C9CF7AF Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, I'm a final year electrical electronics engineering student. I'm using Max Plus 2 Baseline 9.6 to do my final year project. Is there anyone out there with full licences? Can you send me a copy of your license.dat or can anybody tell me how to get the partitioner features from it. Thanks in advance. --------------BCC250B07A5312AD1C9CF7AF Content-Type: text/x-vcard; charset=us-ascii; name="gk7eong.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for gk7eong Content-Disposition: attachment; filename="gk7eong.vcf" begin:vcard n:Goh;Kheng Teong x-mozilla-html:FALSE adr:;;;Johor Bahru;Johor;;Malaysia version:2.1 email;internet:gk7eong@pd.jaring.my fn:Kheng Teong Goh end:vcard --------------BCC250B07A5312AD1C9CF7AF--Article: 25622
gk7eong wrote: > > Hi, > > I'm a final year electrical electronics engineering student. I'm using > Max Plus 2 Baseline 9.6 to do my final year project. Is there anyone out > there with full licences? Can you send me a copy of your license.dat or > can anybody tell me how to get the partitioner features from it. Thanks > in advance. I can send you a license.dat for ModelSim. It will be as useful to you as anyone's Max+Plus 2 license.dat file, since the software is node-locked. You could consider having your school pay for the software, which is the Right Thing to do. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25623
erika_uk@my-deja.com wrote: > > Hey, > > Could someone of you explain me PHYSICALLY why the path delay between > two synchronous components is considered as the maximum clock period. > > The logic levels are1 and 0. > so if i send a pulse 1 and later 0 in less than the path delay, from > where comes the problem > dV=-E.dx, and the electrons have the same speed, so why the conflict > occurs? If the path delay between your registers is at most 10 ns, then do the math. The reciprocal of time is frequency, so 1/10ns = 100 MHz. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25624
Richard Meester wrote: > > Hello all, > > What is the best way to set up timing constraints. I am using xilinx > 3.1li software. > > The desing is targeting a spartan II XC2S150-5PQ208, running at 50 Mhz > and using both clock edges. Standard the timing constraints involve only > the OFFSET in BEFORE clock and OFFSET out after clock, and the clock > frequency. > > How do i figure out what timing constraints to set. Do i need any > special constraints because i am using the rising and falling edge. > For instance : > > process (clock, reset) > begin > if (reset = '1') then > elsif (falling_edge (clock)) then > if (input_x = '1') then > A; > else > B; > end if; > end if; > end process; > > suppose input_x is set on the rising_edge of the clock, it is used in an > equation on the falling edge, so it should be there before the clock > does. I presume that i must set up a timing constraint. But what kind of > constraint, and how do i do it. If you put a period constraint on your clock -- in your case, 50 MHz (or 20 ns, which is equivalent) -- and if you use both edges of the clock in the design, the P+R tools are smart enough to know that you've got a "two-phase clock" and it will automatically set the constraints for things "from the rising edge to the falling edge" and "from the falling edge to the rising edge" to half the clock period, or 10 ns. > What excactly do the offset = in and offset = out mean. Do they mean > that a signal must be valid X ns BEFORE the clock signal arives, and > that a signal is Y seconds AFTER the clock has arived stable? OFFSET IN AFTER means that the data signal into the FPGA will be valid at the FPGA input pin x ns after the clock arrives at the driving device's clock pin. OFFSET IN BEFORE means that the signal going into the FPGA will be valid at the FPGA input pin x ns before the clock arrives at the FPGA clock pin. OFFSET OUT AFTER means that output data will be valid at the FPGA pin x ns after the clock arrives at the FPGA's clock pin. OFFSET OUT BEFORE means that output data will be valid at the FPGA pin x ns before the clock arrives at the next device's clock pin. Note that you really want to understand your PC board's delays, and you should probably use a zero-skew clock buffer to make your life easier. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u
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