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Hi folks!
We are using FC2 on SunOS5.8, with either CDE or KDE/Openwin.
Everything works fine, except the Online Help. When clicking
the Help -> Topics button, a winhelp process is started, but
never shows up on the screen. FC2 then stalls forever...
Has anyone seen this behavior? Workarounds?
The README mentions some problems with the Online Help,
but the -t or -f switches don't solve it.
Any ideas?
Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Article: 25926I had the same problem with Leonardo. It automatically assigns clocks to BUFGs, you can disable this feature and specifically tell it to put the clocks you want on BUFGs. After you do this in synthesis, the constraint 'uselowskewlines' works with the Xilinx tools.(3.1i) set insert_global_bufs FALSE set_attribute .work.arch.struct.clockname -name PAD -value BUFGP -port These are the commands for Leonardo. I'm not sure about other synthesis tools, they must have some such feature too. Hope this helps. Hannah Richard Meester wrote: > Hello All, > > I have some trouble regarding primary global and secondary global clock > lines. > > I have a design that generates a clock from two inputs. This clock is > then used to clock other ff's. The problem now is that there are only 4 > global clock lines with low skew in the spartan II (which i am using) > and i need aprox 8. The 4 global clock lines are used for other > purposes. There are however 24 secondary global lines which also could > do the job. > > Now my design is not yet finished, but when i implement/synthesize part > of the design, it inferres BUFG (1 of the primary global clocks) instead > of just a IBUF, and placing the pin on the top or bottom row of the > device. I looked at the xilinx site, nothing usefull found. I have the > constraints setup for these lines with USELOWSKEWLINES. I also tried by > hardcoded instantiating an IBUF to the clock line, but it gets replaced. > > Anybody some suggestions???? > > Richard > > -- > Quest Innovations > tel: +31 (0) 227 604046 > http://www.quest-innovations.comArticle: 25927
I have a chain of JTAG devices, many of which are VirtexE FPGAs and I am trying to do a readback operation for program verification. It appears that I am reading back good data for the first component in the chain, but for any Virtex part passed the first I read the same 32 bits over and over. I am quite certain that the problem is not a targeting issue (I am not over/under shifting). Has anyone else had this problem? Any help would be greatly appreciated. Thanks. Mike DeKoker Signatec, Inc.Article: 25928
Hi Christophe, What simulator are you using? I have not used coregen RAM, but my wild guess would be that you have a bug in your simulator :) Good luck, Johan P :) Christophe Heyert wrote: > > A very strange thing happened to me yesterday. I'm using a RAM block > generated by the Coregenerator in > my structural design. > The first time I didn't have any problems i my behavioral simulation, > but the second time the following error appeared. > > Internal ERROR : Access violation > Occurred in architecture BEHAVIORAL of entity > C_MEM_BLOCK_V1_0 (which is a single port RAM block). > > Where does this problem come from? > > christopheArticle: 25929
Simon, wat is a normal value in ns for "good low-skew routing". In need this skew to be close to zero because i generate a clock from these lines. Secondly i stoped the synthesiser inserting bufgs by allocating all bufg's to bogus lines, this was the only thing that succeeded in XILINX 3.1li Simon wrote: > There are _no_ secondary clock nets on the Virtex/E/SpartanII. This was > an unfortunate choice of wording in (early?) Virtex data. > > You should be able to stop your synthesiser inserting BUFGs in your > secondary nets. Synplify does this via the 'syn_noclockbuf' attribute. > > You can get good low-skew routing off the top/bottom pins to adjacent > columns, particularly if you keep within the span of a 'hex' line. What do you meen by span of a 'hex' line, i am not very familiar with floorplanning and the fpga editor, although i learned a lot today. (cost a lot of hours, and timing seemed to get worse by the hour when moping around with the floorplanner.) Richard > > Try playing around in the Editor to see what is possible. > > Richard Meester wrote in message > <39D0964B.50AD8AD0@quest-innovations.com>... > >Hello All, > > > >I have some trouble regarding primary global and secondary global clock > >lines. > > > >I have a design that generates a clock from two inputs. This clock is > >then used to clock other ff's. The problem now is that there are only 4 > >global clock lines with low skew in the spartan II (which i am using) > >and i need aprox 8. The 4 global clock lines are used for other > >purposes. There are however 24 secondary global lines which also could > >do the job. > > > >Now my design is not yet finished, but when i implement/synthesize part > >of the design, it inferres BUFG (1 of the primary global clocks) instead > >of just a IBUF, and placing the pin on the top or bottom row of the > >device. I looked at the xilinx site, nothing usefull found. I have the > >constraints setup for these lines with USELOWSKEWLINES. I also tried by > >hardcoded instantiating an IBUF to the clock line, but it gets replaced. > > > >Anybody some suggestions???? > > > >Richard > > > >-- > >Quest Innovations > >tel: +31 (0) 227 604046 > >http://www.quest-innovations.com > > > > -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 25930
From memory, skew can be very low - tens of ps. The 'secondary clock' routing is just fine for clocking a FIFO on incoming data, but maybe not so great for a chain of FFs. Richard Meester wrote in message <39D0EA2E.2530BB08@quest-innovations.com>... >Simon, > >wat is a normal value in ns for "good low-skew routing". In need this skew >to be close to zero because i generate a clock from these lines. > >Secondly i stoped the synthesiser inserting bufgs by allocating all bufg's to >bogus lines, this was the only thing that succeeded in XILINX 3.1li > >Simon wrote: > >> There are _no_ secondary clock nets on the Virtex/E/SpartanII. This was >> an unfortunate choice of wording in (early?) Virtex data. >> >> You should be able to stop your synthesiser inserting BUFGs in your >> secondary nets. Synplify does this via the 'syn_noclockbuf' attribute. >> >> You can get good low-skew routing off the top/bottom pins to adjacent >> columns, particularly if you keep within the span of a 'hex' line. > >What do you meen by span of a 'hex' line, i am not very familiar with >floorplanning and the fpga editor, although i learned a lot today. >(cost a lot of hours, and timing seemed to get worse by the hour when moping >around with the floorplanner.) > >Richard > >> >> Try playing around in the Editor to see what is possible. >> >> Richard Meester wrote in message >> <39D0964B.50AD8AD0@quest-innovations.com>... >> >Hello All, >> > >> >I have some trouble regarding primary global and secondary global clock >> >lines. >> > >> >I have a design that generates a clock from two inputs. This clock is >> >then used to clock other ff's. The problem now is that there are only 4 >> >global clock lines with low skew in the spartan II (which i am using) >> >and i need aprox 8. The 4 global clock lines are used for other >> >purposes. There are however 24 secondary global lines which also could >> >do the job. >> > >> >Now my design is not yet finished, but when i implement/synthesize part >> >of the design, it inferres BUFG (1 of the primary global clocks) instead >> >of just a IBUF, and placing the pin on the top or bottom row of the >> >device. I looked at the xilinx site, nothing usefull found. I have the >> >constraints setup for these lines with USELOWSKEWLINES. I also tried by >> >hardcoded instantiating an IBUF to the clock line, but it gets replaced. >> > >> >Anybody some suggestions???? >> > >> >Richard >> > >> >-- >> >Quest Innovations >> >tel: +31 (0) 227 604046 >> >http://www.quest-innovations.com >> > >> > > >-- >Quest Innovations >tel: +31 (0) 227 604046 >http://www.quest-innovations.com > >Article: 25931
Gang, Check out http://support.xilinx.com/techdocs/10127.htm for the Official Answer. Xilinx sez it's a bug in FPGA Express, which it is, and hopefully Synopsys will see fit to fix it, rather than ignoring it. The workaround is to instantiate a falling-edge triggered flop, which is not acceptable. My suggestion to Xilinx: Shit-can FPGA Express. Get Synplicity on your team. Thank you. Drive through. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25932
Is there any possibility to extract an "ordinary" logic circuit schematic from a hdl file?Article: 25933
Andy,
Great and candid response! I just wish you had talked to me about FPGA
Express a couple of years ago!!
To make Synplicity less expensive, order the Xilinx-only license.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Andy Peters n o a o [.] e d u>" <"apeters <"@> wrote in message
news:8qr607$6tt$1@noao.edu...
> Gang,
>
> Check out http://support.xilinx.com/techdocs/10127.htm for the Official
> Answer.
>
> Xilinx sez it's a bug in FPGA Express, which it is, and hopefully
> Synopsys will see fit to fix it, rather than ignoring it. The
> workaround is to instantiate a falling-edge triggered flop, which is not
> acceptable.
>
> My suggestion to Xilinx:
>
> Shit-can FPGA Express. Get Synplicity on your team.
>
> Thank you. Drive through.
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
Article: 25934
Daniel Nilsson wrote:
>
> Is there any possibility to extract an "ordinary" logic circuit schematic
> from a hdl file?
Do you mean one a normal designer can read, or one that is
logically correct ?
The problems with text to symbol conversion are twofold
a) where to put the symbols, & 'rats nest' connections
b) many of code blocks I write would make lousy
schematics, even if drawn carefully!
So, going below a certain detail threshold makes little sense.
That said, it should be relatively easy to correlate a block overview
rather than a AND.OR.XOR gate drawing.
-jg
Article: 25935Hello: Now, i am doing "16bits converting 64bits fifo" of four channels ,my application is to write a lot of data to a fifo first by polling ,and then read it from the fifo by polling, my design is: the input data is 16 bits width,and use four 16 bits latches and 2 bits counter,the data is sent into 64 bits fifo when counter==2'b11.And then i will transfer it at the top level,if i write and read only a certain fifo ,the data of being read is correct.However,when i switch channel,the reading first data is 0 from the switched channel.Obviously ,the "0" of 64 bits is excrescent,but the back data is correct,that is ,it reads a "0" more.the phenomena happens only switching channel. why?Article: 25936
Dear System-Chip Advocates:
An outstanding program is now complete for our annual
VSI Alliance Member Meeting in Silicon Valley, October 25.
If System-Level ICs are important to you, so is this meeting.
Presentations on how major companies are handling the SoC design and
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include:
· Keynote: Dr. Walden Rhines, President of Mentor Graphics:
"Design Reuse: Great Promise, Great Difficulty, Great Decisions Ahead"
· Tom McCloud, Intel, General Manager, Central Capabilities
Engineering,
Wireless Computing and Communications Group
· Anssi Haverinen, Nokia, Research Manager
· Robert Payne, - Philips Semiconductors, VP of System ASIC
Technology,
· Jim Ballingall - UMC Group, VP World Wide Marketing
· Timothy O'Donnell, VSIA President and President of ARM, Inc.:
"Progress and Direction of the Alliance"
· Larry Rosenberg, VSIA Technical Committee Chair:
"VSIA Technical Update and Projections "
For more information and registration form see www.vsi.org.
· Santa Clara Marriott Hotel, from 9 till 5.
· Admission free for members and non-members.
· Continental breakfast and registration from 7:30a.m.
· Lunch served
· Cocktail reception at 5p.m.
· VSIA orientation at 8a.m. for those not familiar with the
Alliance, to understand what it's about and how it
works.
Or register by email at jennifer@vsi.org or phone 408-356-8800
I look forward to seeing you there.
Stan Baker
Executive Director
VSI Alliance
Article: 25937> A barrel shift and a programmed arithmetic shift are the same circuit other than > the connections at the ends of the shift. In the barrel inputs that would come > off one end are connected from the other end, in the arithmetic, they are > connected to the sign, and in a logical to zero. It would be a fairly trivial > modification if you could get into the source on the cores. Thanks again! After revisiting the arithmetic-shifter implementation, as per your advice, I was able to cut the shifter's FPGA resource utilization down to 'normal.' Apparently, my original HDL implementation (using a for-loop inside an always@ block) synthesized very inefficiently. I deleted the for-loop and manually assigned buses corresponding to each 'stage' of the shifter.Article: 25938
I mean a schematic that tells you how to build the design using ordinary 74 logic. I am a student, and fpga's cost me very much, so if I only do a small design it makes more sense for me to put it in discrete logic. I also wonder if anyone has knowledge of putting part of the logic outside the fpga to reduce fpga size? (counters, shift-registers)Article: 25939
Hi Evan, >>http://www.qsl.net/wb6tpu/si_documents/docs.html > >Thanks for the link. The fourth paper in the list is "Decoupling >capacitor calculations", and its one that I read a couple of years >ago; I haven't read the others. > >However, without wishing to be offensive, I have to say that this >paper is just plain wrong. The recommendations the author arrives at >are way too low. The basic problem is that he's taking an *average* >power consumption for his boards, and then deriving the charge >required per clock cycle, and giving the capacitor size required to >supply this charge. This completely ignores the fundamental reason for >using capacitors to supply 'instantaneous' current to a device. There >will be times when a device suddenly needs current because, for >example, an unusually large number of internal nodes are charging, >several outputs are switching simultaneously, an internal clock edge >has just occurred, or whatever. These requirements are not necessarily >directly related to the devices clock frequency and may, for example, >occur 5ns after every 10th input clock, in a 2ns window. The point of >having local reservoir capacitors is to supply these instaneous >current requirements, which can't be supplied by the PSU since the >main supply inductances don't allow charge to be supplied 'quickly'. >Sure, you can average everything up and come up with a time-averaged >requirement, but it doesn't help. You need to know what the worst-case >instantaneous requirement is, and you have to calculate the required >capacitor which will supply this requirement, with an acceptable >voltage droop, and with a low enough inductance to allow it to be >supplied while it's still useful. > >It would be interesting to hear from anyone else who's read this paper >and has a view on it. My understanding of these papers is that the worst case requirements (large numbers of nodes switching etc) define your target impedance. Since you don't know at what times these demands will occur, you then need to provide that impedance all the way up to the max switching rate of the modes in question. Maybe I missed something, (or am thinking of a dofferent paper!) but that was how I felt things to work. Of course, none of this takes into account ground bounce/SSN problems! There was a good discussion on this topic on the Signal integrity mailing list recently. Archives are also at http://www.qsl.net/wb6tpu so you may have already seen them - the subject was "Decoupling capacitors (again!)" Hope that helps, Martin > >Evan TRW Automotive Advanced Product Development, Stratford Road, Solihull, B90 4GW. UK Tel: +44 (0)121-627-3569 mailto:martin.j.thompson@trw.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25940
Evan wrote: > >It occurs to me that it would be useful to pool the information that >we do have, and to find a structured way of getting the information >that we don't have, so that this information gets into the public >domain. This would involve, as a starting point, writing or collecting >various code templates, passing them around to anyone who has the >appropriate tools and is willing to help (possibly anonymously), and >collecting the results on a website. > Good idea! >Is anyone interested in doing this? If there's a critical mass, I >could try setting up a mailing list and a web site and repository, >hopefully using existing resources from eda.org, seul.org, >sourceforge, or whatever. > I would... I have Synplify (Non-Pro unfortuanetly) at work for Altera. Cheers, Martin TRW Automotive Advanced Product Development, Stratford Road, Solihull, B90 4GW. UK Tel: +44 (0)121-627-3569 mailto:martin.j.thompson@trw.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25941
I am having a problem with using "dont cares" in a truth table for an 8-1 multiplexer. My attempt is shown below. There must be a way of optimising the truth table using "don't cares" but I can't seem to find out how to do it. Can anyone help? The truth table I'm trying to reproduce looks like this. C2, C1, C0, A7, A6, A5, A4, A3, A2, A1, A0 D 0 0 0 x x x x x x x 0 0 0 0 0 x x x x x x x 1 1 0 0 1 x x x x x x 0 x 0 0 0 1 x x x x x x 1 x 1 0 1 0 x x x x x 0 x x 0 0 1 0 x x x x x 1 x x 1 etc....... My attempt A7..A0 PIN; A = [A7..A0]; C2..C0 PIN; C = [C2..C0]; D PIN istype 'dc,com'; Equations TRUTH_TABLE ([C,A] -> [D]) [0,0] -> [0]; [0,1] -> [1]; [1,0] -> [0]; [1,2] -> [1]; [2,0] -> [0]; [2,4] -> [1]; [3,0] -> [0]; [3,8] -> [1]; [4,0] -> [0]; [4,16] -> [1]; [5,0] -> [0]; [5,32] -> [1]; [6,0] -> [0]; [6,64] -> [1]; [7,0] -> [0]; [7,128] -> [1]; end Mux40Article: 25942
In article <8qpmb5$dhi$1@reader1.fr.uu.net>, "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote: > > "Klaus Falser" <kfalser@durst.it> wrote in message > news:8qpkjh$rbk$1@nnrp1.deja.com... > > In article <8qpibm$bf3$1@reader1.fr.uu.net>, > > "Marc Battyani" <Marc.Battyani@fractalconcept.com> wrote: > > > ... the Xilinx trick is > > > to force the output to "1" and then tristate it so that the rise time is > > > much shortened compared to only tristating it. > > > Doing this reduce the rise time from 20ns to 3ns. > > > > ... > > Maybe this slightly modified statement does what you want : > > > > output_pin <= 'Z' when desired_output = '1' else desired_output; > > > > This assumes that threestating is slower than the gate delay > > (which usually holds true). > > I think it could be more like : > output_pin <= 'Z' when desired_output = '1' and output_pin = '1' else > desired_output. > > But the second output_pin should be the actual external signal after the > output buffer not the internal one... > may be I will have to instanciate low level gates. (OBUFT...) > > Marc Battyani > > Sorry, your right. My assumption that switching off the driver is considerably slower than the traveling of the signal to the pin was very, very wrong. However, I lerned something new. This should be the sense of this newsgroup. Best regards -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25943
Daniel Nilsson wrote:
> I mean a schematic that tells you how to build the design using ordinary 74
> logic. I am a student, and fpga's cost me very much, so if I only do a small
> design it makes more sense for me to put it in discrete logic. I also wonder
> if anyone has knowledge of putting part of the logic outside the fpga to
> reduce fpga size? (counters, shift-registers)
Daniel,
A small FPGA (5000 equivalent gates) circuit can be done for about $15 (US)
in parts in single piece quantities. This assumes a Xilinx XCS05XL and a serial
configuration prom. You do however need a prom programmer. I happen to like
the Atmel reprogrammable proms. Atmel even has a simple prom programmer circuit
on thier web site. You would be wasting money even in small quantities to pull
gates out from the FPGA unless there is some other reason than to cut gate
count.
Article: 25944Hello, Does anyone know how to stop maxplus2 version 95 optimising nets away. With older versions I think there was a preserve nets option, but this version doesn't appear to have it. Thanks in advance. -- LeeArticle: 25945
Does anybody know if there is an alternative brand of CPLD's for the Altera EPM3256ATC144, i.e. something with 256 macro- cells or more, 144 pin TQFP package, same pinout as the Altera device ? Any info greatly appreciated. John Kortink Windfall Engineering Email : kortink@inter.nl.net Homepage : http://www.inter.nl.net/users/J.Kortink ViewFinder, the high performance graphics card for RISC PC's : http://web.inter.NL.net/users/J.Kortink/viewfinder.htmArticle: 25946
Daniel Nilsson wrote: > > Is there any possibility to extract an "ordinary" logic circuit schematic > from a hdl file? Synplify does this, though as far as I know, you can't then export that schematic into a standard package. But you can look at it. Or you can synthesise your hdl to EDIF, and generate a schematic from that. Dunno if I'd call it 'ordinary' though. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 25947
John Kortink wrote: > > Does anybody know if there is an alternative brand of CPLD's > for the Altera EPM3256ATC144, i.e. something with 256 macro- > cells or more, 144 pin TQFP package, same pinout as the Altera > device ? The EPM7512AE comes in a 144 pin TQFP. Other vendors have clones of the smaller Altera parts. You may have to go to a RAM-based device to get this density at lower cost. -- mike.treseler@flukenetworks.com or -- tres@tc.fluke.comArticle: 25948
I am not familiar with ABEL, so I can't tell you how to optimize the code. But I can tell you that the optimal circuit is to use a set of 4 input AND gates followed by an 8 input OR gate. This is what you will see if you look in a data book for TTL logic (if you can find one :). If ABEL works like the old PALASM did, you can just specify the 1's conditions and leave the rest to default to output 0's. To do that you would remove all the conditions in your table that output a zero. In any event, I don't think what you have is bad. What does it give you as a result? Alan Horton wrote: > > I am having a problem with using "dont cares" in a truth table for an 8-1 > multiplexer. My attempt is shown below. There must be a way of optimising > the truth table using "don't cares" but I can't seem to find out how to do > it. Can anyone help? > > The truth table I'm trying to reproduce looks like this. > C2, C1, C0, A7, A6, A5, A4, A3, A2, A1, A0 D > 0 0 0 x x x x x x x 0 0 > 0 0 0 x x x x x x x 1 1 > 0 0 1 x x x x x x 0 x 0 > 0 0 1 x x x x x x 1 x 1 > 0 1 0 x x x x x 0 x x 0 > 0 1 0 x x x x x 1 x x 1 > etc....... > > My attempt > > A7..A0 PIN; > A = [A7..A0]; > C2..C0 PIN; > C = [C2..C0]; > D PIN istype 'dc,com'; > > Equations > > TRUTH_TABLE > ([C,A] -> [D]) > [0,0] -> [0]; > [0,1] -> [1]; > [1,0] -> [0]; > [1,2] -> [1]; > [2,0] -> [0]; > [2,4] -> [1]; > [3,0] -> [0]; > [3,8] -> [1]; > [4,0] -> [0]; > [4,16] -> [1]; > [5,0] -> [0]; > [5,32] -> [1]; > [6,0] -> [0]; > [6,64] -> [1]; > [7,0] -> [0]; > [7,128] -> [1]; > > end Mux40 -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25949
Use the WYSIWG option. See the help menu. -- Bob Elkind eteam@aracnet.com Lee Weston wrote: > > Hello, > > Does anyone know how to stop maxplus2 version 95 optimising nets away. > With older versions I think there was a preserve nets option, but this > version doesn't appear to have it. > > Thanks in advance. > > -- > Lee
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