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Dear System-Level Chip advocate: If System-Level ICs are important to you, so is this meeting. The annual VSI Alliance Member Meeting in the US will be held in Silicon Valley on October 25. The keynote speech will be given by Dr. Wally Rhines, president of Mentor Graphics. There will be important and useful presentations from several major companies on how they are handling the SoC design and development challenges and how they are using VSIA specifications and standards in that process. For more information and the registration form, check the VSIA website at www.vsi.org. · Admission if free to members and non-members. · The meeting is at the Santa Clara Marriott Hotel, from 9 till 5. · Continental breakfast and registration from 7:30am. · Lunch served and a cocktail reception at 5pm. · There will be a VSIA orientation meeting at 8am for those not familiar with the Alliance, what all it's all about and how it works. Hope to see you there: Stan Baker VSI Alliance The VSI Alliance is a non-profit consortium of over 160 companies worldwide.Article: 25726
I'm not sure of the ramifications of 1, but 2 is the item that I don't understand. I believe the data you sent me indicated that in the Virtex there was a sharp current peak as the power voltage crosses the 0.8 volt area. But this current drops considerably as the voltage rises further. A) Are you saying that in the 4K family, this high current continues indefinitely until the chip completes the internal clearing of the configuration ram? B) Does asserting the PRGM- line also cause the high current draw until released? I don't normally assert the the INIT- signal at power up, but I often do assert the PRGM- signal. I need to know if this causes the same high current draw. Austin Lesea wrote: > > Rick, > > OK. You are welcome. Let me see if I can help you with this. > > For 4K: > > 1* discharge to less than ~150 mv before staring up again as last configuration > doesn't leak away completely and higher start up current results, > > 2* don't hold off clean-out/configuration with INIT as power on current remains until > you let go (unless that is OK with you and your power supply), > > 3* keep power rising (or at least flat) through the POR region, > > 4* >2ms and <50ms power on ramp up time recommended (within the data sheet power on > ramp up time and current capacity spec). > > 3&4 apply to Virtex, but not 1&2. > > Austin > > rickman wrote: > > > This is very useful information, thanks. > > > > I was not asking about the internal design of the two families of parts, > > although that would be interesting. I was asking about the functional > > difference. In your earlier posts you seem to indicate that there is a > > large current draw under a wider range of conditions with the 4K series > > than with the Virtex series. This is what I am trying to understand. > > > > > > > In 4K, holding INIT and preventing clean out does not make the device > > > > > HOT -- it may be that the 4K device is in contention from the Vcc not > > > > > going down below a few hundred millivolts, and then the Vcc returns, > > > > > and the 4K device is in a partially configured state, and drawing > > > > > current. So the device is already HOT and getting hotter, and INIT > > > > > prevents the clean out. > > > > > > > > > ********************* This bit right here > > ******************************** > > > > > Again, Virtex, Virtex E, Spartan2 do not have this behavior. The > > ********************* This bit right here > > ******************************** > > > > This is the statement I am asking you to clarify. Tell us about the > > difference noted above. I do not understand exactly what is different > > about the behaviour of the two families of devices. I am not asking you > > to explain the internal proprietary design issues. > > > > I do not agree that there is such a significant difference in the > > markets for the Virtex and the Spartan parts. I don't know how you are > > targeting your parts, but I can tell you that the users only look at > > capability (size) and price. I have no reason to care about what the > > intended market for a family of parts is. So with the considerable > > overlap in size of the two families (50, 100 and 200K gates), I expect > > that I will be using either family depending on my specific needs for > > expandability and size. > > > > So I don't agree that you can just say, that there will only be a small > > number of people using the Virtex parts in designs with current limited > > power supplies... except for the fact that you won't support them when > > used that way. > > > > Austin Lesea wrote: > > > > > > Rick, > > > > > > The increased current draw occurs at about 0.6 to 0.8 Vdc in Virtex. > > > > > > It occurs at the POR trip point in 4K (see respective data sheets). > > > > > > The differences between the virtex and 4k power up cleanout circuits are not > > > something I can discuss. > > > > > > While a supply is ramping up, it is driving the filter capacitors to the > > > intended output voltage, and the supply is often current limited (can't supply > > > any more current than it already is) while doing this, and hence the power ramp > > > up time is constrained (i.e. not instant, by I=C*dV/dt). > > > > > > If I had 2000uF of capacitance, and it rises in 2 ms (typical of a really fast > > > power ramp), that is 2.5V into 2,000uF in 2 ms, or I=2.5A. > > > > > > If I had 2000uF of capacitance, and the device suddenly requires 500 mA, you can > > > see what the dV/dt would be. But, nothing is sudden, and the voltage and > > > current interact. > > > > > > Even hot swap PCI has a rise time due to the resistance and inductance of the > > > pcb traces to the bypass capacitors of usually no faster than 1 ms. > > > > > > You can think of Virtex as being a really big non-linear capacitor. It actually > > > draws less current as the ramp slows down. This makes this a chicken and egg > > > problem: how does the power ramp? Is the part connected? they affect one > > > another. We test to make sure that if a power supply could supply no more than > > > 500 mA (in Virtex C grade), the device would be ready for configuration and the > > > vccint is at the power supply vccint (not sagging, or collapsed). The Virtex > > > part may put a flat spot in the ramp up, but that is just fine (we just don't > > > like to see it foldback, and dip which is the case with a power supply that is > > > arranged for a foldback response -- datasheet recommends against this kind of > > > behavior!). > > > > > > We have noted that if you could only supply 100 mA, the ramp might be really > > > long (~100 ms), but the part would clean out, and start to configure. > > > > > > Virtex is not going to be characterized for low current startup, as most designs > > > require more than 500 mA while operating (no market push to do this). > > > > > > Spartan2 on the other hand will be considered (is now being characterized) for > > > lower current startup as the markets are different for the two parts (there is a > > > push to do this). > > > > > > I hope this answers the first question, and I hope you understand that I can not > > > discuss the internal circuit design and operation here required to answer you > > > second question, > > > > -- > > > > Rick Collins > > > > rick.collins@XYarius.com > > > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design > > > > Arius > > 4 King Ave > > Frederick, MD 21701-3110 > > 301-682-7772 Voice > > 301-682-7666 FAX > > > > Internet URL http://www.arius.com -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25727
If the parallel inputs come from a sychronous design, I can't think of a case off hand where you wouldn't have some type of data valid indication, even if it is the sample clock. In the simple case of the data changing on each sample clock, you can connect the toggle FF to the sample clock too to generate your flag to go across the domains. I suppose you could have a case where you don't have access to the sample clock, in which case about all you can do is oversample the input by a fair amount, look for changes on each input and if you see one on any input use that to resync an internally generated sample counter. This also works for a parallel word of async inputs like you might get from a keypad. BTW, you can use the carry chains in a non-conventional manner in these last two cases to generate a 'something's changed since last clock' signal in very little space. For the detection, you don't care about the accuracy of the data, just that something has changed so that you can restart a count off to when you sample the input. Nial Stewart wrote: > > Ray Andraka wrote: > > > > The best way I've found for general purpose parallel is create one extra signal > > with a toggle flip flop toggled by writing valid data to a register. On the > > second clock side, you have a wrtie pulse generator that is triggered when it > > senses a change in the level on the synchronized flag, and then that is used to > > transfer the data from the common holding register across the clock domain > > boundary. It can be pipelined a little, but you do generally still need 2 or 3 > > clocks on the recieving side per clock on the transmit side. You can put > > parallel circuits to maintain the data rate. > > > > Ray, > > I thought Simon was describing a situation where you have > parallel data being generated asynchronously with no other timing or > flag info, and thought he had some clever way of ensuring you'd > captured the data correctly. > > I realise that each case needs to be examined and a properly 'safe' > interface > designed where required. > > Nial. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 25728
I hate to sound dense, but disabling interrupts during interrupt processing is not new, every x86 processor has that. They also still allow other interrupts such as NMI. Can you explain a little more about what ARM is doing that is patented? I took a minute and searched the IBM patent site. Here is the summary I found... """"""""""""""""""""""""""""""""""""""""""""""""""""""""" A CPU architecture is provided having a user mode (User32), a plurality of exception modes (IRQ32 etc) and a system mode (System) entered via one of the exception modes. The system mode re-uses the same set of registers (16) as the user mode and yet has access to a set of privileged resources compared to the standard resources of the user mode. Interrupt of the same type are disabled when the system is already in that exception mode, but are re-enabled when the system is moved into the system mode. Branch instructions may be used in the user and system modes, but not the exception modes. """"""""""""""""""""""""""""""""""""""""""""""""""""""""" To me this sounds like a very unique way of dealing with the issues of interrupt context switching. Although I am not sure I completely understand what it is saying, is does not sound like something totaly obvious. One way to get around the patent is to change any of the features mentioned above. Since no one will be coding branch instruction in exception handling code, you can leave them enabled and you will no longer be in violation of the patent! Ulf Samuelsson wrote: > > -- > Best regards, > ulf at atmel dot com > The contents of this message is intended to be my private opinion and > may or may not be shared by my employer Atmel Sweden > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:39C37C92.FB919779@yahoo.com... > > Ulf Samuelsson wrote: > > > The it follows logically that the context must be protected from > > > another interrupt until the CPU has saved the current context. > > > Yet they patent it. Ridiculous..... > > > > I would like to understand this. You can't patent a concept, how did > > they reduce this to practice? If they have no hardware to save context, > > what did they patent, the software to save context, disabling interrupts > > or what? > They have hardware resources for storing the context, but the > processor does not no it automatically in a reentrant way. > I.E: Pushing return address on a stack while incrementing the stackpointer. > Instead the ARM stores the return address in an internal register which > is common for all interrupts. > > It this was the only feature you have a problem. > Guess what happens if you get two interrupts? > The second interrupt overwrites the internal register. > So they disable the interrupt. > The core of the patent is that they disable "interrupts" while allowing > other exceptions to happen. (Page Fault, Fast Interrupt (which uses > a separate register) > > In my opinion , as long as you decide to do interrupt handling in S/W > (which is prior art) and you want to have an exception register > and MMU , the rest is obvious. > Patent is 5,701,493 > > > > > > In the light of the ARM threats to the "www.open-cores.com" activity > it > > > would be interesting to see how easy the ARM patents would fall down in > > > court...." > > > > I have not heard of the conflict with ARM. Is there a web page > > discussing it? > I saw that www.open-cores.com got a threatening letter when > they published their FPGA core implementation. -> www.altavist.com ? > ARM has sued some U.S. company that cloned the core. > They claim they do not violate the patents. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25729
Alun wrote: > > "Michael Rhotert" <mrhotert@t-online.de> wrote in message > news:8q2pmd$hcq$11$1@news.t-online.com... > > > We are considering moving the fanout functionality inside the > > > Virtex, to save on external parts count. The issue I have a > > > question about is the following. When one sets up the constraints > > > for the P&R tool (Alliance in this case), is there a way of doing > > > this so that one can specify the **maximum skew** between any 2 > > > clock outputs? In other words, is it possible to fan out a clock > > > inside the Virtex for external use and simultaneously approximate > > > (dare I say guarantee?) the low skew among all clock outputs that > > > is characteristic of an external buffer? > > > > Maybe you can use the 2x output of the DLL, divide it by 2 in a CLB, and > > feed the divided signal to several IOBs with output registers, clocked by > > the 2x-clock. > > Using this approach, you get multiple low skew signals with the wanted > > frequency. > > > > Michael > > This is the best approach but the *huge* snag (depending on what you want to > do) is that you can't use external feedback to get the external clocks to > have zero skew compared to the DLL input clock. The external FB clock must > be 2x if you use the DLL 2x output. > Read XAPP132 (Virtex DLL app note) *very* carefully. There are loads of > rules and a new rule appears every few months. > > There is an article on how to get low skew with non-clocked outputs which I > can't lay my hands on right now. I got it from the Xilinx web site and > covers the use of MAXSKEW (Xilinx P&R) and placement out outputs for low > skew. Place the outputs near each other along the top or bottom of the > device (ie by the long lines) and constrain the skew to whatever you need. > The article quoted an example result of 56ps with a constraint of 100ps (I > think), though don't bank on getting near this figure. > > Alun > Camdigital I don't know that you have understood the circuit being proposed. Or Maybe I didn't. But I think the clocks can be output by using the IOB FFs to divide a 2x clock from any source. The DLL can be used because it can generate the 2x clock. Or it could come from a 2x Xtal. But one of these outputs is fed back to the FPGA to use internally. This can be run through a second DLL to put the internal clock in phase with the external clock. This may work better than the external PLL chip since it only has a single source of error and jitter, the FPGA. Doing it the other way introduces two sources of error. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 25730
Does anyone in this newsgroup realistically think that they can do the
work below in 30-40 hours? Of course I would have to inquire to find out
the details in order to make an estimate of what is really required. But
just reading what this company wants, I see four main tasks: 1) design and
schematic capture of the board, 2) design and HDL/schematic capture of the
FPGA, 3) simulation of maybe the board and certainly the FPGA, and 4) lab
testing/debug. I personally do not think that I can do all of the above
tasks in 30-40 hours.
At least they have a detailed block diagram.
How about yous guys/gals? Can anyone do this work based on what's
written below?
-Simon Ramirez, Consultant
-Synchronous Design, Inc.
"Walt" <walt_white@southwestsoftware.com> wrote in message
news:v98x5.31686$I6.182833@news1.rdc1.az.home.com...
> Hello,
>
> We are looking for a freelance designer who can help us develop a
> daughterboard module. This work will involve the schematic capture and
> layout of the PCB in (preferably in Protel), and the programming of the
> SpartonII FPGA. The hardware design will be based on a detailed block
> diagram of the board that we provide, along with some key part numbers and
> other needed information. The board includes some A/Ds, D/As and a DDS.
> The work should take between 30 to 40 hrs and can be done at your
location.
>
> The project deliverables will be Protel design files, the FPGA design
files,
> and any documentation used to create the design. All rights and claims to
> any work on this project at all times is unequivocally the property and
> intellectual property in origin and by any extension with all rights and
> privileges reserved to Southwest Software & Systems LLC (3S).
>
> Payment for the work will be a flat fee of $2000.00 plus a royalty of 5.0%
> of the sale price for each board, and the boards will sell about $675ea
and
> volume is expected to be a few hundred (For example, assuming a 200 board
> volume, the total payment for the hardware design would be: $2000.00 +
0.05
> x $675.00/Board x 200Boards = $8,750). Additionally, there could be
similar
> follow-up designs.
>
> If you are interested and qualified to do this work, please contact me as
> soon as possible, we are ready to begin immediately.
>
> Regards,
>
> Walt White
> Southwest Software & Systems LLC
> www.southwestsoftware.com
>
>
>
>
Article: 25731tangozebra@bigfoot.com (tangozebra) writes: > This is a more general legal question - but lets say you're given an NDA > at an interview, and you write "not signed" as illegibly as possible on > the signature line and hand it back as if you signed it. What legal > ramifications does this have? My question is: why bother? If you are interviewing with a company with the goal of being offered employment, then it's certainly not in your best interest to dick around with them based on their NDA form. If you believe that a given NDA form isn't worth your signature, then simply don't sign it. Talk it over with the interviewer. Thank them for their time and leave. Being honest and open about your concerns will pay far more dividends in the long run than trying to find ways to trick the system, in my experience. I can't think of a situation whereby pretending to sign a form is going to be in your best interest. Kelly -- Kelly Hall Captus Networks We're hiring software professionals: careers@captusnetworks.comArticle: 25732
[Slightly sorry for beating a dead horse.] If the pintouts were available in raw text, it would be simple to run diff on the two canidates and see the differences. -- These are my opinions, not necessarily my employers. I hate spam.Article: 25733
If I was going to use a corner of a Virtex for a clock generator, I'd try real hard to use the FFs in the IOBs. Obviously, I'd try to place them close to eachother and I'd clock them all off the same clock. But now that I think about it, I haven't seen any specs on skew between pins on a setup like that. Have I missed it and/or where would I look? -- These are my opinions, not necessarily my employers. I hate spam.Article: 25734
On Mon, 18 Sep 2000 17:52:45 GMT, tangozebra@bigfoot.com (tangozebra) wrote: >This is a more general legal question - but lets say you're given an NDA >at an interview, and you write "not signed" as illegibly as possible on >the signature line and hand it back as if you signed it. What legal >ramifications does this have? I would guess that this depends on what they can show as to your intents in doing so. JonArticle: 25735
"Ulf Samuelsson" <ulf@atmel.spammenot.com> wrote in message
news:m4ux5.11397$Fl2.93156@nntpserver.swip.net...
>
> <default@user.com> wrote in message news:39C2F1C4.6D15B439@user.com...
> > Hello, a few months back I purchased an XS40-010XL+ from XESS
> > corporation (http://www.xess.com.) The board is populated with an
> > 8051uC and Xilinx XC4010XL ("10k system gates") FPGA, with a 128k X 8
> > async SRAM chip. The board has its own VGA connector (you are
> > responsible for implementing the display controller circuit), a PS/2
> > keyboard connector, and standard connector headers giving access to all
> > 84 I/O pins of the FPGA.
> >
> > Initially, the board was great, but I've since discovered 10k gates
> > isn't a whole lot at all! So now I'm looking to move up to a larger
> > FPGA board.
>
> The Atmel STK40 has 2 x size (AT40K20) and is about $150-200.
> Check at www.kanda-systems.com
> It has a socket for an AVR (8515) and I think you may be able to put an
8051
> there.
> No external memory though.
>
> If you wait for a month or two, you may be able to get your hands on the
> brand new
> FPSLIC demoboard.
> I think it will be about the same price and has an AVR integrated w 36 kB
of
> SRAM.
I would definitly recommed to wait the FLPSIC board. I got the AT40K20
and I am not very happy with it.
It does not even have enough free I/Os to connect proper external sram.
(like 16x64k) Instead they wasted ~50 I/O pins on a six digit numerical
LCD. An alphanumeric 16x1 LCD with controller would have probably been just
a few $ more, which would have freed many I/O pins, had given more output
capabilites and the amount of required control logic is probably all over
all
comparable to the "pure" LCD.
And: No VGA, no S/H for the fast A/D, and various other quirks which
are showstoppers in some situations.. (like the undocumented programming
jumper .. . .)
The pretty expensive book that comes with the kit also isnt that
satisfying.... (printing the appnotes byself is cheaper)
Oh yes, and the downloading software crashes w2k on exit....
ok, enough so far. I hope Kanda did a better job with the FPLSIC
devkit. I will try to get it as soon as it is available. But I have seen
a price quote of ~$500 on atmel page ??!
Article: 25736> I would definitly recommed to wait for the FLPSIC board. I got the AT40K20 > and I am not very happy with it. Of course I am speaking about the STK40, not the FPGA byself :)Article: 25737
I agree that 30-40 hours is a little ridiculous. Especially since it is to include the layout, which you didn't include in your list. -- Greg xxxgread@voicenet.com (Remove the 'xxx' to send Email) S. Ramirez wrote in message ... > Does anyone in this newsgroup realistically think that they can do the >work below in 30-40 hours? Of course I would have to inquire to find out >the details in order to make an estimate of what is really required. But >just reading what this company wants, I see four main tasks: 1) design and >schematic capture of the board, 2) design and HDL/schematic capture of the >FPGA, 3) simulation of maybe the board and certainly the FPGA, and 4) lab >testing/debug. I personally do not think that I can do all of the above >tasks in 30-40 hours. > At least they have a detailed block diagram. > How about yous guys/gals? Can anyone do this work based on what's >written below? >-Simon Ramirez, Consultant >-Synchronous Design, Inc. > > > >"Walt" <walt_white@southwestsoftware.com> wrote in message >news:v98x5.31686$I6.182833@news1.rdc1.az.home.com... >> Hello, >> >> We are looking for a freelance designer who can help us develop a >> daughterboard module. This work will involve the schematic capture and >> layout of the PCB in (preferably in Protel), and the programming of the >> SpartonII FPGA. The hardware design will be based on a detailed block >> diagram of the board that we provide, along with some key part numbers and >> other needed information. The board includes some A/Ds, D/As and a DDS. >> The work should take between 30 to 40 hrs and can be done at your >location. >> >> The project deliverables will be Protel design files, the FPGA design >files, >> and any documentation used to create the design. All rights and claims to >> any work on this project at all times is unequivocally the property and >> intellectual property in origin and by any extension with all rights and >> privileges reserved to Southwest Software & Systems LLC (3S). >> >> Payment for the work will be a flat fee of $2000.00 plus a royalty of 5.0% >> of the sale price for each board, and the boards will sell about $675ea >and >> volume is expected to be a few hundred (For example, assuming a 200 board >> volume, the total payment for the hardware design would be: $2000.00 + >0.05 >> x $675.00/Board x 200Boards = $8,750). Additionally, there could be >similar >> follow-up designs. >> >> If you are interested and qualified to do this work, please contact me as >> soon as possible, we are ready to begin immediately. >> >> Regards, >> >> Walt White >> Southwest Software & Systems LLC >> www.southwestsoftware.com >> >> >> >> > >Article: 25738
Gary, It is trivial, really. Go to the power estimator page, and fill out the estimator with as many educated guesses as you can for a V150. Be really over conservative (more IO's, more CLB's, higher percentage of switching, etc). Look at how much current is predicted. http://www.xilinx.com/cgi-bin/powerweb.pl Make sure you are not exceeding the power dissipation for the device. The XC2S150 will be less current that the 150 due to the process improvements. We will have more data on that it the future. The estimator is based on actual lab measurments of designs. It is a vast improvement over any power estimation for FPGAs I have seen before. We correlate its results against a number of customer reference designs, Austin Gary Watson wrote: > I know it's difficult to predict the power requirements of Xilinx parts, but > what's a safe 2.5V regulator to use for the internal supply of a XC2S150? > The data sheet is most unhelpful in figuring this out. Since I plan to roll > out this product in phases over the next year, I can't say what all my > internal logic might be doing down the road, so I'm happy to over-spec the > regulator to a reasonable degree. > > By the way, I'm getting quoted over 10 UK pounds ($14) for the config prom > for this puppy (XC18V01S20C). Is there a cheaper way to do this? This prom > increases the cost of using a Spartan II by 50%! > > -- > > Gary Watson > gary2@nexsan.com > Nexsan Technologies Ltd. > Derby DE21 7BF ENGLAND > http://www.nexsan.comArticle: 25739
Right on Simon ! Looks far too tight to me. What about the budget for Photo plotting, PCB fab, assembly, parts, time to coordinate all this ? Not to mention one simple mistake in the PCB schematic that would require a second turn; not uncommon. Who eats it ? - New photo plot + new PCB + some new parts + time. Will they want the design squeezed into an FPGA which takes time and skill ? What about the restriction to Protel; shutting out many other qualified engineers who are expert on other tools. I am small potatoes myself and I work on jobs that will bring in $20K. I visited this guy's web page and they looked like a going concern. So why the nickel & dime approach ? It comes across as amateurish. They are from never-never land. Whoever takes this job, come and see me. I would love to hire (read 'exploit' wink wink ) you. DanArticle: 25740
eomArticle: 25741
Greg,
Thanks for pointing out my serious omission.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Gregory C. Read" <xxxgread@voicenet.com> wrote in message
news:ITwx5.159$du2.8575@news3.voicenet.com...
> I agree that 30-40 hours is a little ridiculous. Especially since it is
to
> include the layout, which you didn't include in your list.
>
> --
> Greg
> xxxgread@voicenet.com
> (Remove the 'xxx' to send Email)
>
>
> S. Ramirez wrote in message ...
> > Does anyone in this newsgroup realistically think that they can do
the
> >work below in 30-40 hours? Of course I would have to inquire to find out
> >the details in order to make an estimate of what is really required. But
> >just reading what this company wants, I see four main tasks: 1) design
and
> >schematic capture of the board, 2) design and HDL/schematic capture of
the
> >FPGA, 3) simulation of maybe the board and certainly the FPGA, and 4) lab
> >testing/debug. I personally do not think that I can do all of the above
> >tasks in 30-40 hours.
> > At least they have a detailed block diagram.
> > How about yous guys/gals? Can anyone do this work based on what's
> >written below?
> >-Simon Ramirez, Consultant
> >-Synchronous Design, Inc.
> >
> >
> >
> >"Walt" <walt_white@southwestsoftware.com> wrote in message
> >news:v98x5.31686$I6.182833@news1.rdc1.az.home.com...
> >> Hello,
> >>
> >> We are looking for a freelance designer who can help us develop a
> >> daughterboard module. This work will involve the schematic capture and
> >> layout of the PCB in (preferably in Protel), and the programming of the
> >> SpartonII FPGA. The hardware design will be based on a detailed block
> >> diagram of the board that we provide, along with some key part numbers
> and
> >> other needed information. The board includes some A/Ds, D/As and a
DDS.
> >> The work should take between 30 to 40 hrs and can be done at your
> >location.
> >>
> >> The project deliverables will be Protel design files, the FPGA design
> >files,
> >> and any documentation used to create the design. All rights and claims
> to
> >> any work on this project at all times is unequivocally the property and
> >> intellectual property in origin and by any extension with all rights
and
> >> privileges reserved to Southwest Software & Systems LLC (3S).
> >>
> >> Payment for the work will be a flat fee of $2000.00 plus a royalty of
> 5.0%
> >> of the sale price for each board, and the boards will sell about $675ea
> >and
> >> volume is expected to be a few hundred (For example, assuming a 200
board
> >> volume, the total payment for the hardware design would be: $2000.00 +
> >0.05
> >> x $675.00/Board x 200Boards = $8,750). Additionally, there could be
> >similar
> >> follow-up designs.
> >>
> >> If you are interested and qualified to do this work, please contact me
as
> >> soon as possible, we are ready to begin immediately.
> >>
> >> Regards,
> >>
> >> Walt White
> >> Southwest Software & Systems LLC
> >> www.southwestsoftware.com
> >>
> >>
> >>
> >>
> >
> >
>
>
>
Article: 25742Rick, Here is some NT4.0 SP6 from my set-up. I'm usung 3.1wp1.x Application version build+D-20+0 In article <39C5457B.EC72AFB3@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: > I am trying to get the Xilinx Web Pack up and running on my machine and > am having trouble. > > The first problem I had was the fact that the install did not seem to > handle properly the path in the shortcut as I put it under the "Program > files" directory and it needed quotes around it to be able to > incorporate the space in the path. my path is d:\Xilinx_CPLD\nt ... no help here because no embedded spaces > > The next problem I have is trying to access the help. Many of the items > in the help window cause errors like "Can not find or run the program or > file 'dkxilinx.hlp'". It also could not find a current version (or any > for that matter) of "hhcntl.ocx". When I invoke the 'Help on Technical Support' from the Start>>Programs>>Xilinx CPLD WebPACK I get a message that says "You need a newer version of HHCTRL.OCX to be able to read this file". > > When I try to bring up the online version of help, I get an error that > it can not open the site with a very long and complicated name > containing characters that are not legal in a URL such as the @ sign. > > I don't know what either of these files are, but I am beginning to think > that I can't run this software under Win95. Is that my problem? > > The real problem I am having is that when I try to create a new project, > I am not presented with the option of using a real part, but rather the > only option for device is "virtual device". I was able to compile a test program using an XCR3256XL TQ144 and download it to an Insight Coolrunner board, and the LCD display appeared to run as expected, so my set-up is not totally broken. Hope this helps, Bob > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25743
There ain't much info here as to what is in the FPGA, or even how big a device it is. The FPGA design and verification alone could take as much as 10X or more of his estimated 30-40hours. I think the board layout alone, given a complete and verified netlist could be more than the 30-40 hours (check with a layout house if you don't believe me). For the pricing, I am always leery of projected volumes, especially if such a large percentage of the income is to be based on it. If the company tanks, or he only manages to sell one or tow boards or if the project gets scrapped, the consultant/contractor is working for about $50/hr (assuming the hours are met), which is quite low (I don't think you can get warm bodies to fill seats on your location for that anymore, and if you did you'd spend more than the 40 hours just getting them up to speed) That said, the DDS function could easily be incorporated into the FPGA. "S. Ramirez" wrote: > > Does anyone in this newsgroup realistically think that they can do the > work below in 30-40 hours? Of course I would have to inquire to find out > the details in order to make an estimate of what is really required. But > just reading what this company wants, I see four main tasks: 1) design and > schematic capture of the board, 2) design and HDL/schematic capture of the > FPGA, 3) simulation of maybe the board and certainly the FPGA, and 4) lab > testing/debug. I personally do not think that I can do all of the above > tasks in 30-40 hours. > At least they have a detailed block diagram. > How about yous guys/gals? Can anyone do this work based on what's > written below? > -Simon Ramirez, Consultant > -Synchronous Design, Inc. > > "Walt" <walt_white@southwestsoftware.com> wrote in message > news:v98x5.31686$I6.182833@news1.rdc1.az.home.com... > > Hello, > > > > We are looking for a freelance designer who can help us develop a > > daughterboard module. This work will involve the schematic capture and > > layout of the PCB in (preferably in Protel), and the programming of the > > SpartonII FPGA. The hardware design will be based on a detailed block > > diagram of the board that we provide, along with some key part numbers and > > other needed information. The board includes some A/Ds, D/As and a DDS. > > The work should take between 30 to 40 hrs and can be done at your > location. > > > > The project deliverables will be Protel design files, the FPGA design > files, > > and any documentation used to create the design. All rights and claims to > > any work on this project at all times is unequivocally the property and > > intellectual property in origin and by any extension with all rights and > > privileges reserved to Southwest Software & Systems LLC (3S). > > > > Payment for the work will be a flat fee of $2000.00 plus a royalty of 5.0% > > of the sale price for each board, and the boards will sell about $675ea > and > > volume is expected to be a few hundred (For example, assuming a 200 board > > volume, the total payment for the hardware design would be: $2000.00 + > 0.05 > > x $675.00/Board x 200Boards = $8,750). Additionally, there could be > similar > > follow-up designs. > > > > If you are interested and qualified to do this work, please contact me as > > soon as possible, we are ready to begin immediately. > > > > Regards, > > > > Walt White > > Southwest Software & Systems LLC > > www.southwestsoftware.com > > > > > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com Sender: eric@ruckus.brouhaha.comArticle: 25744
rickman <spamgoeshere4@yahoo.com> writes: > Although this does not work with the new Xilinx approach of renting you > the software. They now say that your ownership of the software is > limited to one year. That is a tough one to work around. If you want to > get a new license number, you have to pay for support after the year is > up. Actually that's pretty easy to work around. You just need a TSR that slows down the real-time clock. I've seen those around somewhere, probably on Warez groups. I don't understand WHY Xilinx has gone to this stupid model. Wasn't it good enough that you had to pay for maintenance or upgrades if you wanted support for new parts? One more reason I don't use Xilinx parts...Article: 25745
rickman <spamgoeshere4@yahoo.com> writes: > To me this sounds like a very unique way of dealing with the issues of > interrupt context switching. Although I am not sure I completely > understand what it is saying, is does not sound like something totaly > obvious. Hmm, it sounds familiar to me. Maybe not all of the features together at the same time though. It doesn't strike me as "novel", and I can easily imagine people saying something like "yeah, we analyzed that when designing our XYZ processor, but decided it complicated the CPU too much". Ie, if things were done in software because it was more feasible for a long time, but then cpu design gets easier and cheaper, does migrating such things into hardware constitute a patentable idea?Article: 25746
hello, i want to programm a xilinx cpld and a fpga in a jtag chain. does anyone know, if i can use the jtag pins as general purpose pins after programming. i think there is a problem with the connection between fpga and xilinx. i have not made a test but maybe someone else ? :) arnd --------------------------------- Arnd Sluiter Center for Sensor Systems (ZESS) Paul-Bonatz-Str. 9-11 57068 Siegen Germany Fon: ++49271/ 740-2465 Fax.: ++49271/ 740-2336 e-mail: sluiter@zess.uni-siegen.de ---------------------------------Article: 25747
check out http://www.elca.de/prode.html Best Regards Ernst Zwingenberger Mikhail Matusov <matusov@ANNTIsquarepegSPPAMM.ca> schrieb in im Newsbeitrag: appx5.4617$gi1.96222@news.magma.ca... > Are there any available? > > -- > ============================ > Mikhail Matusov > Hardware Design Engineer > Square Peg Communications > Tel.: 1 (613) 271-0044 ext.231 > Fax: 1 (613) 271-3007 > http://www.squarepeg.ca > >Article: 25748
arnd, It depends what familiy you're using. For example, the spartan familiy of FPGA's does let you use the JTAG pins for other purposes after configuration is complete, while the Virtex/Spartan-II families do not. Also, just a reminder that programming an FPGA with JTAG does *not* save the configuration; it will need to be re-programmed the next time power is applied. -kent sluiter@zess.uni-siegen.de (Arnd Sluiter) wrote in <39c71523.4262969@news.uni-siegen.de>: >hello, > >i want to programm a xilinx cpld and a fpga in a jtag chain. does >anyone know, if i can use the jtag pins as general purpose pins >after programming. i think there is a problem with the connection >between fpga and xilinx. > >i have not made a test but maybe someone else ? :) > >arnd >--------------------------------- >Arnd Sluiter >Center for Sensor Systems (ZESS) >Paul-Bonatz-Str. 9-11 >57068 Siegen >Germany > >Fon: ++49271/ 740-2465 >Fax.: ++49271/ 740-2336 >e-mail: sluiter@zess.uni-siegen.de >--------------------------------- >Article: 25749
rickman wrote: > > I am trying to get the Xilinx Web Pack up and running on my machine and > am having trouble. > > The first problem I had was the fact that the install did not seem to > handle properly the path in the shortcut as I put it under the "Program > files" directory and it needed quotes around it to be able to > incorporate the space in the path. > > The next problem I have is trying to access the help. Many of the items > in the help window cause errors like "Can not find or run the program or > file 'dkxilinx.hlp'". It also could not find a current version (or any > for that matter) of "hhcntl.ocx". > Rick, The problems may still be related to your - very unorthodox :) - choice of install path for the Xilinx S/W. Even though the installer accepts a path with spaces in it, the S/W does not necessarily support it. I had that problem when installing the 3.1i S/W. I recommend that you check if the missing files are actually present on your system. If this is the case, an uninstall followed by a new install to the default path may do the trick. BTW, in my case, the uninstall was a bit difficult, because the uninstall info could not be found due to the spaces in the path... Tobias F. Garde ASIC Development Engineer Tellabs Denmark A/S
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