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Alan Horton wrote: > I am having a problem with using "dont cares" in a truth table for an 8-1 > multiplexer. My attempt is shown below. There must be a way of optimising > the truth table using "don't cares" but I can't seem to find out how to do > it. Can anyone help? > > The truth table I'm trying to reproduce looks like this. > C2, C1, C0, A7, A6, A5, A4, A3, A2, A1, A0 D > 0 0 0 x x x x x x x 0 0 > 0 0 0 x x x x x x x 1 1 > 0 0 1 x x x x x x 0 x 0 > 0 0 1 x x x x x x 1 x 1 > 0 1 0 x x x x x 0 x x 0 > 0 1 0 x x x x x 1 x x 1 > etc....... > > My attempt > > A7..A0 PIN; > A = [A7..A0]; > C2..C0 PIN; > C = [C2..C0]; > D PIN istype 'dc,com'; > > Equations > > TRUTH_TABLE > ([C,A] -> [D]) > [0,0] -> [0]; > [0,1] -> [1]; > [1,0] -> [0]; > [1,2] -> [1]; > [2,0] -> [0]; > [2,4] -> [1]; > [3,0] -> [0]; > [3,8] -> [1]; > [4,0] -> [0]; > [4,16] -> [1]; > [5,0] -> [0]; > [5,32] -> [1]; > [6,0] -> [0]; > [6,64] -> [1]; > [7,0] -> [0]; > [7,128] -> [1]; > > end Mux40 The problem is that each line of your table that outputs a 1 generates an 11 input and gate e.g. [7,128] -> [1] becomes c0 & c1 & c2 & a7 & !a6 & !a5 .... & !a0 whereas what you want, as rickman has pointed out, is a 4 input gate c0 & c1 & c2 & a7 The most compact way of describing it would probably be D = (C == 0) & A0 + (C == 1) & A1 + etc, etc; However now that Xilinx are giving away their XST synthesis tool for use with CPLDs why don't you consider moving to Verilog. The above mux could code as: wire D; wire [2:0] C; wire [7:0] A; assign D = A[C];Article: 25951
On Wed, 27 Sep 2000 02:44:03 -0700, "Martin.J Thompson" <Martin.J.Thompson@trw.com> wrote: >My understanding of these papers is that the worst case requirements (large numbers of nodes switching etc) define your target impedance. Since you don't know at what times these demands will occur, you then need to provide that impedance all the way up to the max switching rate of the modes in question. >Maybe I missed something, (or am thinking of a dofferent paper!) but that was how I felt things to work. > >There was a good discussion on this topic on the Signal integrity mailing list recently. Archives are also at >http://www.qsl.net/wb6tpu >so you may have already seen them - the subject was "Decoupling capacitors (again!)" I'm not on the mailing list, but I did have another look at this paper. The author gives an example of a board with 5 CMOS ASICs on it. One of them has an average power consumption of 4.3W, and runs at 5V/50MHz. The calculated decoupling capacitance is 57nF. This is so low that it should cause some alarm bells. The procedure he uses to arrive at 57nF is very simple, and I've repeated it below. 1) Power consumption is 4.3W @ 5V, so average current is 0.86A. 2) The chip runs at 50MHz, so the clock cycle time is 20ns. 3) The chip draws current on both clock edges. Clock edges are 10ns apart, and so 8.6nC are required on every clock edge. 4) This must be supplied by local decoupling caps, with a maximum Vdd droop spec of 3%. Since dV = dQ/C,and dV is allowed to be only 5V*3% = 0.15V, we get C = 8.6nC/0.15V = 57.3nF, to supply the 8.6nC. Only problem is, this isn't how chips work. Imagine that the same chip has a 50MHz clock, but most internal activity occurs on every 8th clock cycle. It could then require very little charge for 7 cycles, and then 60nC on the next 2 clock edges, rather than 8.6nC. This means that it requires 7 times as much decoupling in this case. However, it still has the same average power requirement. IO activity is likely to be even more sporadic than this. A 32-bit bus, charging 100pF through 3V, requires 9.6nC, which will - initially at least - have to come from the caps. If you average this requirement out over many cycles it might appear to be negligible, but in fact it has doubled the simplistic decoupling estimate. In short, designing to average powers is pretty much like designing to average propagation delays. Decoupling, at least in this context, is about instantaneous requirements, not time-averaged requirements. >Of course, none of this takes into account ground bounce/SSN problems! I'm not sure that SSN is really an issue here; you can still calculate the required decoupling knowing the instantaneous charge requirement. However, actually getting the required current through the pin and leadframe inductances without an unacceptable voltage swing is another matter. EvanArticle: 25952
--------------06595C9E5F51B39D3F11877D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Martin, The subject of bypass gets re-hashed on a fairly regular basis. This article is useful as it is accurate as far as it goes. In an FPGA, where we don't have a clue what you, the customer, are going to do, bypassing takes on a much more difficult task. One approach is to concern yourself with the determination of how much current is required at each possible frequency, and the resulting bypass reactance vs. frequency, and then design a series of capacitance networks (capacitors of differring values and types) to cover the reactance vs frequency desired. i.e. less than 2 ohms from 0 to 1 GHz. You are still guessing at the peak current with this method, as you note in your comments. The "switched capacitance approach" used by me and others is another solution. For example, if the amount of capacitance switched by the IO's is X pF, then if I want less than 4% dV/dt (~150mV noise), I need to have 25 times X pF to bypass that one IO. Still a guess as to the peak currents, but perhaps an overly conservative guess. Now IO's don't actually switch capacitance (the loads may be inductive, resistive, or capacitive due to the transmission line and its length on the PCB). As such, the switched C approach is an estimate of a worst case. Add up the residual C of the points driven, not including the t-lines (t-lines are NOT capacitors at the edge rate, nor the data rates). T-lines transform the impedance at one end to the other end. A capacitive load may look inductive if the length is 1/4 wave for the frequency dominant in the edge. This may still be a 10X over estimate, as package C includes the t-line of the package (again not a capacitor). Driving a bank of parallel connected IC's (RAM's) does look like a big C. The guesstimate for the core bypassing may be done similarly by solving P=CV^2F for the C switched by the core to consume the power P at the frequency F operating at the core voltage V. Again, some amount of capacitance is desired to keep the dV/dt externally under a dull roar, and values such as 25 to 1 are used (similar to the io's). The power estimator for Virtex and Virtex E can be used for "what if's" Often forgotten is that the die has capacitance itself in the structures (self-bypassed) for both the core and the IO's. So does the multi-layer laminate packaging. That is why a 0.1uF cap still works after all these years. The local capacitance is small, but highly effective at the edge rates of the logic or IO. It is the 'refilling' of this internal capacitance that the external capacitors must accomplish. If it seems that the bypassing is excessive, perhaps it is. Removal of the capacitors, one by one, until the noise floor increases, is a technique to evaluate how over or under the original calculations and assumptions were to the reality of the final assembly. I see more over-estimation, than under. As you well note, one can not forget the low frequency components of the data transistions. The reactance approach attempts to maintain an extremely low supply inductance from DC to Ghz. Depending on the data patterns, there may be low frequency large currents needed, and hence, large value capacitors required. These may be located anywhere on the board, so they are often not a concern. Simultaneous switching outputs are to be floor-planned because if all of the outputs of a bank all go from a 1 to a 0 on a a clock edge, you will most definitely collapse the on-chip Vcco! See the SSO guidelines which define the most outputs allowed in the best bypassing case. In our appnote 158 (re-write due to be released perhaps this week), we make a point of recommending a number of large capacitors precisely because we don't know what the frequency distribution is, and you probably are not sure either. Austin "Martin.J Thompson" wrote: > Hi Evan, > > >>http://www.qsl.net/wb6tpu/si_documents/docs.html > > > >Thanks for the link. The fourth paper in the list is "Decoupling > >capacitor calculations", and its one that I read a couple of years > >ago; I haven't read the others. > > > >However, without wishing to be offensive, I have to say that this > >paper is just plain wrong. The recommendations the author arrives at > >are way too low. The basic problem is that he's taking an *average* > >power consumption for his boards, and then deriving the charge > >required per clock cycle, and giving the capacitor size required to > >supply this charge. This completely ignores the fundamental reason for > >using capacitors to supply 'instantaneous' current to a device. There > >will be times when a device suddenly needs current because, for > >example, an unusually large number of internal nodes are charging, > >several outputs are switching simultaneously, an internal clock edge > >has just occurred, or whatever. These requirements are not necessarily > >directly related to the devices clock frequency and may, for example, > >occur 5ns after every 10th input clock, in a 2ns window. The point of > >having local reservoir capacitors is to supply these instaneous > >current requirements, which can't be supplied by the PSU since the > >main supply inductances don't allow charge to be supplied 'quickly'. > >Sure, you can average everything up and come up with a time-averaged > >requirement, but it doesn't help. You need to know what the worst-case > >instantaneous requirement is, and you have to calculate the required > >capacitor which will supply this requirement, with an acceptable > >voltage droop, and with a low enough inductance to allow it to be > >supplied while it's still useful. > > > >It would be interesting to hear from anyone else who's read this paper > >and has a view on it. > > My understanding of these papers is that the worst case requirements (large numbers of nodes switching etc) define your target impedance. Since you don't know at what times these demands will occur, you then need to provide that impedance all the way up to the max switching rate of the modes in question. > Maybe I missed something, (or am thinking of a dofferent paper!) but that was how I felt things to work. > > Of course, none of this takes into account ground bounce/SSN problems! > > There was a good discussion on this topic on the Signal integrity mailing list recently. Archives are also at > http://www.qsl.net/wb6tpu > so you may have already seen them - the subject was "Decoupling capacitors (again!)" > > Hope that helps, > > Martin > > > > >Evan > > TRW Automotive Advanced Product Development, > Stratford Road, Solihull, B90 4GW. UK > Tel: +44 (0)121-627-3569 > mailto:martin.j.thompson@trw.com > > Sent via Deja.com http://www.deja.com/ > Before you buy. --------------06595C9E5F51B39D3F11877D Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Martin, <p>The subject of bypass gets re-hashed on a fairly regular basis. This article is useful as it is accurate as far as it goes. <p>In an FPGA, where we don't have a clue what you, the customer, are going to do, bypassing takes on a much more difficult task. <p>One approach is to concern yourself with the determination of how much current is required at each possible frequency, and the resulting bypass reactance vs. frequency, and then design a series of capacitance networks (capacitors of differring values and types) to cover the reactance vs frequency desired. i.e. less than 2 ohms from 0 to 1 GHz. You are still guessing at the peak current with this method, as you note in your comments. <p>The "switched capacitance approach" used by me and others is another solution. For example, if the amount of capacitance switched by the IO's is X pF, then if I want less than 4% dV/dt (~150mV noise), I need to have 25 times X pF to bypass that one IO. Still a guess as to the peak currents, but perhaps an overly conservative guess. <p>Now IO's don't actually <b>switch capacitance</b> (the loads may be inductive, resistive, or capacitive due to the transmission line and its length on the PCB). As such, the switched C approach is an estimate of a worst case. Add up the residual C of the points driven, not including the t-lines (t-lines are NOT capacitors at the edge rate, nor the data rates). T-lines transform the impedance at one end to the other end. A capacitive load may look inductive if the length is 1/4 wave for the frequency dominant in the edge. <p>This may still be a 10X over estimate, as package C includes the t-line of the package (again not a capacitor). Driving a bank of parallel connected IC's (RAM's) <i>does</i> look like a big C. <p>The guesstimate for the core bypassing may be done similarly by solving P=CV^2F for the C switched by the core to consume the power P at the frequency F operating at the core voltage V. Again, some amount of capacitance is desired to keep the dV/dt externally under a dull roar, and values such as 25 to 1 are used (similar to the io's). <p>The power estimator for Virtex and Virtex E can be used for "what if's" <p>Often forgotten is that the die has capacitance itself in the structures (self-bypassed) for both the core and the IO's. So does the multi-layer laminate packaging. That is why a 0.1uF cap still works after all these years. The local capacitance is small, but highly effective at the edge rates of the logic or IO. It is the 'refilling' of this internal capacitance that the external capacitors must accomplish. <p>If it seems that the bypassing is excessive, perhaps it is. Removal of the capacitors, one by one, until the noise floor increases, is a technique to evaluate how over or under the original calculations and assumptions were to the reality of the final assembly. I see more over-estimation, than under. <p>As you well note, one can not forget the <b>low frequency components</b> of the data transistions. The reactance approach attempts to maintain an extremely low supply inductance from DC to Ghz. Depending on the data patterns, there may be low frequency large currents needed, and hence, large value capacitors required. These may be located anywhere on the board, so they are often not a concern. <p>Simultaneous switching outputs are to be floor-planned because if all of the outputs of a bank all go from a 1 to a 0 on a a clock edge, you will most definitely collapse the on-chip Vcco! See the SSO guidelines which define the most outputs allowed in the best bypassing case. <p>In our appnote 158 (re-write due to be released perhaps this week), we make a point of recommending a number of large capacitors precisely because we don't know what the frequency distribution is, and you probably are not sure either. <p>Austin <p>"Martin.J Thompson" wrote: <blockquote TYPE=CITE>Hi Evan, <p>>><a href="http://www.qsl.net/wb6tpu/si_documents/docs.html">http://www.qsl.net/wb6tpu/si_documents/docs.html</a> <br>> <br>>Thanks for the link. The fourth paper in the list is "Decoupling <br>>capacitor calculations", and its one that I read a couple of years <br>>ago; I haven't read the others. <br>> <br>>However, without wishing to be offensive, I have to say that this <br>>paper is just plain wrong. The recommendations the author arrives at <br>>are way too low. The basic problem is that he's taking an *average* <br>>power consumption for his boards, and then deriving the charge <br>>required per clock cycle, and giving the capacitor size required to <br>>supply this charge. This completely ignores the fundamental reason for <br>>using capacitors to supply 'instantaneous' current to a device. There <br>>will be times when a device suddenly needs current because, for <br>>example, an unusually large number of internal nodes are charging, <br>>several outputs are switching simultaneously, an internal clock edge <br>>has just occurred, or whatever. These requirements are not necessarily <br>>directly related to the devices clock frequency and may, for example, <br>>occur 5ns after every 10th input clock, in a 2ns window. The point of <br>>having local reservoir capacitors is to supply these instaneous <br>>current requirements, which can't be supplied by the PSU since the <br>>main supply inductances don't allow charge to be supplied 'quickly'. <br>>Sure, you can average everything up and come up with a time-averaged <br>>requirement, but it doesn't help. You need to know what the worst-case <br>>instantaneous requirement is, and you have to calculate the required <br>>capacitor which will supply this requirement, with an acceptable <br>>voltage droop, and with a low enough inductance to allow it to be <br>>supplied while it's still useful. <br>> <br>>It would be interesting to hear from anyone else who's read this paper <br>>and has a view on it. <p>My understanding of these papers is that the worst case requirements (large numbers of nodes switching etc) define your target impedance. Since you don't know at what times these demands will occur, you then need to provide that impedance all the way up to the max switching rate of the modes in question. <br>Maybe I missed something, (or am thinking of a dofferent paper!) but that was how I felt things to work. <p>Of course, none of this takes into account ground bounce/SSN problems! <p>There was a good discussion on this topic on the Signal integrity mailing list recently. Archives are also at <br><a href="http://www.qsl.net/wb6tpu">http://www.qsl.net/wb6tpu</a> <br>so you may have already seen them - the subject was "Decoupling capacitors (again!)" <p>Hope that helps, <p>Martin <p>> <br>>Evan <p>TRW Automotive Advanced Product Development, <br>Stratford Road, Solihull, B90 4GW. UK <br>Tel: +44 (0)121-627-3569 <br><a href="mailto:martin.j.thompson@trw.com">mailto:martin.j.thompson@trw.com</a> <p> Sent via Deja.com <a href="http://www.deja.com/">http://www.deja.com/</a> <br> Before you buy.</blockquote> </html> --------------06595C9E5F51B39D3F11877D--Article: 25953
"S. Ramirez" wrote: > > Andy, > Great and candid response! I just wish you had talked to me about FPGA > Express a couple of years ago!! I wish I'd known the bugs a couple of years ago. As for being candid, telling the vendors the truth, even if they can't handle it, is the thing to do. > To make Synplicity less expensive, order the Xilinx-only license. What's sorta funny is that the Synplicity rep just called to follow up on a request I'd made awhile ago. So I downloaded the newest version, and my demo license JUST arrived via e-mail. Now, to figure out the diff betwixt Synplify and Synplify Pro... any takers? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25954
eml@riverside-machines.com.NOSPAM wrote: > What do you all think? Anyone willing to help? Evan, A demo license for Synplify just arrived. Time for some comparisons. I'll let you know what I learn. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 25955
There was a file called rnotes_6.0.pdf that I got from Simplicity that highlighted the differences. HDL Analyst is standard FSM Viewer FSM Explorer for selected architectures Tcl Window Log Watch window Probe Point Extraction Text File Crossprobing Pipelining for selected architectures Multiple implementations New User Interface. You maybe able to search their site, and grab the rnotes file. - Bob In article <8qtpid$deq$1@noao.edu>, Andy Peters <"apeters <"@> n o a o [.] e d u> wrote: > "S. Ramirez" wrote: > > > > Andy, > > Great and candid response! I just wish you had talked to me about FPGA > > Express a couple of years ago!! > > I wish I'd known the bugs a couple of years ago. As for being candid, > telling the vendors the truth, even if they can't handle it, is the > thing to do. > > > To make Synplicity less expensive, order the Xilinx-only license. > > What's sorta funny is that the Synplicity rep just called to follow up > on a request I'd made awhile ago. So I downloaded the newest version, > and my demo license JUST arrived via e-mail. > > Now, to figure out the diff betwixt Synplify and Synplify Pro... any > takers? > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25956
Data and Clock arrive from external devices to the FPGA and propagate to a FF. Offset in before is the amount of time the data is valid at FF before the clock arrives to that FF, i.e. it take more time for clock to propagate to FF then for data. Yury -----Original Message----- From: kanglc@agilis.st.com.sg [SMTP:kanglc@agilis.st.com.sg] Sent: Tuesday, September 19, 2000 10:10 PM To: comp.arch.fpga@list.deja.com Subject: Re: timing constraints Message from the Deja.com forum: comp.arch.fpga Your subscription is set to individual email delivery This message was sent to yuryws@banet.net Deja.com: Best way to buy a PC http://www.deja.com/channels/channel.xp?CID=13031 > What excactly do the offset = in and offset = out mean. Do they mean > that a signal must be valid X ns BEFORE the clock signal arives, and > that a signal is Y seconds AFTER the clock has arived stable? This could be useful: http://support.xilinx.com/support/techsup/journals/timing/presentation/t imin g/noframe/index.htm Regards, LC _____________________________________________________________ Deja.com: Before you buy. http://www.deja.com/ * To modify or remove your subscription, go to http://www.deja.com/edit_sub.xp?group=comp.arch.fpga * Read this thread at http://www.deja.com/thread/%3C39c81cb6%40news.starhub.net.sg%3E Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25957
Hello, My current project requires the use of a fpga to achieve all the associated logic functionality. Simply put the peripherals will communicate via a bus internal to the fpga, therefore the fpga will contains busses and muxes, registers (may use fpga ram), and contain some complex random logic and sequencers. I have investigated both the Atmel AT40 and the Altera Flex 10K family. This has left me confused as their architectures seem quite different, yet both could ultimately do the job. Have I missed the point? My question is how to determine which family will be better suited to my particular application. Any comments welcome! thanks, Graham Sent via Deja.com http://www.deja.com/ Before you buy.Article: 25958
I'll soon be working on a Xilinx Virtex-300 prototyping board (I huge step up from my Xess XS40-010XL!) I know that Xilinx's Foundation Express 2.x/3.x uses a licensed version of Synopsys FPGA Expresss to handle HDL synthesis. I'm also aware that designers can optionally configure their own software tools for synthesis. For example, use Synplicity to do synthesis, then let Xilinx's place/route software deal with the resulting gate netlist. What advantages does a third-party (Synplicity or other) HDL synthesis tool offer over the 'stock' Xilinx FPGA-Express? I really don't have a need for optimal synthesis, as I'm using the FPGA board to simulate the functionality of ASIC design. (The final code is headed to a ASIC standard-cell process.) but still, just for my enlightenment...Article: 25959
how to verify the downloaded design in the xc 4003e device using the x-checker cable on the xilinx demonstration board. is it sufficient to connect the x-cheker cable to the J2 header connector onthe demo board to download/verify and debug along with setting the mode switches or some external settings are required?Article: 25960
Yury, Thanks this link is verry usefull, and states all info that i need. Thanks Richard Yury Wolf-Sonkin wrote: > Data and Clock arrive from external devices to the FPGA and propagate to a > FF. Offset in before is the amount of time the data is valid at FF before > the clock arrives to that FF, i.e. it take more time for clock to propagate > to FF then for data. > > Yury > -----Original Message----- > From: kanglc@agilis.st.com.sg [SMTP:kanglc@agilis.st.com.sg] > Sent: Tuesday, September 19, 2000 10:10 PM > To: comp.arch.fpga@list.deja.com > Subject: Re: timing constraints > > Message from the Deja.com forum: > comp.arch.fpga > Your subscription is set to individual email delivery > This message was sent to yuryws@banet.net > Deja.com: Best way to buy a PC > http://www.deja.com/channels/channel.xp?CID=13031 > > > What excactly do the offset = in and offset = out mean. Do they mean > > that a signal must be valid X ns BEFORE the clock signal arives, and > > that a signal is Y seconds AFTER the clock has arived stable? > > This could be useful: > http://support.xilinx.com/support/techsup/journals/timing/presentation/t > imin > g/noframe/index.htm > > Regards, > LC > > _____________________________________________________________ > Deja.com: Before you buy. > http://www.deja.com/ > * To modify or remove your subscription, go to > http://www.deja.com/edit_sub.xp?group=comp.arch.fpga > * Read this thread at > http://www.deja.com/thread/%3C39c81cb6%40news.starhub.net.sg%3E > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 25961
how to verify a downloaded design in the xc4003e device on the xilixn demo board using the x-checker cable Any external mode settings are required inspite of connecting the cable to the J2 header connector and setting the SW2 mode switches? external settings for verification and debugging on the demo board?Article: 25962
bob elkind wrote: > > Use the WYSIWG option. See the help menu. > > -- Bob Elkind eteam@aracnet.com > > Lee Weston wrote: > > > > Hello, > > > > Does anyone know how to stop maxplus2 version 95 optimising nets away. > > With older versions I think there was a preserve nets option, but this > > version doesn't appear to have it. > > > > Thanks in advance. > > > > -- > > Lee Tried this, doesn't appear to stop the optimisation. -- Lee Weston, Philips Semiconductors, CS-DM Southampton, SO15 0DJ, UK mailto:lee.weston@philips.com seri:weston@ukpsshp1 phone: +44 (0) 23 80316471 fax +44 (0) 23 80316303Article: 25963
Rick,
Thanks for your input. I have already produced my design with AND gates
and an 8 input OR and it works fine. As I'm only at the learning stage I
try to produce each design using schematic capture and HDL.
My result at present gives me D=1 and only goes to "0" when there is a
change in the control pattern. It then returns to "1" on the rising edge of
A0.
I tried eliminating the terms in my code where D=0 and the result is that D
goes to "1" at the correct time but only stays high for the period of A0.
I need to find a way to represent the "dont cares" in my truth table.
rickman wrote in message <39D21E2F.89BEBE0F@yahoo.com>...
>I am not familiar with ABEL, so I can't tell you how to optimize the
>code. But I can tell you that the optimal circuit is to use a set of 4
>input AND gates followed by an 8 input OR gate. This is what you will
>see if you look in a data book for TTL logic (if you can find one :).
>
>If ABEL works like the old PALASM did, you can just specify the 1's
>conditions and leave the rest to default to output 0's. To do that you
>would remove all the conditions in your table that output a zero. In any
>event, I don't think what you have is bad. What does it give you as a
>result?
Article: 25964Hi Daniel, I agree with Theron, small FPGAs are very cheep today. And they are still large enough to let you implement much more functionallity than you can hope to do with discrete logic. I'm also very doubtful about the success of redusing fpga size by putting counters etc outside the chip. Check out the really small and cheep circuits on Xilinx homepage! I'm not sure where you can order FPGA's in quantities of ONE, but speek to Dipcom who distribute Xilinx stuff here in Sweden! Good luck, /Johan ps Since you are a student - Let me know if you would be interested in doing your Master Thesis on something FPGA related! Theron Hicks wrote: > > Daniel Nilsson wrote: > > > I mean a schematic that tells you how to build the design using ordinary 74 > > logic. I am a student, and fpga's cost me very much, so if I only do a small > > design it makes more sense for me to put it in discrete logic. I also wonder > > if anyone has knowledge of putting part of the logic outside the fpga to > > reduce fpga size? (counters, shift-registers) > > Daniel, > A small FPGA (5000 equivalent gates) circuit can be done for about $15 (US) > in parts in single piece quantities. This assumes a Xilinx XCS05XL and a serial > configuration prom. You do however need a prom programmer. I happen to like > the Atmel reprogrammable proms. Atmel even has a simple prom programmer circuit > on thier web site. You would be wasting money even in small quantities to pull > gates out from the FPGA unless there is some other reason than to cut gate > count.Article: 25965
Hi Chen, I don't think you have provided enough info for someone in the newsgroup to solve your problem. You ought to try to simulate your design, concentrating on the problem you have. If you can't see any problem in RTL simulation, just take the same test bench and apply it to a back annotated netlist. Good luck, /Johan chsw wrote: > > Hello: Now, i am doing "16bits converting 64bits fifo" of four channels ,my application is to write a lot of data to a fifo first by polling ,and then read it from the fifo by polling, my design is: the input data is 16 bits width,and use four 16 bits latches and 2 bits counter,the data is sent into 64 bits fifo when counter==2'b11.And then i will transfer it at the top level,if i write and read only a certain fifo ,the data of being read is correct.However,when i switch channel,the reading first data is 0 from the switched channel.Obviously ,the "0" of 64 bits is excrescent,but the back data is correct,that is ,it reads a "0" more.the phenomena happens only switching channel. why?Article: 25966
I have this :
entity US1 is port (
...
DDSFSK : out std_logic;
...
); end US1;
and then
DDSFSK <= '1';
Seems easy for me, but FPGA Express gives me :
Error: Cannot isolate ports with direction 'INOUT' on net 'DDSFSK'.
(FPGA-DRCFIX-1)
If I put DDSFSK <= '0'; instead of DDSFSK <= '1'; it works.
Any clue ? I don't have any other use of this signal in the design.
Thanks
Marc Battyani
Article: 25967
Dear Netscape User,
What a generic name. Email me privately, and I'll discuss this with
you.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
"Netscape User" <your_email@here.net> wrote in message
news:39D2CF60.FDB7AEA6@here.net...
> I'll soon be working on a Xilinx Virtex-300 prototyping board (I huge
> step up from my Xess XS40-010XL!)
>
> I know that Xilinx's Foundation Express 2.x/3.x uses a licensed version
> of Synopsys FPGA Expresss to handle HDL synthesis. I'm also aware that
> designers can optionally configure their own software tools for
> synthesis. For example, use Synplicity to do synthesis, then let
> Xilinx's place/route software deal with the resulting gate netlist.
>
> What advantages does a third-party (Synplicity or other) HDL synthesis
> tool offer over the 'stock' Xilinx FPGA-Express? I really don't have a
> need for optimal synthesis, as I'm using the FPGA board to simulate the
> functionality of ASIC design. (The final code is headed to a ASIC
> standard-cell process.)
>
> but still, just for my enlightenment...
>
Article: 25968On Thu, 28 Sep 2000 09:35:56 +0100, "Alan Horton" <arh@jet.uk> wrote: >Rick, > Thanks for your input. I have already produced my design with AND gates >and an 8 input OR and it works fine. As I'm only at the learning stage I >try to produce each design using schematic capture and HDL. > >My result at present gives me D=1 and only goes to "0" when there is a >change in the control pattern. It then returns to "1" on the rising edge of >A0. > >I tried eliminating the terms in my code where D=0 and the result is that D >goes to "1" at the correct time but only stays high for the period of A0. > >I need to find a way to represent the "dont cares" in my truth table. I think the problem in your original code is that it doesn't correctly specify the don't cares. For instance, you've got: ([C,A] -> [D]) [0,0] -> [0]; [0,1] -> [1]; [1,0] -> [0]; [1,2] -> [1]; This makes [0,3], for example, a don't care, and the compiler is free to generate either a 1 or a 0 output, but it must actually generate a 1 output in this case. It's a few years since I've done any Abel, but I think your options are: 1) expand A and C into bits, and specify the DC's as you did at the top of your original post 2) I suspect your code might work as intended if you turn *off* don't cares (does @onset just map 1's?). You won't need the truth table lines that produce a 0 output, and you should just get your 8 product terms. BTW, I trust you won't be taking any advice to learn Verilog.. :) EvanArticle: 25969
Graham,
What you are doing is very typical for an FPGA to handle. I have done
what you are trying to do using both Altera 10K and Xilinx Virtex FPGAs.
The Xilinx Spartan FPGAs will do, also.
I had Atmel try to sell me on using their 6K family several years back.
This was the family previous to the AT40. So I gave them the VHDL code and
told them to place and route it in their part to see what kind of
performance it would bring. I was looking for 36 MHz minimum performance,
and I was achieving 42 MHz using the Xilinx 4KXL family. According to their
sales pitch, they could run circles around Xilinx.
But the proof is in the Putin, as they say in Russia. The local Atmel
FAE guy squirmed when I asked him to fit the design into his super-fast
Atmel FPGA. Actually, he squirmed, because he wasn't technically capable of
doing it himself. So he had to ask the Atmel factory to do it. They did,
and it came in at 27 MHz.
After several episodes of the above, I think Atmel finally realized
that the 6K family wasn't what it was cracked up to be. I was told that the
AT40 family fixed a lot of the problems that the 6K family had.
Nonetheless, I consider Atmel as following in the footsteps of the other
FPGA vendors.
So my advice is this. Given that there isn't much data on Atmel's AT40
family, why don't you ask the Atmel factory, or local FAE if he is up to it,
to fit your design into one of their devices? You could also ask the other
FPGA vendor to do the same and compare results. This sticking their feet to
the fire approach does seem to weed out the misfits (no pun intended).
Maybe someone in this newsgroup has extensive experience with the Atmel
AT40 family, too.
-Simon Ramirez, Consultant
Synchronous Design, Inc.
<graham_moss@my-deja.com> wrote in message
news:8qub1g$3me$1@nnrp1.deja.com...
> Hello,
> My current project requires the use of a fpga to achieve all the
> associated logic functionality. Simply put the peripherals will
> communicate via a bus internal to the fpga, therefore the fpga will
> contains busses and muxes, registers (may use fpga ram), and contain
> some complex random logic and sequencers.
>
> I have investigated both the Atmel AT40 and the Altera Flex 10K family.
>
> This has left me confused as their architectures seem quite different,
> yet both could ultimately do the job.
>
> Have I missed the point? My question is how to determine which family
> will be better suited to my particular application.
>
> Any comments welcome!
>
> thanks,
> Graham
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>
Article: 25970Hi Evan, I don't remember what the original message was about but I guess you are speeking about sharing experiences from using different synthesizers and backend tools for FPGA's... I am interested in such a project! I have been working along that line myself for a couple of years. I have a few designs that I know well - Over the years I have tried new tools/methods on these designs to get a feeling about which tools are the most promising. Since I have been working at Ericsson Network Core Products (who do a lot of hardware) I have had access to many tools, not only for FPGA's.... What I guess will be the troublesome part is to find good sources to use as bench marks. There are so many parameters you want to check. How efficient is the placer? To answer that you'll need a rather "realistic" design. The designs I have used are very realistic but they are all Ericsson property - I can not contribute with anything in the field of benchmarks :( Anyway, I'm interested in your mailinglist and will do my best to contribute to it. I'm starting up a company these days (this is my last week at ///!!!) and I can guarantee you that most of my employees will be able and interested to contribute in one way or another "Martin.J Thompson" wrote: > > Evan wrote: > > > >It occurs to me that it would be useful to pool the information that > >we do have, and to find a structured way of getting the information > >that we don't have, so that this information gets into the public > >domain. This would involve, as a starting point, writing or collecting > >various code templates, passing them around to anyone who has the > >appropriate tools and is willing to help (possibly anonymously), and > >collecting the results on a website. > > > > Good idea! > > >Is anyone interested in doing this? If there's a critical mass, I > >could try setting up a mailing list and a web site and repository, > >hopefully using existing resources from eda.org, seul.org, > >sourceforge, or whatever. > > > > I would... I have Synplify (Non-Pro unfortuanetly) at work for Altera. > > Cheers, > Martin > > TRW Automotive Advanced Product Development, > Stratford Road, Solihull, B90 4GW. UK > Tel: +44 (0)121-627-3569 > mailto:martin.j.thompson@trw.com > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 25971
I found out that all I needed to do was expand the inputs and to enter the "dont cares" in my truth table as .X. instead of just X The truth table is:- TRUTH_TABLE ([C2,C1,C0,A7,A6,A5,A4,A3,A2,A1,A0] -> [D]) [0,0,0,.X.,.X.,.X.,.X.,.X.,.X.,.X.,0] -> [0]; [0,0,0,.X.,.X.,.X.,.X.,.X.,.X.,.X.,1] -> [1]; [0,0,1,.X.,.X.,.X.,.X.,.X.,.X.,0,.X.] -> [0]; [0,0,1,.X.,.X.,.X.,.X.,.X.,.X.,1,.X.] -> [1]; [0,1,0,.X.,.X.,.X.,.X.,.X.,0,.X.,.X.] -> [0]; [0,1,0,.X.,.X.,.X.,.X.,.X.,1,.X.,.X.] -> [1]; [0,1,1,.X.,.X.,.X.,.X.,0,.X.,.X.,.X.] -> [0]; [0,1,1,.X.,.X.,.X.,.X.,1,.X.,.X.,.X.] -> [1]; [1,0,0,.X.,.X.,.X.,0,.X.,.X.,.X.,.X.] -> [0]; [1,0,0,.X.,.X.,.X.,1,.X.,.X.,.X.,.X.] -> [1]; [1,0,1,.X.,.X.,0,.X.,.X.,.X.,.X.,.X.] -> [0]; [1,0,1,.X.,.X.,1,.X.,.X.,.X.,.X.,.X.] -> [1]; [1,1,0,.X.,0,.X.,.X.,.X.,.X.,.X.,.X.] -> [0]; [1,1,0,.X.,1,.X.,.X.,.X.,.X.,.X.,.X.] -> [1]; [1,1,1,0,.X.,.X.,.X.,.X.,.X.,.X.,.X.] -> [0]; [1,1,1,1,.X.,.X.,.X.,.X.,.X.,.X.,.X.] -> [1]; This worked fine. Thanks to all of you for your input. AlanArticle: 25972
hi all I read the Xilinx application note xapp132 about the Virtex DLL and saw on page 5 >Source Clock Input - CLKIN >The CLKIN pin provides the user source clock (the clock signal on which the DLL operates) to >the DLL. The CLKIN frequency must fall in the ranges specified in the datasheet. The clock >input signal can be provided by one of the following: >. BUFG - Internal global clock buffer >. IBUFG - Global clock input buffer on the same edge of the device (top or bottom) >. IO_LVDS_DLL - the pin adjacent to a global clock pin. I thought it would be useful to provide a 50/50 mark/space ratio on a signal entering on a non GCK pin, so I implemented IBUF, BUFG, CLKDLL, BUFG. It was not to be however as Map gave this error message >ERROR:MapLib:102 - BUFG symbol "InB" (output signal=oscib) driving CLKDLL must > be driven by CLKDLL too. Hmmm. Xilinx Answer #7147 has this to say >General Description: Can any net in the design drive the clkin input of a clkdll? > >Solution 2: > >This is a valid error because if the CLKIN is driven by a non BUFG/IBUFG, >we cannot guarantee a proper phase relationship to the original clock and >timing analysis results will not be valid. This is consistent with the App Note (Xilinx XAPP# 132). ??? It continues > > >However... there are valid reasons for wanting to do this and the common >one is clock doubling where phase relationship to original clock doesn't >matter. The 3.1i release (May, 2000) will support this under environment >variable control, and it will also change the error message to indicate that >such an env var exists, but to warn the user that timing analysis results will >no longer be valid for paths affected by the output of this DLL. > >SET XIL_MAP_ALLOW_ANY_DLL_INPUT=1 (PCs) >setenv XIL_MAP_ALLOW_ANY_DLL_INPUT 1 (Work Stations) I'm not too bothered about the timing analysis being wrong so I tried it and got the same error message. :( Seems a shame they haven't implemented this. I can think of a few applications where it might be useful. What happens to the outputs of a DLL if the input Period is stable but not the Mark/Space ratio? KateArticle: 25973
Marc Battyani <Marc.Battyani@fractalconcept.com> wrote in message news:8qv3i5$l9k$1@reader1.fr.uu.net... > I have this : > entity US1 is port ( > ... > DDSFSK : out std_logic; > ... > ); end US1; > > and then > > DDSFSK <= '1'; > > Seems easy for me, but FPGA Express gives me : > > Error: Cannot isolate ports with direction 'INOUT' on net 'DDSFSK'. > (FPGA-DRCFIX-1) > > If I put DDSFSK <= '0'; instead of DDSFSK <= '1'; it works. > > Any clue ? I don't have any other use of this signal in the design. Are you sure that it is not used anywhere else? Here is what the help says: FPGA-DRCFIX-1 Message Cannot isolate ports with direction 'INOUT' on net '%1'. Description The Xilinx net-list reader requires that every net has at most one port on it. The named net has multiple ports attached to it and one of them has the direction 'INOUT'. Inserting a buffer to isolate this port maybe incorrect, and thus is not automatically performed. To fix this problem either modify the HDL or net-list such that the port has a direction input or output (if it is appropriate) or modify the design by merging all the ports on the named net and and in each cell instance of the modified design merging all the nets of pins corresponding to the merged ports. -- ============================ Mikhail Matusov Hardware Design Engineer Square Peg Communications Tel.: 1 (613) 271-0044 ext.231 Fax: 1 (613) 271-3007 http://www.squarepeg.ca > > Thanks > > Marc Battyani > > > >Article: 25974
"Mikhail Matusov" <matusov@ANNTIsquarepegSPPAMM.ca> wrote in message news:jGIA5.3054$wo.25887@news.magma.ca... > > Marc Battyani <Marc.Battyani@fractalconcept.com> wrote in message > news:8qv3i5$l9k$1@reader1.fr.uu.net... > > I have this : > > entity US1 is port ( > > ... > > DDSFSK : out std_logic; > > ... > > ); end US1; > > > > and then > > > > DDSFSK <= '1'; > > > > Seems easy for me, but FPGA Express gives me : > > > > Error: Cannot isolate ports with direction 'INOUT' on net 'DDSFSK'. > > (FPGA-DRCFIX-1) > > > > If I put DDSFSK <= '0'; instead of DDSFSK <= '1'; it works. > > > > Any clue ? I don't have any other use of this signal in the design. > > Are you sure that it is not used anywhere else? Here is what the help says: ... Yes it's only used once in the design. In fact I just found out that the pb is not related to this signal but to another part of the design. I have set one signal to a constant value in another part of the design and it complains here. When I set the other signal to a clock then it stops complaining.... Strange... Thanks anyway Marc Battyani
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