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Sounds like you need to clock the CClk a few more times. If you want to use the select map after you load it set Persist to yes. Steve "Wamsi Mohan" <wamsi_mohan@yahoo.com> wrote in message news:8df10c0.0107090723.79205b89@posting.google.com... > Hello. > The problem I am facing is that when I try to configure the XCV600E > using selectMAP, the Done does not go high. However, INIT does not go > low either to indicate any config error. > I follow the usual steps of driving prog low and then high, waiting for > Init to go high and then clock the data[7:0]. Bitgen is compiled with > cclk option (as opposed to jtag clk or userclk). The mode pins are set > to 110 (select MAP). I have tried to abort the config cycle and read > back the status word. I read back 0xDF which Xilinx claims is correct. > > Any thoughts? > Thanks > -Wamsi >Article: 32801
Hi everyone,
I'm trying to generate 200 MHz signal from 50 Mhz source using
CLKDLL. The simulation seems to work just fine. However when I try to
implement, I get the error:
ERROR:NgdBuild:466 - input pad net 'CLK_50Mhz' has illegal
connection
ERROR:NgdBuild:466 - output pad net 'LOCK' has illegal
connection
This was preceded by an earlier synthesis warning:
Warning: Existing pad cell '/vers1-Optimized/CLKDLL/clkpad' is
connected to the port 'CLK_50MHz' - no pad cells inserted at this
port. (FPGA-PADMAP-1)
Currently I don't have any UCF file (don't know how to create one). Is
this the source of my errors?
Thanks in advance.
James Wang
Article: 32802Hi Dean, I would recommend looking at the 'equations' section of the fitter report to see what logic was implemeneted. Your 'PHI' input most likely got optimized out as the previous posts were pointing out. If the equation shown in the fitter report does not involve the PHI signal, then it was optimized out... Hope that helps, Mark Dean Malandris wrote: > On 2 Jul 2001 14:48:40 GMT, hess@cs.indiana.edu (Caleb Hess) wrote: > > >What are you using the AND gate outputs for? If the output is unconnected, > >or simplifies to a logical don't care, then everything in front of it is > >unused. If you want to retain the inputs, try adding the KEEP attribute to > >them. > > The outputs of the AND gates fed two lots of 24-bit counters. Oddly > enough, when I modified another (unrelated) part of the circuit, the > problem went away. I was using v3.2 of the software. I've since > upgraded to v3.3 just in case.Article: 32803
Why dose everyone suggest Xilinx? when there are *other* people out there making FPGA's. We should not suggest that Xilinx is the world standard as their are compines that don't use Xilinx chips and only use one other make (ie Altera). Lets keep it balanced chaps, or we will have to start advertising within our own messages. Worst still - someone will paten this group 8o) ! Cyber_Spook_ManArticle: 32804
Make that "MSB" John_H wrote: > An added benefit: the LSB of the counter (the sign > bit) can be used to directly drive the counter reset.Article: 32805
Dear User Group; Gefen makes an interface that allows any computer with a DVI output, including the older G4 with DVI graphics to connect to any new Apple flat panel display 15" and 17" Studio Display and 22" Cinema Display monitors with ADC connection. The DVI to ADC Conversion Box as it is called also allows Macintosh users to add a second DVI PCI card and to drive a second Apple flat panel display (15" and 17" Studio Display and 22" Cinema Display ) The package includes: 1- The DVI to ADC Conversion Box 2- 6 feet DVI cable (M-M) 3- 6 feet USB cable (A-B) The package list price is $299.00 and we wanted to offer it to your user group at a special discount ($100.00) off or $199.00. Any purchases during the month of July 2001 will be honored at the reduced price. You can find more information online at http://www.gefen.com Call us and mention this ad to get your $100.00 discount. vygwbfyowhddmeypcjuzlubusArticle: 32806
cyber_spook <pjc@cyberspook.freeserve.co.uk> writes: > Why dose everyone suggest Xilinx? when there are *other* people out > there making FPGA's. We should not suggest that Xilinx is the world > standard as their are compines that don't use Xilinx chips and only use > one other make (ie Altera). > > Lets keep it balanced chaps, or we will have to start advertising within > our own messages. Worst still - someone will paten this group 8o) ! Hey, if people want Altera discussions on this NG, they should start some. This is a forum of the readers, by the readers, for the readers. There aren't any people chartered to generate new interesting content and post it here. So if the NG seems to have a Xilinx bias, it's only because that happens to be what a lot of people are using.Article: 32807
man... you guys must be the all-star FPGA team. thanks for all the input and i will try them to see if i can get the design to work. how long will it take to be an fpga guru? chrisArticle: 32808
Sorry for any "Xilinx lovefest" themes in my own messages. As much as I love Altera (and respect the other vendors) I haven't had the chance to design brand A into my designs in the last few... years. Brand X has been chosen recently for performance, price, or arbitrary external influence reasons. I'd enjoy getting back to the devices I spent most of my "formative years" developing my design talents. Until I can make the claim that they're better than a competitor, the competition gets the socket.Article: 32809
Silly me - just subtract the last stage instead of adding when the second
multiplicand is negative since +8-16=-8
1110 1110 -2
1101 1101 1101
----------- ----------- -----
+...1111110 +...1111110 + -2
+...0000000 +...0000000 + 0
+...1111000 +...1111000 + -8
-...1110000 +...0010000 - -16
----------- ----------- -----
...0000110 ...0000110 6
Article: 32810The binaries beginning with blif* are used for Abel designs. For example, blifsim is the Abel equation simulator. These programs will automatically be invoked by iSE Project Navigator for Abel design flows. -Dennis McCrohan, Xilinx CPLD s/w Steve Casselman wrote: > If you look in the Xilinx bin (xilinx/bin/nt on windows machines) directory > you'll find some undocumented tools. The ones I'm interested in are all the > blif tools. Is there any way to use these? Is there any documentation that > shows how to use these tools? > > Thanks > SteveArticle: 32811
Jure Oblak wrote: > > Hi, > > I have a design that uses several BlockRAMs. These blockRAMs > (RAMB4_S16) should have a deafult value written in them. I am using > the following code to define the INIT values of blockRAMs > attribute INIT_00 of U1: label is > "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF"; > attribute INIT_01 of U1: label is > "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF"; See Allan's advice for a free solution. Some synthesis tools allow a cleaner solution. I would code this RAM this as an array of vectors and let Leonardo generate the required BlockRAM attributes into the .edf file. This leaves your source clean and simulateable. --Mike TreselerArticle: 32812
Mark Ng wrote: > All 9500 data sheets list which Function Block and Macrocell a particular I/O > pin resides in. Given that, you can judge which pins are adjacent on the die. > Is that a hard & fast rule ? i.e. if 2 IOs are sourced from adjacent macrocells then their die pads will be adjacent ? > > If your IO pins fall in between two function blocks, you can usually tell if > they are adjacent by looking at the pin numbers. They are adjacent as the pin > numbers increase... > > I hope that helps.. > > Mark > O.k. except what happens for the BGA FGA case where there is no strict pin sequence ?Article: 32813
cyber_spook wrote: > Why dose everyone suggest Xilinx? when there are *other* people out > there making FPGA's. We should not suggest that Xilinx is the world > standard as their are compines that don't use Xilinx chips and only use > one other make (ie Altera). > > Lets keep it balanced chaps, or we will have to start advertising within > our own messages. Worst still - someone will paten this group 8o) ! > > Cyber_Spook_Man I think one of the bigger reasons must be the one mentioned by Peter A. some while back. Altera employees are not allowed to post on this NG whereas Xilinx ones are automatically issued with flame-proof underwear and directed to the battlefield.Article: 32814
> Lets keep it balanced chaps, or we will have to start advertising within > our own messages. Worst still - someone will paten this group 8o) ! use TTL and Vacuum Tubes. Signed "Friends of dusty old parts"Article: 32815
I really stopped considering Altera when they said "reconfigurable computing is a red herring." What happened (IMHO) is Xilinx said "we believe in the future of reconfigurable computing" and Altera said "we don't!" I was also pretty angered when one of the head people at Altera said "we make our tools for idiots since all engineers are idiots!" I lost all respect Altera when their head of reconfigurable computing could not go to a conference (he had been on the program committee for years) because he was born in that city in which the conference was held that year. When you have been around as long as I have you get to know something about the companys you deal with. If I had to I'd work at Xilinx but I'd never work at Altera. Steve Casselman "cyber_spook" <pjc@cyberspook.freeserve.co.uk> wrote in message news:3B4A1C44.67603D24@cyberspook.freeserve.co.uk... > Why dose everyone suggest Xilinx? when there are *other* people out > there making FPGA's. We should not suggest that Xilinx is the world > standard as their are compines that don't use Xilinx chips and only use > one other make (ie Altera). > > Lets keep it balanced chaps, or we will have to start advertising within > our own messages. Worst still - someone will paten this group 8o) ! > > Cyber_Spook_Man > >Article: 32816
> Hey, if people want Altera discussions on this NG, they should start some. > This is a forum of the readers, by the readers, for the readers. There > aren't any people chartered to generate new interesting content and post > it here. I thought there are. Or at least there are people chartered by Xilinx to answer to interesting content posted here. They do a great job. The group would surely benefit from Altera and Actel doing the same. Kolja SulimmaArticle: 32817
Mike Treseler wrote: > Some synthesis tools allow a cleaner solution. > I would code this RAM this as an array of vectors and > let Leonardo generate the required BlockRAM attributes > into the .edf file. Does Leonardo handle clock enables to the BlockRAM? Does Leonardo handle different widths on the two ports? Does Leonardo handle the clear register input to the BlockRAM? Then some of us are going to be instantiating memories... -- Phil HaysArticle: 32818
Rick Filipkiewicz wrote: > cyber_spook wrote: > > > Why dose everyone suggest Xilinx? when there are *other* people out > > there making FPGA's. We should not suggest that Xilinx is the world > > standard as their are compines that don't use Xilinx chips and only use > > one other make (ie Altera). > > > > Lets keep it balanced chaps, or we will have to start advertising within > > our own messages. Worst still - someone will paten this group 8o) ! > > > > Cyber_Spook_Man > > I think one of the bigger reasons must be the one mentioned by Peter A. some > while back. Altera employees are not allowed to post on this NG whereas > Xilinx ones are automatically issued with flame-proof underwear and directed > to the battlefield. Poppycock. Altera employees have posted on this newsgroup in the past, although not anywhere near the extent of Xilinx representative postings. Check recent history of the group for postings by Brian Sullivan. Think of what you're saying: Actel and Altera each has employees paid specifically to communicate with customers, and yet both companies prohibit communication to 1000s of customers at a time via a usenet newsgroup? That probably is not the case. The reasons for Altera and Actel *not* having their own "Peter Alfke equivalents" are (my guesses): 1. The is and will only be *one* Peter Alfke (had to throw that one in!). 2. The organisational structures of Altera and Actel maintain more or less distinct responsibilities between groups (e.g. marketing, sales, tech support, customer service, field apps/sales, etc.). Altera or Actel) would need 3 or more people (from different groups with different VPs in charge) to represent the various groups in the company, a logistical (and managerial) problem that makes the implementation too complicated for most companies. Peter Alfke is in one such group at Xilinx, but he has the charter to *span* these distinct groups and act as an ombudsman to this newsgroup. Xilinx gave Peter such a charter; without it he would have had his keyboard-typing fingers chopped off (both of them) for crossing marketing/sales/tech support boundaries. I repeat, these postulations are nothing more or less than my own guesses. I'm sure Peter will help clarify or correct these wild guesses 8^> I may be way off base on this, but I sure had fun writing it! Bob Elkind, the e-team: fpga/design consultingArticle: 32819
Steve Casselman wrote: > I really stopped considering Altera when they said "reconfigurable computing > is a red herring." What happened (IMHO) is Xilinx said "we believe in the > future of reconfigurable computing" and Altera said "we don't!" I was also > pretty angered when one of the head people at Altera said "we make our tools > for idiots since all engineers are idiots!" I lost all respect Altera when > their head of reconfigurable computing could not go to a conference (he had > been on the program committee for years) because he was born in that city in > which the conference was held that year. > > When you have been around as long as I have you get to know something about > the companys you deal with. If I had to I'd work at Xilinx but I'd never > work at Altera. > > Steve Casselman Interesting characterisations, Steve... Some of us have been around long enough (Ray Andraka, Phil Freidin, and quite a few others) to know that both Xilinx and Altera have, on occasion, had "BOZOs" (a technical term, not meant to insult professional clowns) in their employ. And both outfits have some gems, as well. Personally, I've met both types at both companies, and I've been burnt at different times by both companies. In one instance, my project was *sunk* by parts that did not meet datasheet specs (and the company *knew* that, but refused to come clean), and as a result, shortly thereafter, my career took a sharp left (or right) turn. In short, I can personally attest to the fact that both Altera and Xilinx are somewhat less than perfect, but are too worthy of our attention and interest to ignore. If I ignore or dismiss either outfit, I do myself (and my clients) a dis-service. Bob Elkind, the e-team: fpga/design consultingArticle: 32820
Good Morning,
my problem is that Matlab produce for me the coefficient
-0.12456985477 that I've to translate in two's complement with one bit
for the sign , one bit before the point and 10 bit later, may you tell
me which string of binary number I've to put inside my FIR for this
coefficient ??
Thank you really much...
Antonio D'Ottavio
Article: 32822bob elkind wrote: > Rick Filipkiewicz wrote: > > > > I think one of the bigger reasons must be the one mentioned by Peter A. some > > while back. Altera employees are not allowed to post on this NG whereas > > Xilinx ones are automatically issued with flame-proof underwear and directed > > to the battlefield. > > Poppycock. Altera employees have posted on this newsgroup in the past, although > not anywhere near the extent of Xilinx representative postings. Check recent > history of the group for postings by Brian Sullivan. > > Think of what you're saying: Actel and Altera each has employees paid > specifically to communicate with customers, and yet both companies prohibit > communication to 1000s of customers at a time via a usenet newsgroup? > That probably is not the case. > This wasn't my comment - it came from Peter A. > > The reasons for Altera and Actel *not* having their own "Peter Alfke > equivalents" are (my guesses): > > 1. The is and will only be *one* Peter Alfke (had to throw that one in!). > Not forgetting Austin Lesea doing good work on the DLL/PLL debate [and Shannon], Vikram Seth, Brian ??, Mark Ng. > > 2. The organisational structures of Altera and Actel maintain more or less > distinct responsibilities between groups (e.g. marketing, sales, tech support, > customer service, field apps/sales, etc.). Altera or Actel) would need 3 or > more people (from different groups with different VPs in charge) to > represent the various groups in the company, a logistical (and managerial) > problem that makes the implementation too complicated for most companies. > I don't see why organisational structure has, or should have, anything to do with posting on a NG. What you seem to be saying is IMHO far too formal an approach for a NG. We're all grown-ups here & will allow for the fact that even an FPGA Vendor employee may have only part of the picture. Most times I'd rather have a description of the elephant's leg right now than wait for a sanctioned description of the whole animal.Article: 32823
There are a number of fft cores out there. I've got one that I thought to check out but never got time.. :) I think I got it from www.opencores.org but I am not sure - But, if you are doing your Master Thesis I think it is a good idea to write your own FFT core which is not very difficult if you know gate arrays and vhdl/verilog - If you use an "Open Core" you'll have as much trouble to verify it as you would have to write your own - and you miss the fun of implementing fast arithmetics in modern gate arrays. Good Luck with your Master Thesis /Johan www.wdi.se "llandre" <andmars@tin.it> skrev i meddelandet news:7MWB6.24511$r67.507093@news2.tin.it... > I'm looking for a free FFT core written in VHDL for a graduating > thesis. Where ca I find it? > > Thanks a lot in advance. > > -- > llandre > e-mail : andmarsNOSPAM@tin.it > web : http://www.dei.unipd.it/~patch > > >Article: 32824
"Magnus Homann" <d0asta@mis.dtek.chalmers.se> skrev i meddelandet news:lty9tie3k1.fsf@mis.dtek.chalmers.se... > Peter Alfke <peter.alfke@xilinx.com> writes: > > > yorams@hywire.com wrote: > > > > > Hi. > > > I have read xilinx application note xapp258 and I have the following > > > question: > > > > > > <snip> > > > the following might occur > > > > > > path between bit i of counter to its synchronizer is: epsilon; > > > path between bit j of counter to its synchronizer is: epsilon + Tcyc; > > > > > > under these condition the synchronizer can sample false value of the gray > > > counter and thus give false full or empty flag. > > > > > > > > > Is it possible ? > > > Can it be avoided ? > > > > > > > The idea behind using Grey counters is that they make the problem > > you mention disappear. If you transfer the Grey value from one > > clock domain to the other, and you do it at the most awkward moment, > > right as the Grey counter increments, you will not transfer garbage > > ( which might happen with a binary counter ), since adjacent Grey > > values only differ by one bit. So you transfer either the old or the > > new value. Either one is as good as the other at that particular > > moment. > > Peter, I understood his comments as what happens if the skew of the > counter bits is larger than the cycle time. Unlikely, but > theoretically possible. > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se Hi Homann, wasn't Peters comment about transfer over clock domain borders? Might be way out as usual /Johan P www.wdi.se
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