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I have the Silo-3 Demo from "Verilog HDL_ by Samir Palnitkar installed on two machines running Windows 2000 Pro. One is a Dell Dimension XPS Pro200n, the other is a Dell 4100. Silo runs on the XPS, but crashes with a memory access violation as soon as I attempt to run a simulation on the 4100. This behavior occurs with exam1a.s. (While Silo does run on the XPS, it crashed while I was adjusting a window size. How stable is the demo version of Silo?) Does anyone have any idea what might be causing this? Thanks, Dave FeustelArticle: 33276
Hello everybody, I (and I suppose many other people in this group ;-) have the problem, that it is really difficult to estimate AND measure the power consumption of a FPGA design. I know that power consumption strongly depends on size of the design, clock frequency and, one of the most difficult to estimate parameters, average toggle rate. OK, we have the virtex power estimator, XPower and some nice application notes, but after all its just a very raw guess, then we add 100% security plus a layout to change the power supply easy on the prototype ;-) But what is VERY sad is the fact, that it is mostly impossible, to measure the power consumption on the real, working board :-((( There inst just one VCC pin, there are many, all connectet to the power plane. Cutting the power plane and feeding the whole power over a zero Ohm resistor is no good idea. Socket?? With BGAs?? Signal integrity?? Damit!!! Whats your expirience with this? Any hints? -- MFG FalkArticle: 33277
usually, you need special equipment for soldering BGAs such as the A.P.E. hot air reflow system. you can set the temperature and pre-heat the board as well. also, if you mess up on soldering an fpga, you can re-ball the bga by buying a re-ball kit. i forget the name of the manufacturer that has it, but i am sure a simple search on a meta-search engine can find it. chrisArticle: 33278
Measure the differential power on the board between a configured and running FPGA and one that is either unconfigured or loaded with a placeholder static design. Falk Brunner wrote: > Hello everybody, > > I (and I suppose many other people in this group ;-) have the problem, > that it is really difficult to estimate AND measure the power > consumption of a FPGA design. I know that power consumption strongly > depends on size of the design, clock frequency and, one of the most > difficult to estimate parameters, average toggle rate. OK, we have the > virtex power estimator, XPower and some nice application notes, but > after all its just a very raw guess, then we add 100% security plus a > layout to change the power supply easy on the prototype ;-) > But what is VERY sad is the fact, that it is mostly impossible, to > measure the power consumption on the real, working board :-((( > There inst just one VCC pin, there are many, all connectet to the power > plane. Cutting the power plane and feeding the whole power over a zero > Ohm resistor is no good idea. Socket?? With BGAs?? Signal integrity?? > Damit!!! > > Whats your expirience with this? > Any hints? > > -- > MFG > Falk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33280
Philipp Krause <pkk@spth.de> wrote in message news:3B594569.9000504@spth.de... > Are there any free tools around? I'd like to learn VHDL, but don't want > to spend money on commercial software since I don't know which chip > family I'll use when it comes to implementing something. > > Philipp Krause > You can get the free Altera software on this page: http://www.altera.com/support/software/sof-download_center.html Note that you can also get a free copy of Exemplar's Leonardo Spectrum synthesis tool or Synopsys' FPGA Express synthsis tool for either VHDL or Verilog on this page as well. The third-party tools are the same tools you'd get if you were to buy them, but they only let you target Altera devices. -Pete-Article: 33281
Dave Feustel wrote:
> I have the Silo-3 Demo from "Verilog HDL_ by Samir Palnitkar
> installed on two machines running Windows 2000 Pro.
> One is a Dell Dimension XPS Pro200n, the other is a Dell 4100.
> Silo runs on the XPS, but crashes with a memory access violation
> as soon as I attempt to run a simulation on the 4100. This behavior
> occurs with exam1a.s. (While Silo does run on the XPS, it crashed
> while I was adjusting a window size. How stable is the demo version
> of Silo?)
>
> Does anyone have any idea what might be causing this?
As a wild guess - Windows 2000. The same program works ok here on Win98.
Vladimir Dergachev
>
> Thanks,
>
> Dave Feustel
>
>
>
Article: 33282Peter Ormsby wrote: > > Philipp Krause <pkk@spth.de> wrote in message > news:3B594569.9000504@spth.de... > > Are there any free tools around? I'd like to learn VHDL, but don't want > > to spend money on commercial software since I don't know which chip > > family I'll use when it comes to implementing something. > > > > Philipp Krause > > > > You can get the free Altera software on this page: > > http://www.altera.com/support/software/sof-download_center.html > > Note that you can also get a free copy of Exemplar's Leonardo Spectrum > synthesis tool or Synopsys' FPGA Express synthsis tool for either VHDL or > Verilog on this page as well. The third-party tools are the same tools > you'd get if you were to buy them, but they only let you target Altera > devices. > > -Pete- and Leonardo only runs if you have a network card...Article: 33283
Hi Can anyone tell me where I can download A|RT Builder & A|RT Designer? www.edadirect.com and www.frontierd.com/ only have trial versions of A|RT Fixed Point Library. Are there any other good C to VHDL converters available? Thanks AndrewArticle: 33284
Hi Does anyone know if there is an alternate site to download Baseline 10.1 and Maxplus II from? The Altera FTP server does not seem to support resuming, and the files are too big to download in one go. Thank You Andrew GrayArticle: 33285
You can order ADL (Altera Digital Library) CD. On CD You will find all You need. M. -- Veselic Mladen Laboratorija Sigma ECO Izenjering Andrew Gray <andrewgray@iafrica.com> wrote in message news:3b5aa232.0@news1.mweb.co.za... > Hi > > Does anyone know if there is an alternate site to download Baseline 10.1 and > Maxplus II from? > The Altera FTP server does not seem to support resuming, and the files are > too big to download in one go. > > Thank You > > Andrew Gray > >Article: 33286
Hey Everyone, Does anyone know how to interface from the Altera software package programming output to jtag. Altera tries to sell its serial programming cable BitBlaster for around $500, which IMHO is a little overpriced ;) (since we go from serial data to ... yep serial data, right??) Thanks, MichaArticle: 33287
Hi, See the pdf file, it's contained the schematic: http://www.altera.com/literature/ds/dsbytemv.pdf It's about $150.00. It also Supports both JTAG and Passive-Serial download protocol, 3.3V I/O with 5.0V tolerance I/O. Of course, you can build your own as you wished. Hope this helps, HongArticle: 33288
Falk Brunner wrote: > I (and I suppose many other people in this group ;-) have the problem, > that it is really difficult to estimate AND measure the power > consumption of a FPGA design. I know that power consumption strongly > depends on size of the design, clock frequency and, one of the most > difficult to estimate parameters, average toggle rate. OK, we have the > virtex power estimator, XPower and some nice application notes, but > after all its just a very raw guess, then we add 100% security plus a > layout to change the power supply easy on the prototype ;-) > But what is VERY sad is the fact, that it is mostly impossible, to > measure the power consumption on the real, working board :-((( Measure temperature rise. This is an idea I've used when other methods were not reasonable. Measuring the package temperature and/or the die temperature and the input airflow temperature and use the published thermal resistance numbers to convert the difference(s) into estimated temperature. The achievable accuracy depends on the degree to which you match the measurement conditions of the published thermal resistance numbers. See: http://www.xilinx.com/partinfo/pkgs_pdf/pkgs1.pdf Also, it would be possible to measure a temperature rise from a known heat flow (build a board with only the FPGA, and load a design that is intended only to generate heat, and then directly measure the power to the board, and use this to calibrate your board/test fixture for the real board. -- Phil HaysArticle: 33289
"bob elkind" <eteam@aracnet.com> wrote in message news:3B56B4AD.1CAB25AB@aracnet.com... <snipped> > AHDL design language gets you pretty close to the the low level of the device > technology, maintains pretty good "power", and avoids 90% of the frustration > level of VHDL. Don't forget, schematic libraries can be a minor tar baby unto > themselves. For a newbie, AHDL is a really good starting point. I'd steer my > own offspring into AHDL first, to build confidence, before suggesting they > tackle VHDL on their first design. And I still think schematics are (more or > less) a dead end, with AHDL being a better alternative.. > > -- Bob Elkind, the e-team FPGA/design consulting I'm just getting started working with FPGAs. What is an example of (and source for) an AHDL that I could use to generate a design for a (Xilinx Spartan 2 or Virtex 2) FPGA? Thanks, Dave Feustel Fort Wayne, IndianaArticle: 33290
Since Verilog doesn't handle signed numbers natively (yet... look for
Verilog 2001 support from the synthesis vendors) I look at this from the
same perspective as AHDL. I don't think you can get conceptually much
simpler than the method you suggested but you can keep the logical
resources to a minimum. It's been a while since I've touched AHDL so
forgive me if something looks strange below - I think you'll get the
idea.
Rather than sign extending the adder and doing an xor of the top two
bits (b'10' for saturated negative and b'01' for saturated positive),
recognizing that the inputs to the xor function boil down to just the
two sign bits and the carry-in to the sign stage lets you manipulate the
carry out of the last stage before the sign within the Altera
architecture carry chain to give you the results you want.
VARIABLES
y[7..0] :NODE;
SignCarryIn :CARRY;
Saturated :CARRY;
q[7:0] :DFF;
BEGIN
(SignCarryIn,y[6..0]) = (0,a[6..0]) + (0,b[6..0]); -- raw add w/o
signs
y[7] = a[7] & b[7] # (a[7] $ b[7]) & !SignCarryIn;
Saturated = a[7] & b[7] & !SignCarryIn # !a[7] & !b[7] &
SignCarryIn;
q[].clk = Clk;
q[7] = y[7]; -- sign bit above includes saturation
IF( Saturated ) THEN -- if saturated,
q[6..0] = !a[7]; -- a[7]==b[7]==1 gives q[7]=1, q[6..0]=0
ELSE -- a[7]==b[7]==0 gives q[7]=0, q[6..0]=-1
q[6..0] = y[6..0]; -- if unsaturated, q[]=y[]
END IF;
END
Altera gives you a synchronous load that's independent of the carry
chain allowing the combinatorial result to control the load and the sign
from either value (it takes two positives or two negatives to saturate)
to determine the load value. [The Xilinx carry chain can't give
same-cycle load based on carry out unless the synchronous set/reset is
used and the MSbit is in a different slice than the other bits - a
little ugly.]
If you don't care about symmetry around zero, ignore this paragraph to
avoid confusion... If you want the saturation to be +/- 2^n-1, you
might try adding a carry-in bit (+1) to the next adder stage based on a
-2^n detect. If there is no next adder stage a slower performance
saturable adder can take the +1 carry-in straight from the combinatorial
y[] == -2^n check though the timing analysis might choke a little on
this safe race condition; (a+b) == -2^n doesn't trigger the saturation
load so -2^n+1 still won't trigger the load.
Not simpler as much as the same concept sped up.
Russell Shaw wrote:
> Hi all,
>
> I need a saturable adder like the ALU in DSPs.
> I thought maybe you could just sign-extend the two input
> busses, add them, then detect if the result has overflowed
> the input bus width. If so, the result could be saturated
> to max-neg or max-pos.
>
> AHDL seems a bit limited for handling signed numbers. I'm
> learning some VHDL because it seems to have more constructs
> and knows about signed/unsigned numbers.
>
> Are there any simpler ways of doing such an adder?
>
> --Russell
Article: 33291In article <3B59D22E.C7D8256F@gmx.de>, Falk Brunner <Falk.Brunner@gmx.de> wrote: > Hello everybody, > > I (and I suppose many other people in this group ;-) have the problem, > that it is really difficult to estimate AND measure the power > consumption of a FPGA design. I know that power consumption strongly > depends on size of the design, clock frequency and, one of the most > difficult to estimate parameters, average toggle rate. OK, we have the > virtex power estimator, XPower and some nice application notes, but > after all its just a very raw guess, then we add 100% security plus a > layout to change the power supply easy on the prototype ;-) > But what is VERY sad is the fact, that it is mostly impossible, to > measure the power consumption on the real, working board :-((( > There inst just one VCC pin, there are many, all connectet to the power > plane. Cutting the power plane and feeding the whole power over a zero > Ohm resistor is no good idea. Socket?? With BGAs?? Signal integrity?? > Damit!!! > > Whats your expirience with this? > Any hints? One thing that would be really useful but that nobody has to my knowledge is a tool that works in conjunction with a functional simulation of the device that could actually look at internal nodes and see toggle rates, see pin I/Os humping up and down, etc. and would automatically figure out the power consumption. I have wanted a tool like this for years. Does anybody know if such a thing exists? Nate ---------------------------------------------------- Nate Goldshlag nateg@pobox.com Arlington, MA http://www.pobox.com/~nategArticle: 33292
Must the network card be connected to the internet for Leonardo to work? "Russell Shaw" <rjshaw@iprimus.com.au> wrote in message news:3B5A99EB.8E4F346D@iprimus.com.au... > > > Peter Ormsby wrote: > > > > Philipp Krause <pkk@spth.de> wrote in message > > news:3B594569.9000504@spth.de... > > > Are there any free tools around? I'd like to learn VHDL, but don't want > > > to spend money on commercial software since I don't know which chip > > > family I'll use when it comes to implementing something. > > > > > > Philipp Krause > > > > > > > You can get the free Altera software on this page: > > > > http://www.altera.com/support/software/sof-download_center.html > > > > Note that you can also get a free copy of Exemplar's Leonardo Spectrum > > synthesis tool or Synopsys' FPGA Express synthsis tool for either VHDL or > > Verilog on this page as well. The third-party tools are the same tools > > you'd get if you were to buy them, but they only let you target Altera > > devices. > > > > -Pete- > > and Leonardo only runs if you have a network card...Article: 33293
The version of Silos that I was using is old. I downloaded Silosdemoprogram and that doesn't crash, but I get error messages when I attempt simulate the exam1 project. "Vladimir Dergachev" <volodya@mindspring.com> wrote in message news:N3t67.290$UB6.53498@e3500-atl1.usenetserver.com... > Dave Feustel wrote: > > > I have the Silo-3 Demo from "Verilog HDL_ by Samir Palnitkar > > installed on two machines running Windows 2000 Pro. > > One is a Dell Dimension XPS Pro200n, the other is a Dell 4100. > > Silo runs on the XPS, but crashes with a memory access violation > > as soon as I attempt to run a simulation on the 4100. This behavior > > occurs with exam1a.s. (While Silo does run on the XPS, it crashed > > while I was adjusting a window size. How stable is the demo version > > of Silo?) > > > > Does anyone have any idea what might be causing this? > > As a wild guess - Windows 2000. The same program works ok here on Win98. > > Vladimir Dergachev > > > > > > Thanks, > > > > Dave Feustel > > > > > > > >Article: 33294
Hello, I am thinking the cost between 3-to-1 and 4-to-1 mux. The thing is that in 2 level logic, the 3-to-1 MUX has lower cost than the other one. Am I correct? However, I do not know in real FPGA implemeatation, what is the cost difference between them? Thnaks for help, -ysliArticle: 33295
Has anyone had any experience using the Xilinx Multilinx cable to configure via USB? Thanks, Dave Feustel Fort Wayne, IndianaArticle: 33296
"Andrew Gray" <andrewgray@iafrica.com> wrote in message news:3b5aa232.0@news1.mweb.co.za... > > Does anyone know if there is an alternate site to download Baseline 10.1 and > Maxplus II from? > The Altera FTP server does not seem to support resuming, and the files are > too big to download in one go. Not to my knowledge, and after downloading, I couldn't get their key to work. I'd suggest following Maki's suggestion, and ordering the CD. That's what I will do, as I've had no success with the d/l key. BillArticle: 33297
Okay, maybe the "race" condition in the slower performance saturable counter isn't so safe... a -(2^n+1) might get stuck with a false carry-in giving the -2^n value rather than the -(2^n-1) that I was expecting. A next-cycle carry-in is still safe, at least. John_H wrote: > If you don't care about symmetry around zero, ignore this paragraph to > avoid confusion... If you want the saturation to be +/- 2^n-1, you > might try adding a carry-in bit (+1) to the next adder stage based on a > -2^n detect. If there is no next adder stage a slower performance > saturable adder can take the +1 carry-in straight from the combinatorial > y[] == -2^n check though the timing analysis might choke a little on > this safe race condition; (a+b) == -2^n doesn't trigger the saturation > load so -2^n+1 still won't trigger the load.Article: 33298
> > I have the Silo-3 Demo from "Verilog HDL_ by Samir Palnitkar > > installed on two machines running Windows 2000 Pro. > > One is a Dell Dimension XPS Pro200n, the other is a Dell 4100. > > Silo runs on the XPS, but crashes with a memory access violation > > as soon as I attempt to run a simulation on the 4100. This behavior > > occurs with exam1a.s. (While Silo does run on the XPS, it crashed > > while I was adjusting a window size. How stable is the demo version > > of Silo?) > > > > Does anyone have any idea what might be causing this? > > As a wild guess - Windows 2000. The same program works ok here on Win98. The Silos executable bundled with that book is probably very very old, back from the Win95 days. I have had no problems running an updated Silos demo version under Win2000 Pro. Unfortunately, simucad.com recently stopped handing out the free demo version. Now they require you register for an evalulation version.Article: 33299
Thanks for the information. Does icarus run under windows, or do I have to run that part on the Linux system? I have been playing with microprocessors for quite a while, but the FPGA kit is my first adventure in that area. What I had in mind for the FPGA was a 32 bit shift register or two, to be used for I/O expansion on a small micro with limited pin count. And also to learn something new and prevent "brain rust". In my experience, except for the flash of light and puff of smoke type errors, it's usually my code. Vladimir Dergachev wrote: > Tom Wyckoff wrote: > > >> I purchased Atmels' AT40K FPGA starter kit after reading that it "includes >> everything you need to get started......" It didn't. It came with a > > > Yep. The statement above was true a year ago, but since the company that > was making inexpensive synthesizer got acquired.. Good news below. > > >> trial >> license for a synthesizer, but it was expired. I have the open cores >> CDROMs. What, if anything, can I install from the CDROM to make this >> device useful? I have an idea for a simple project, but I am missing an >> essential piece of the software puzzle. >> >> Thanks, >> >> Tom Wyckoff >> >> > > > Actually I have got the same kit and I have not used my license yet. I am > using Icarus Verilog (www.icarus.com) to which I wrote an edif output > module (volodya-project.sourceforge.com). It works as long as you stay away > from anywhere complex behavioral stuff - as iverilog sythesis module cannot > properly handle "for" and "if" yet. This stuff is GPL. > > I would certainly appreciate some help as I am quite new to the hardware > part and it sometimes it takes a while to tell whether the error is in my > code, or that hardware is working differently from what I think.. > > Vladimir Dergachev
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