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In article <TQ057.1409$sE4.26519@news6.giganews.com>, dwright@srtorque.com says... > Has anyone had a working logic design in VHDL other than a few Cypress and > Xilinx insiders? Do I detect some frustration? Been there, and fairly recently. Sure. It took a while, some more gray hairs (well, mostly silver now), and a lot of persistence, but I'm getting reasonably good at it now. Lots more to learn, but that keeps it interesting. > Logic was never this complicated before! Sure it was. Try pushing the envelope in MSI. I did years ago and it was not easy. I remember when 80/40MHz was a stretch using ECL (even the 4.5V 1000A linear power supplies were "interesting"). Timing analysis? That's what scopes and delay lines (be they discrete or different lengths of coax) were used for. ;-) > What a total waste of human intelligence. > > It is far easier to build with discrete MSI/LSI parts or code in computer > language than get even something simple into a small CPLD or FPGA. Umm, VHDL is a computer language. ;-) VHDL, and I assume Verilog (haven't used it) has a very steep learning curve, to be sure. The FPGA architecture and implementation tools have a steep learning curve. Simulation has a steep curve. Yes, it's hard work, but I love it when a plan comes together. My first VHDL implementations of simple I/O circuits were a wonder to behold (wonder how they worked). It took a few passes to be able to turn out respectable looking stuff. When some fairly complex state machines worked the first time out of the box, I was sold. Besides, if it were easy they wouldn't pay the bux! ;-) ---- KeithArticle: 33151
Ray Andraka wrote:
>
> Yep, somewhere around 15 million marketing gates worth this past year, all in
^^^^^^^^^^^^^^^
How many real gates is that then Ray?
Nial.
Article: 33152> Is this FIFO asynchronous, i.e., are the read and write clocks > mutually asynchronous? If so, and if you're meeting static timing, > I'd bet on a problem in the control logic. A resynchronization > problem isn't going to show up as a static timing error, but it > certainly can sink your design. > > Bob Perlman Thanks for the info but I've done the due diligence on the design. Again it's not temperature related (as I'd expect for timing problems assuming enough IC's are screened). I also know about the timing files - we spent several weeks figuring out those timing problems before Xilinx "remembered" the speed file issue. I understand that Xilinx has recalled stock from distributors for rescreening. Something about metal particle defects shorting routing channels around BRAM's - this would explain why certain parts work w/ certain bit files. And why the failures are of the "hard" type - not intermittent as in a timing related failure. Buyer beware, I'd be interested in anyone else's story. ThanksArticle: 33153
Hi, to my knowledge, XILINX RAM/ROM blocks must *ALWAYS* be instantiated and cannot be automatically inferred during RTL synthesis (at least this is the case for FPGA compiler). The contents of instantiated 16x1RAM/ROM can then be initialized using the INIT attribute. XILINX LUT's can be either used as 4-input function generators or as 16x1 RAM. In case your 'addr' parameter was 4bits wide (16 possible case alternatives) and signal q is n bits wide, you would get a synthesis result of n parallel LUT's (function generators) which is exactly the same as n parallel 16x1 bit RAM's. So in this case you couldn't improve on your design using RAM's. I'm not sure if you could improve on your design even if you were using the VIRTEX block select RAM, which can store up to 4096x1 bits and thus can serve as 12 input function generator. For your code example a 16bits function generator with 16 outputs would be required (and hence a 64k x 16 RAM). best regards, Robert Martin Schoeberl schrieb: > I have a simple VHDL code like: > > process(addr) begin > > q <= x"84ff"; -- not impl loop > case addr is > when x"0000" => q <= x"8200"; -- nop > when x"0002" => q <= x"d2ff"; -- iconst_m1 > when x"0003" => q <= x"d200"; -- iconst_0 > when x"0004" => q <= x"d201"; -- iconst_1 > when x"0005" => q <= x"d202"; -- iconst_2 > .... > > to implement a ROM. > But WebPACK produces LUT's and does not use the internal ram blocks. > As a result the design does not fit. > Any suggestion how to give the sysnth. or map tool a hint to use the ram > block? > > Thanks > Martin > -- > Whant to see the evolution of a Java processor? > > http://www.jopdesign.com -- ------------------------------------------------------------------------------ Dipl.-Ing. Robert Siegmund email: rsie@infotech.tu-chemnitz.de Chemnitz University of Technology Dpt. of Systems and Circuit Design www: http://www.tu-chemnitz.de/~rsie Chemnitz,Germany ------------------------------------------------------------------------------Article: 33154
Martin,
I would suggest you to instantiate a BRAM into your design with WE's
grounded and the INIT values are set as you want. I am attaching a sample
code to illustrate this.
Regards,
Ekrem.
---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rom_imp is
Port (
Exp_In: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
Log_In: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
Clk: IN STD_LOGIC;
Exp_Out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
Log_Out: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
end rom_imp;
architecture behavioral of rom_imp is
component RAMB4_S8_S8
port (
ADDRA: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
ADDRB: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
CLKA: IN STD_LOGIC;
CLKB: IN STD_LOGIC;
DIA: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
DIB: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
DOA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
DOB: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
ENA: IN STD_LOGIC;
ENB: IN STD_LOGIC;
RSTA: IN STD_LOGIC;
RSTB: IN STD_LOGIC;
WEA: IN STD_LOGIC;
WEB: IN STD_LOGIC);
end component;
attribute init_00:string;
..
attribute init_0f:string;
attribute init_00 of bram1:label is
"F772BFBB1B3418BD6BA826EB940967083FCF38B8A4870378AE1545BE93E22D01";
..
..
..
attribute init_0f of bram1:label is
"3089E06F397D90921F64E93A2D7840B842E5CF86147C995EEA9BDDCE2802F06D";
begin
bram1:RAMB4_S8_S8
port
map(ADDRA=>Exp_In,ADDRB=>Log_In,CLKA=>clk,CLKB=>clk,DOA=>Exp_Out,DOB=>Log_Out,
ENA=>'1',ENB=>'1',RSTA=>'0',RSTB=>'0',WEA=>'0',WEB=>'0',DIA=>"00000000",DIB=>"00000000");
end behavioral;
---
Martin Schoeberl wrote:
> I have a simple VHDL code like:
>
> process(addr) begin
>
> q <= x"84ff"; -- not impl loop
> case addr is
> when x"0000" => q <= x"8200"; -- nop
> when x"0002" => q <= x"d2ff"; -- iconst_m1
> when x"0003" => q <= x"d200"; -- iconst_0
> when x"0004" => q <= x"d201"; -- iconst_1
> when x"0005" => q <= x"d202"; -- iconst_2
> ....
>
> to implement a ROM.
> But WebPACK produces LUT's and does not use the internal ram blocks.
> As a result the design does not fit.
> Any suggestion how to give the sysnth. or map tool a hint to use the ram
> block?
>
> Thanks
> Martin
> --
> Whant to see the evolution of a Java processor?
>
> http://www.jopdesign.com
Article: 33155
Russell Shaw wrote:
> > This CUPL code creates a 4 bit, saturating UP counter...
>
> This is the same kind of thing in AHDL:
>
> SUBDESIGN Sat_cntr(
> CLK: input;
> Dout[3..0]: output;
> )
>
> variable
> cntr[3..0]: DFF;
>
> BEGIN
> cntr[].clk=CLK;
>
> if(cntr[]!=H"f")
> then
> cntr[]=cntr[]+1;
> else
> cntr[]=cntr[];
> end if;
>
> Dout[]=cntr[];
> END;
I still think the VHDL is simpler. As this is a sub part of a
design I'll not include the entity or architecture declarations.
I've included a reset to make it more useful.
signal count : std_logic_vector(3 downto 0);
(all signals are declared in the architecture defn before the begin
statement).
process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
count <= "0000";
elsif(count /= "1111") then
count <= count + 1;
end if;
end if;
end process;
Nial.
Article: 33156thomas, My own highly biased opinion: You will be very, very alone. It will be quiet. Maybe too quiet. Wake up. Look at the support Xilinx has for its users! Not just the features (although again, I feel we are now three generations ahead there, too). Use the hotline (or if a student, use the university support system -- a hotline just for students alone via email). As for HDL's: don't learn a non-standard language, learn verilog or VHDL. I have many here who are "schematic-saurs" ( I am one as well!) and they (me) have all now taken a verilog classes. You may still do schematics with our tools, it is just that it gets so hard to keep track of the millions of gates in the larger designs. Something like 95% of all new designs are in HDL's. Want a job? -- learn the HDL's, and not the non-standard one! Austin Lesea Principal Engineer ICDES APG Xilinx thomas daehler wrote: > Hello > > As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) > -Chips are mask programmable (by third party) > Xilinx advantages: > -Cheaper boot proms > > Has anyone compared these two devices and can give me > further hints about advantages / disadvantages? > The amount of RAM and Logic blocks, the pricing and even > the archictecture seem to be almost the same for both devices. > Is that right? > > ThomasArticle: 33157
Ray, Virtex II was designed with SEU's in mind, so there are a few new features. 1. It takes two SEU's to set an input to an output, or an output to an input. This prevents crashing buses, contention, etc. 2. The SRL16/LUT RAM is in its own column (2 of the 22 for the CLB's) so that readback and checking of the CLB configuration does not disturb the SRL/LUT ram. If the LUT is not being used dynamically, it too can be read back without disturb. 3. The power on circuits are more robust (doesn't help is the SEU forces a PROG cycle .....). 4. The internal configuration access allows the design itself to have its own check logic running along with the application in a synchronous fashion. And, a comment: at geometries smaller than .22u (classic Virtex), it is much more difficult to control upsets. The EPI layer is ineffective at some point, and other techniques must be sought. It is our belief that we must use the best technology AND the best system design techniques as you describe (vectors, checking, checksums, readbacks, re-configuration, configuration refresh, etc) if a reliable system is to be realized. Please consult with the QPRO program here at Xilinx before using any Xilinx part in an application where there is a risk to life or property. There is a disclaimer that is pretty standard int he industry to make the lawyers happy (in the on-line catalog), and everyone doing such a design should read the fine print. Austin Ray Andraka wrote: > The configuration memory in FPGAs is more robust than typical SRAM, so you will > see less frequent upsets for a give exposure level. Still, in a safety critical > application where you would normally monitor a circuit's health, you'll want to > verify that the chip is operating correctly. This can be done through a > combination of test vectors, redundancy (voting) and configuration readback. > There is a considerable amount written about this in various space electronics > journals/conference proceedings. You generally will see data path upsets before > you see configuration upsets. Configuration upsets can also be reduced by using > a QPRO part, which has an epi layer. Of course that means you are limited to > essentially a Virtex1000-4 (no E, no II), but if safety is your prime concern > this is probably the way to go. > > For configuration readback, there are some gotchas you will need to be aware of > in Virtex-E, which I am not sure got fixed in virtexII. As stated in the data > sheet, you can't readback Block RAM while it is being used, and you can't read > CLBRAM or SRL16s while the write enable is high. Additionally, reading back > cells configured with SRL16's or CLBRAM while the clock is running corrupts the > configuration of the CLB (not just the memory contents). If you are using the > SRL16's and/or CLBRAM, you need to be very careful to not readback columns > containing those elements while the clock is running. > > I a current design slated for a low earth orbit, we are getting around that by > running test vectors through the design between valid data packets. Processed > data is not used until after the next test vector validation cycle ompletes, > verifying the circuit was not corrupted during the processing. You could also > use triple mode redundancy to detect circuit/data problems and correct based on > that... in our case the available number of logic cells and available power did > not permit the TMR. > > Jon Harrison wrote: > > > Hi, > > > > We are starting out on a new design for an airborne application, which will > > employ a large numer of Virtex-E/II FPGAs. The issue of safety > > classification has raised it's head, and whether the volatility of SRAM > > FPGAs constitutes an intrinsic hazard. Conventionaly with SRAM devices which > > hold program information in microprocessor based systems this is addressed > > by the use of continuous memory testing and checksumming. > > > > Has anyone else crossed this thorny issue yet ? Guidance as to any > > procedures / processes followed would be useful. > > > > We would propose to address this issue by using device readback to allow > > checksumming of the configuration data - has this been found to be > > acceptable eleswhere ? > > > > Cheers, > > > > Jon > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 33158
Ray Andraka schrieb: > > single unit pricing From www.avnetmarshall.com/dynamic/search: > > XC2S15-5VQ100 $8.96 > XCS10XL-4VQ100 $12.76 > > These are the cheapest I saw for each part. The XC2S15 gives you 384 LUTs plus 4 > block RAMs at 3/4 the price of the XCS10, which has 392 LUTs. You give up all of > 8 LUTs, but gain 4 block RAMs, SRL16 capability (which is big in my book), faster > clocks, later technology and a longer time horizon. I'll give up the 8 LUTs for > all that, especially considering the price difference. Besides, I can use the 4 > dual port block rams as 8 big LUTs if I wanted to. >From the technical point of view, I totally agree. But there are sometimes other reasons to choose Spartan over Spartan-II. If someone develops for a big company, which has good price conditions from Xilinx (Quantity), then you should (must) choose Spartan. Single unit pricing isnt applicable here. -- MFG FalkArticle: 33159
John Smith schrieb: > > I'm looking for a small processor core that fit in a 'cheap' fpga > leaving some space for IO. > Free or for little cost preferred. www.free-ip.com www.fpgacpu.org -- MFG FalkArticle: 33160
I needed two 12 bit signed data by 8 bit signed coefficient multipliers for an XCV50 design. I assumed the constant, parallel, reloadable (stop during reload) with maximum pipelining would give me a small, fast result. I can afford some time in h-blanking to reload the coefficients. The result was large and slow. When I went to a parallel, non constant pipelined multiplier it was quite a lot smaller and faster. This was a surprise. Any explanations? I thought the constant multiplier was supposed to be more economical than the full multiplier, Also, in the non-constant multiplier the "LOADB" pin is still there. Why is this? I don't see why this is needed. Is it only a clock enable on the B input? Thanks Pete FraserArticle: 33161
Wolfgang Loewer wrote: > > Hi Russell, > > try to do a functional compilation and simulation, which doesn't give you > timing information but preserves all combinatorial nodes. In the MAX+plus II > compiler go to PROCESSING and turn on FUNCTIONAL SNF EXTRACTOR. Thanks WL, that worked:) > The following is from the solutions database on the Altera web. I searched > for "node simulation" > > Problem > Why can't I find my node name during simulation? > > Solution > There are two reasons your node may not appear in the simulation file: > 1) Your node may not appear in the simulation file if it has been renamed by > the MAX+PLUSŪ II software. To prevent the MAX+PLUS II software from changing > node names, turn on the Preserve All Node Name Synonyms command (Processing > menu) in the MAX+PLUS II Compiler and recompile your project. For functional > simulation, all nodes are visible if this option is turned on > 2) The Compiler combines combinatorial nodes into logic cells during > synthesis. Therefore, some combinatorial nodes will not be available during > timing simulation. > > Regards > Wolfgang Loewer > http://www.elca.de > > Russell Shaw <rjshaw@iprimus.com.au> wrote in message > news:3B551BCA.7B5F13BD@iprimus.com.au... > > Hi all, > > > > With this bit of code: > > > > > > SUBDESIGN Test( > > Ain: input; > > Dout: output; > > ) > > > > variable > > link: node; > > > > BEGIN > > link=Ain; > > Dout=link; > > END; > > > > > > After i compiled it and load the nodes into the waveform editor, > > buried nodes such as 'link' aren't there. On bigger designs, lots > > of buried nodes aren't there. How do i get them too? -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33162
We're upgrading a few of our old 800 MHz PIII machines to speed Xilinx design. Has anybody published benchmarks to indicate if we'd be better of with fast Athlons or Fast P 4s? Thanks.Article: 33163
www@plexus-technologies.com (Dean) wrote > I want to build a simple state machine .... Here's a good way to learn how to make a state machine and to learn VHDL in general: Get a copy of Aldec Active HDL with a free 20-day license from http://www.aldec.com Aldec has a graphical state machine editor that generates VHDL code. Use the state machine editor to construct the state machine you want (or use their tutorial state machine). Compile to VHDL and use the result as an example for understanding how VHDL works. In the long run, things like state machine editors are marginally useful, since it's faster to just write VHDL. But for learning, it's a very useful tool.Article: 33164
Hi Robert,
> to my knowledge, XILINX RAM/ROM blocks must *ALWAYS* be instantiated
> and cannot be automatically inferred during RTL synthesis
> (at least this is the case for FPGA compiler). The contents of
> instantiated 16x1RAM/ROM can then be initialized using the INIT attribute.
I've also a 'real' ram in my design that is compiled to a Xilinx ram block.
The code ist just:
type mem_type is array (0 to 255) of std_logic_vector(width-1 downto 0);
signal mem : mem_type;
...
if (wr_ena = '1') then
mem(conv_integer(unsigned(wraddr))) <= data;
end if ;
...
do <= mem(conv_integer(unsigned(rdaddr)));
> XILINX LUT's can be either used as 4-input function
> generators or as 16x1 RAM. In case your 'addr' parameter was
> 4bits wide (16 possible case alternatives) and signal q is n bits wide,
> you would get a synthesis result of n parallel LUT's
> (function generators) which is exactly the same as n parallel 16x1 bit
> RAM's.
> So in this case you couldn't improve on your design using RAM's.
Normally I would not care if it is implemented in a LUT or a ram block,
but the design does not fit, because of the extensive use of the LUTs
although there are 4 ram blocks unused.
For a larger block I think it's a performance difference (But I don't
know for shure because thats the first try with Xilinx FPGAs)
I would like to keep my design without specific code for Xilinx.
It is currently Altera specific (you guess: the ram blocks) :-(
and I'm trying to get one source base which compiles on both
architectures.
Martin
--
Whant to see the evolution of a Java processor?
http://www.jopdesign.com
Article: 33165
Hi Ekram,
Thanks for the sample, but isn't there a way to code this architecture
independent. I would like to use the code for Altera and Xilinx
FPGAs.
Martin
--
Whant to see the evolution of a Java processor?
http://www.jopdesign.com
Article: 33166Thanks for the links. A lot to check out. JohnArticle: 33167
The web pack doesn,t (AFAIK) infer block ROM. Use coregen to generate a ROM macro and instantiate that. Martin Schoeberl wrote: > I have a simple VHDL code like: > > process(addr) begin > > q <= x"84ff"; -- not impl loop > case addr is > when x"0000" => q <= x"8200"; -- nop > when x"0002" => q <= x"d2ff"; -- iconst_m1 > when x"0003" => q <= x"d200"; -- iconst_0 > when x"0004" => q <= x"d201"; -- iconst_1 > when x"0005" => q <= x"d202"; -- iconst_2 > .... > > to implement a ROM. > But WebPACK produces LUT's and does not use the internal ram blocks. > As a result the design does not fit. > Any suggestion how to give the sysnth. or map tool a hint to use the ram > block? > > Thanks > Martin > -- > Whant to see the evolution of a Java processor? > > http://www.jopdesign.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33168
thomas daehler wrote: > > Hello > > As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) Xilinx has schematics too. But if you're doing HDL, the free/low cost Altera OEM versions of synthesis and simulation software are superior to X. > -Chips are mask programmable (by third party) If you ever sell 100,000 widgets. > Xilinx advantages: > -Cheaper boot proms You can also load either device from uP flash. > Has anyone compared these two devices and can give me > further hints about advantages / disadvantages? > The amount of RAM and Logic blocks, the pricing and even > the archictecture seem to be almost the same for both devices. > Is that right? The parts are roughly equivalent. Call a local distributor and ask for two samples of each part to test availability. Parts you can get are always better than those you can't. Get a quote for 5000 on both parts. See if someone will come load software on your machine. --Mike TreselerArticle: 33169
Ben Franchuk wrote: > Nial Stewart wrote: > > > > Ray Andraka wrote: > > > > > > Yep, somewhere around 15 million marketing gates worth this past year, all in > > ^^^^^^^^^^^^^^^ > > > > How many real gates is that then Ray? > > Probably should have said "equivalent gates", which is the number reported by the PAR tools. The number is a little hard to translate because it doesn't really take into account the combinatorial logic. This is 14 chip designs, mostly in pretty full V1000/2000E parts. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33170
Martin, You have the form, fit and functionally compatible XCR3032XL-10PC44C. This device is a pin-for-pin replacement. It is a 3V part, while the XCR5032C is powered by 5V. The design needs to be retargeted to the XCR3032XL (they are not JEDEC file compatible - this would be done using WebPACK/WebFITTER). You wouldn't necessarily have to delay publishing or re-write, just add a bit about targeting the correct device (5V or 3.3V). A demo board change (if you have one), is usually pretty easily accomplished either by adding a resistor to lower the supply out of the regulator or changing the regulator itself. Hope this solution will work for you. Regards, Patrick Kane Xilinx University Program Martin Rice wrote: > Having just written some teaching materials based on the 5032 ISP device, I find the part has disappeared. Do I have to re-write everything, and design a new target board?Article: 33171
"Pete Fraser" <pete@rgb.com> wrote: >We're upgrading a few of our old 800 MHz PIII machines >to speed Xilinx design. > >Has anybody published benchmarks to indicate >if we'd be better of with fast Athlons or Fast P 4s? I haven't seen specifically synthesis & PAR benchmarks but I have looked at many other application benchmarks. I think the most comparable ones are graphics apps which are integer processing heavy. In almost all the benchmarks I have seen a 1.2 GHz Athlon is at least as fast as a 1.7 GHz P4 except when the code is specifically optimized for SSE/SSE2 for P4. I think a 1.4 Athlon with PC2100 DDR is by far the best choice not even considering the savings. MuzafferArticle: 33172
Incredible opportunity with Optical Startup that's actually making money!! 3 big customers, including one of the largest carriers in the world. Looking for FPGA Project leader to build 3 Chips for TDM Application in NexGen box. Soup-to-nuts. You're the chief. Substantial salary and equity. Northern MA. contact fdv@employmentconsulting.comArticle: 33173
sandeep schrieb: > > Hello everybody, > Myself is Sandeep,and is a Post Graduate student and > doing dissertation in JPEG baseline image compression using VLSI. > I have written a code for 2-D DCT using VHDL and simulated it, but hte > problem is that it is not fitting in any of the CPLD or FPGA. I have > used Xilinx 2.1 tool.Is there any solution to this problem?????????/ > My doubt is that while writing the code is it necessary to take in to > consideration the internal architecture of the FPGA or CPLD??? If yes > then in which manner???????/ Hmm, VHDL looks a little bit like C, or better Pascal. This tempts programmers (especially the software guys) to write just the logic structure they want, without thinking (or knowing) how this translates to hardware. The same sad procedure that created "Hello World" programms requireing 10 MB Ram and 300+ MHz processors :-0 Dont get me wrong, I dont want to kick your ass, but when programming in VHDL, one should "see" the hardware behind the copde, at least do a degree. I cant say with a few word, how to make it fit. But I do know, that there are many DCTs out there and the DO fit well into the FPGAs (not CPLDs, the devices are really small). Btw, what means does not fit into any FPGA?? Tried the Virtex-E series? With the 3.2 million gate device? IF your code doesnt fit in there, you really messed something up. Have a look at this sites. www.fpgacpu.org www.free-ip.com -- MFG FalkArticle: 33174
In article <n6mbltolkeumv9iip824a556tiei0bbuj6@4ax.com>, Muzaffer Kal <muzaffer@dspia.com> wrote: >I haven't seen specifically synthesis & PAR benchmarks but I have >looked at many other application benchmarks. I think the most >comparable ones are graphics apps which are integer processing heavy. >In almost all the benchmarks I have seen a 1.2 GHz Athlon is at least >as fast as a 1.7 GHz P4 except when the code is specifically optimized >for SSE/SSE2 for P4. I think a 1.4 Athlon with PC2100 DDR is by far >the best choice not even considering the savings. And the savings will be significant, not just for the processor, but for the memory. RAMBUS is expensive, even with the price collapse, compared to SDRAM and DDR-SDRAM. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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