Messages from 33075

Article: 33075
Subject: Re: Book Recommendation (bit different)
From: Vladimir Dergachev <volodya@mindspring.com>
Date: Tue, 17 Jul 2001 05:24:37 -0400
Links: << >> << T >> << A >>

SAF wrote:

> Thant's absolutely mad. I checked the prices on Amazon, BooksaMillion
> and BarnesandNoble, and they're all too high. If you want, try
> ordering them from Amazon.co.uk (www.amazon.co.uk), the price there is
> close to what I got them for.
> 
> Never thought I'd see the day where something was cheaper here than in
> the US! :)
> 

You are lucky. When I wanted to get a book, the only one available (in 
Barnes'n'Noble) was "Verilog HDL", Samir Palnitkar. I like it, but it was 
the very last one and now none of the stores around here have any. 
(I checked several).

                                       Vladimir Dergachev
PS I live in NC, USA
 cheap!
>> Good for you!
>

Article: 33076
Subject: Re: Book Recommendation (bit different)
From: safahmy@hotmail.com (SAF)
Date: 17 Jul 2001 02:25:09 -0700
Links: << >> << T >> << A >>

Thant's absolutely mad. I checked the prices on Amazon, BooksaMillion
and BarnesandNoble, and they're all too high. If you want, try
ordering them from Amazon.co.uk (www.amazon.co.uk), the price there is
close to what I got them for.

Never thought I'd see the day where something was cheaper here than in
the US! :)


Gonzalo Arana <gonzaloa@sinectis.com.ar> wrote in message news:<3B538661.B1F956@sinectis.com.ar>...
> Hi,
> 
> SAF wrote:
> > 
> > OK,
> > 
> > After spending 3 hours in the biggest bookshops in town (the
> > world-famous Foyles, Waterstones and some new joint), I managed to
> > find the following two titles, which I bought:
> > 
> > Yalamanchili, Sudhakar (2001) "Introductory VHDL: From Simulation to
> > Synthesis" includes Xilinx Student Edition 2.1i - Only £25! (about
> > $37) It seems a pretty good book too.
> 
> Is it this one (ISBN: 0130809829)?
> http://www.amazon.com/exec/obidos/tg/stores/detail/-/books/0130809829/contents/ref=pm_dp_ln_b_2/104-5678861-7531964
> 
> > 
> > Zwolinski, Mark (1997) "Digital System Design with VHDL" - £30 (about
> > $45) Good because it stradles the digital systems and VHDL borders,
> > explaining both.
> 
> Is it this book (ISBN: 0201360632)?
> http://www.amazon.com/exec/obidos/tg/stores/detail/-/books/0201360632/contents/ref=pm_dp_ln_b_2/104-5678861-7531964
> 
> > 
> 
> You got them really cheap!
> Good for you!

Article: 33077
Subject: Re: I NEED XILINX FOUNDATION PROFESSIONAL
From: dottavio@ised.it (Antonio)
Date: 17 Jul 2001 02:42:37 -0700
Links: << >> << T >> << A >>

I had the same problem, you have to search well on Xilinx site, there
is the page of documentation where you can require the Xilinx
Foundation ISE 3.3 , they'll send it free to your home, may'be
together with Xtreme DSP , in any way the fastest solution is to ask
the evaluation CD to xilinx representative in your country, Good luck

Article: 33078
Subject: Re: PROBLEM!!!
From: "Stefaan Vanheesbeke" <stefaan.vanheesbeke@planetinternet.be>
Date: Tue, 17 Jul 2001 13:30:50 +0200
Links: << >> << T >> << A >>

Do you have a network connected?

There is a problem with W2k if you want to read the NIC without a network
connected. There is a way to solve it, but is not working properly.

I had the same problem with the Altera Quartus software on win 2000 (they
are using the same license manager). The only way to fix it in my case was
to connect a network.


This is the explanation of the problem according to Altera

7. If you are running the Quartus II software under the
Windows 2000 operating system using a single-user (node-locked)
license that is locked to a network interface card number
(NIC ID), and are not physically connected to the network, the
Quartus II software will not be able to determine your NIC ID
and will not allow you to compile a design. You should follow
the recommendations given on the following Microsoft Knowledge
Base web page:
http://support.microsoft.com/support/kb/articles/Q239/9/24.asp

This problem also occurs if you are running a FLEXlm license
server under the Windows 2000 operating system with a license
bound to the NIC ID.


"Tomek" <tbednar@poczta.onet.pl> wrote in message
news:3b53dcc1$1@news.vogel.pl...
> Hi,
> I have a problem. I want to work Xilinx Foundation under Windows 2000, but
> program lmutil.exe return bad hostid.
> I have license on my net card but lmutil return no correct net card
number.
> I worked under WinNT and everything was OK.
> What can I do to run Xilinx Foundation?
>
> Tom
>
>

Article: 33079
Subject: Re: conditional expression optimization
From: pwomack@engage.com (bugbear)
Date: 17 Jul 2001 04:57:30 -0700
Links: << >> << T >> << A >>

Jon <jschneider@cix.ceeowe.ewekay> wrote in message news:<ulmlonciy.fsf@cix.ceeowe.ewekay>...
> pwomack@engage.com (bugbear) writes:
> 
> > (a eq 10 and a eq 30)
> > 
> > Is there a name for this optimisation?
> 
> Constant folding ?

It doesn't look the same to me: Here's a page
on constant folding.
http://cs.wpi.edu/~kal/PLT/PLT10.3.2.html
It seems to be slightly different.

Optimising "my" expression requires the detection
of a proprty of the expression, as well as constantness(sp ?).
Consider this:

	(a eq b and a eq b + 1)

Or even 

	(a eq b and a ne b)

Also optimisable, and the last one has no constants...

	BugBear

Article: 33080
Subject: processor core
From: xyz1625us@yahoo.com (John Smith)
Date: 17 Jul 2001 05:05:47 -0700
Links: << >> << T >> << A >>

I'm looking for a small processor core that fit in a 'cheap' fpga
leaving some space for IO.
Free or for little cost preferred.

Thanks
John

Article: 33081
Subject: Re: Xilinx .bit file format
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Tue, 17 Jul 2001 14:04:22 +0100
Links: << >> << T >> << A >>

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Hi Dave,

If you are loading the bitstream using master or slave serial mode then this
should not make a difference. However, if you are using a uP
to download the bitstream, I assume you are counting on a specified number of
clock cycles. In this case changing the code of the uP will do
the trick.

My 2 cents worth.

Stephan

Dave Brown wrote:

> I have a .bit file that I converted to a .hex file with PromGEN. When I look
> at this .hex file, I noticed there is only one 32 bit dummy word before the
> syncronization word. I read in XAPP176 (from the Xilinx website) that there
> are supposed to be 2 32 bit dummy words. Has anyone else had similar
> problems? Just curious, because we can't get this .bit file to load into the
> FPGA. Is there a definitive description somewhere of the header that a .bit
> file should have for a Spartan II?
> Thanks,
> Dave

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--------------AC24FA98CA7B348B4191A893--

Article: 33082
(removed)

Article: 33083
(removed)

Article: 33084
Subject: Coolrunner: availability
From: "Martin Rice" <jmrice@ntlworld.com>
Date: Tue, 17 Jul 2001 06:35:56 -0700
Links: << >> << T >> << A >>

Having just written some teaching materials based on the 5032 ISP device, I find the part has disappeared.  Do I have to re-write everything, and design a new target board?

Article: 33085
Subject: Unconnected nets
From: "Noddy" <g9731642@campus.ru.ac.za>
Date: Tue, 17 Jul 2001 16:39:51 +0200
Links: << >> << T >> << A >>

Hi,

I've got a problem with design implementation. I have two filters which have
there inputs connected to a digital mixer, and outputs go into a truncation,
where I take the 4 MSB. Anyway, the whole thing works fine in the logic
simulator, and I have named all my nets nicely etc. but upon implementation,
the implementation log report gives a number of nets which it says has no
load or unconnected, and so it doesn't route.

I can't seem to locate these so-called unconnected nets anywhere. Anyone
have some ideas?

Adrian

Article: 33086
Subject: Interpolating Filter question
From: dottavio@ised.it (Antonio)
Date: 17 Jul 2001 07:46:55 -0700
Links: << >> << T >> << A >>

Good Morning, my question is this  :
Matlab design for me a polyphase filter using the function rcosflt ,
the number of coefficient produced is function of the interpolation
rate (...why ??) in particular for interpolation 3 I've 19
coefficients, for interpolation 4 I've 25 coefficients and for
interpolation 6 I've 37 coefficients .
This means that I always have 1 fir with 7 taps and
(interpolation_rate -1) filters with 6 taps , so I had think to
produce only one polyphase filter that interpolate 6 and when I want
to interpolate 3 I use the first 3 FIR, when I want to interpolate 4 I
use the first 4 FIR and when I want interpolate & I use all 6 FIR ,
naturally the coefficients are programmable.
I would want to ask you if this is correct by your point of view ...

Thank you in any case ...


Antonio D'Ottavio

Article: 33087
Subject: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
From: Paul Graham <grahamp@ee.byu.edu>
Date: Tue, 17 Jul 2001 09:10:08 -0600
Links: << >> << T >> << A >>

I have created a Web page describing how to use the Xilinx Alliance
3.1i/3.3i tools under Linux using Wine.  The URL is:

http://splish.ee.byu.edu/tutorials/linux-alliance/linux-alliance.html

This publicly available Web page describes the complete installation
process as well as how to set up users' environments to run the tools.
I also have included sections on how to run the Xilinx tools under
Wine and some of the caveats and work-arounds I have encountered.

The great news is that the Xilinx Alliance tools install nicely under
Wine now as do the Service Packs and Device Updates, so creating and
maintaining the installations has become much easier.

If you encounter any problems with my instructions, let me know.  I
have tried to be as complete as possible and have tested the
instructions fairly well, but there is always room for improvement.

Enjoy,

Paul
=====================================
Paul Graham (grahamp@ee.byu.edu)
459 CB, Electrical Engineering Dept.
Brigham Young University
Provo, Utah 84602

Article: 33088
Subject: Re: processor core
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Tue, 17 Jul 2001 15:19:14 GMT
Links: << >> << T >> << A >>

take a look at: http://www.jopdesign.com
a java processor

Martin

"John Smith" <xyz1625us@yahoo.com> schrieb im Newsbeitrag
news:8c835672.0107170405.224a2753@posting.google.com...
> I'm looking for a small processor core that fit in a 'cheap' fpga
> leaving some space for IO.
> Free or for little cost preferred.
>
> Thanks
> John

Article: 33089
Subject: Re: Unconnected nets
From: Stephan Neuhold <stephan.neuhold@xilinx.com>
Date: Tue, 17 Jul 2001 16:33:17 +0100
Links: << >> << T >> << A >>

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Hi Adrian,

My guess is, since you are only using the 4 MSBs of the data, the 4 LSBs are
being optimised out. The implementation tools would
see these as either "dangling" or "unconnected nets" or "loadless nets". Try
connecting the 4 LSBs to output pins and rerun
implementation. Just a thought.

SN

Noddy wrote:

> Hi,
>
> I've got a problem with design implementation. I have two filters which have
> there inputs connected to a digital mixer, and outputs go into a truncation,
> where I take the 4 MSB. Anyway, the whole thing works fine in the logic
> simulator, and I have named all my nets nicely etc. but upon implementation,
> the implementation log report gives a number of nets which it says has no
> load or unconnected, and so it doesn't route.
>
> I can't seem to locate these so-called unconnected nets anywhere. Anyone
> have some ideas?
>
> Adrian

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Article: 33090
Subject: Help me please in one test.
From: <kodtest99@yahoo.com>
Date: Tue, 17 Jul 2001 15:41:45 GMT
Links: << >> << T >> << A >>

This is test.
Answer me please for test message.
Thanks,
Robert.

 ----------------------------------
| FREE Vacation!  FANTASNIC offer! |
|                                  |
|  http://linkresort.fasturl.it    |
 ----------------------------------

Article: 33091
Subject: Re: PROBLEM!!!
From: Dave Colson <dscolson@rcn.com>
Date: Tue, 17 Jul 2001 11:42:47 -0400
Links: << >> << T >> << A >>

Tom,

Try updating the lmutil from globetrotter. I have had similar problems. Usually
this will fix the problem.
http://www.globetrotter.com/

Dave C

Tomek wrote:

> Hi,
> I have a problem. I want to work Xilinx Foundation under Windows 2000, but
> program lmutil.exe return bad hostid.
> I have license on my net card but lmutil return no correct net card number.
> I worked under WinNT and everything was OK.
> What can I do to run Xilinx Foundation?
>
> Tom

Article: 33092
Subject: MCS file format
From: "Dave Brown" <dbrown@novatel.ca>
Date: Tue, 17 Jul 2001 09:47:58 -0600
Links: << >> << T >> << A >>

Using PROMGen I made an MCS format file and have tried loading this into a
SpartanII, and it's not working. I opened up the MCS file and looked at it,
and I noticed that the intial dummy word and synchronization word is listed
as FFFFFFFF5599AA66. This looks wrong to me, the sync word is supposed to be
AA995566. I've looked at several MCS files, and they all have the sync word
as 5599AA66. Is this correct? The FPGA configuration doesn't get past the
sync word when using PROMs that have this MCS file.
Thanks,
Dave

Article: 33093
Subject: Re: PROBLEM!!!
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 17 Jul 2001 09:56:37 -0600
Links: << >> << T >> << A >>

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I too had a similar problem on my laptop.  Licenses worked when I was connected
to the network but when unconnected, the NIC address seemed to disappear.  If
this is your problem as well, the steps laid out in the following record fixed
it for me: http://support.xilinx.com/techdocs/11347.htm  In short, if you
install the NWLink IPX/SPX Compatible Transport Network Protocol, it seems to
allow the flexlm software to get the hostid without a network connection.  I can
thank a Xilinx FAE for showing me that one.


--  Brian





Stefaan Vanheesbeke wrote:

> Do you have a network connected?
>
> There is a problem with W2k if you want to read the NIC without a network
> connected. There is a way to solve it, but is not working properly.
>
> I had the same problem with the Altera Quartus software on win 2000 (they
> are using the same license manager). The only way to fix it in my case was
> to connect a network.
>
> This is the explanation of the problem according to Altera
>
> 7. If you are running the Quartus II software under the
> Windows 2000 operating system using a single-user (node-locked)
> license that is locked to a network interface card number
> (NIC ID), and are not physically connected to the network, the
> Quartus II software will not be able to determine your NIC ID
> and will not allow you to compile a design. You should follow
> the recommendations given on the following Microsoft Knowledge
> Base web page:
> http://support.microsoft.com/support/kb/articles/Q239/9/24.asp
>
> This problem also occurs if you are running a FLEXlm license
> server under the Windows 2000 operating system with a license
> bound to the NIC ID.
>
> "Tomek" <tbednar@poczta.onet.pl> wrote in message
> news:3b53dcc1$1@news.vogel.pl...
> > Hi,
> > I have a problem. I want to work Xilinx Foundation under Windows 2000, but
> > program lmutil.exe return bad hostid.
> > I have license on my net card but lmutil return no correct net card
> number.
> > I worked under WinNT and everything was OK.
> > What can I do to run Xilinx Foundation?
> >
> > Tom
> >
> >

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Article: 33094
Subject: Re: processor core
From: Veronica Merryfield <Veronica.Merryfield@tesco.net>
Date: Tue, 17 Jul 2001 17:03:05 +0100
Links: << >> << T >> << A >>

Take a look at http://www.fpgacpu.org/ and roll your own!

John Smith wrote:

> I'm looking for a small processor core that fit in a 'cheap' fpga
> leaving some space for IO.
> Free or for little cost preferred.
>
> Thanks
> John

Article: 33095
Subject: Re: processor core
From: Brian Philofsky <brian.philofsky@xilinx.com>
Date: Tue, 17 Jul 2001 10:04:04 -0600
Links: << >> << T >> << A >>

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John,

   If you are planning to target a Xilinx FPGA, there is a list of
free and pay-for uP cores on the Xilinx website in the Processor
Central sections:
http://www.xilinx.com/xlnx/xil_prodcat_product.jsp?title=soft_processor_cores

Select a link at the bottom of that page for a list of those types of
processors.

You could see if any of those fit your needs.  There are several
other availible as well scattered across the net.  You may also want
to try a Google search to see what you may find.

--  Brian



John Smith wrote:

> I'm looking for a small processor core that fit in a 'cheap' fpga
> leaving some space for IO.
> Free or for little cost preferred.
>
> Thanks
> John

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Article: 33096
Subject: Re: PROBLEM!!!
From: Dave Colson <dscolson@rcn.com>
Date: Tue, 17 Jul 2001 13:36:39 -0400
Links: << >> << T >> << A >>

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BTY I have had this problem with the network connected.

Dave Colson wrote:

> Tom,
>
> Try updating the lmutil from globetrotter. I have had similar problems. Usually
> this will fix the problem.
> http://www.globetrotter.com/
>
> Dave C
>
> Tomek wrote:
>
> > Hi,
> > I have a problem. I want to work Xilinx Foundation under Windows 2000, but
> > program lmutil.exe return bad hostid.
> > I have license on my net card but lmutil return no correct net card number.
> > I worked under WinNT and everything was OK.
> > What can I do to run Xilinx Foundation?
> >
> > Tom

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
BTY I have had this problem <u>with</u> the network connected.
<p>Dave Colson wrote:
<blockquote TYPE=CITE>Tom,
<p>Try updating the lmutil from globetrotter. I have had similar problems.
Usually
<br>this will fix the problem.
<br><a href="http://www.globetrotter.com/">http://www.globetrotter.com/</a>
<p>Dave C
<p>Tomek wrote:
<p>> Hi,
<br>> I have a problem. I want to work Xilinx Foundation under Windows
2000, but
<br>> program lmutil.exe return bad hostid.
<br>> I have license on my net card but lmutil return no correct net card
number.
<br>> I worked under WinNT and everything was OK.
<br>> What can I do to run Xilinx Foundation?
<br>>
<br>> Tom</blockquote>
</html>

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Article: 33097
Subject: Xilinx System Generator V1.0 question
From: "JianYong Niu" <cop00jn@shef.ac.uk>
Date: Tue, 17 Jul 2001 19:14:47 +0100
Links: << >> << T >> << A >>

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Hi, all. I met a problem while systhesize the VHDL files generated by =
Xilinx System Generator. The design is the 'integrate' example attached =
with the SysGen software. The synthesis and P&M tool is Xilinx =
Foundation series 3.1i.

After the preject was synthesized, the following warning were generated:

"Warning: The value '1' of the duplicate instance property =
'syn_black_box' is ignored
Warning: the value 'true' of the duplicate instance property =
'fpga_dont_touch' is ignored
...
"
What is worse is that the Map&Place was suspended with fatal error as:
"ERROR:NgdBuild:456 - logical net 'integrity_Gateway_Out_valid' has both =
active
   and tristate drivers"

By checking the top level entity 'integrity', It was surprising to find =
that the output port of the entity 'integrity_Gateway_Out_valid' and =
'integrity_Gateway_Out' were specified as 'inout' rather than 'out'!! =
What is the problem?

entity integrity is=20
  generic (
    integrity_Gateway_In_arith: integer :=3D xlSigned;
    integrity_Gateway_In_bin_pt: integer :=3D 0;
    integrity_Gateway_In_width: integer :=3D 8;
    integrity_Gateway_Out_arith: integer :=3D xlUnsigned;
    integrity_Gateway_Out_bin_pt: integer :=3D 0;
    integrity_Gateway_Out_width: integer :=3D 8
  );
  port (
    ce: in std_logic;
    clk: in std_logic;
    clr: in std_logic;
    integrity_Gateway_In: in std_logic_vector =
(integrity_Gateway_In_width - 1 downto 0);
    integrity_Gateway_In_valid: in std_logic;
    integrity_Gateway_Out: inout std_logic_vector =
(integrity_Gateway_Out_width - 1 downto 0);
    integrity_Gateway_Out_valid: inout std_logic
  );
end integrity;

Anybody met similiar problem as above? if there are, how do u guys fix =
it?

Thanks a lot in advance.

Jianyong




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</HEAD>
<BODY>
<DIV><FONT face=3DArial size=3D2>Hi, all. I met a problem while =
systhesize the VHDL=20
files generated by Xilinx System Generator. =
The&nbsp;design&nbsp;is&nbsp;the=20
'integrate' example attached with the SysGen software.&nbsp;The =
synthesis=20
and&nbsp;P&amp;M tool is Xilinx Foundation series 3.1i.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>After the preject was&nbsp;synthesized, =
the=20
following warning were generated:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>"<FONT color=3D#ff0000>Warning: The =
value '1' of the=20
duplicate instance property 'syn_black_box' is =
ignored</FONT></FONT></DIV>
<DIV><FONT face=3DArial color=3D#ff0000 size=3D2>Warning: the&nbsp;value =
'true' of the=20
duplicate instance property 'fpga_dont_touch' is ignored</FONT></DIV>
<DIV><FONT face=3DArial color=3D#ff0000 size=3D2>...</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>"</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>What is&nbsp;worse is that&nbsp;the =
Map&amp;Place=20
was suspended&nbsp;with fatal error as:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2><FONT =
color=3D#ff0000>"ERROR:NgdBuild:456 - logical=20
net 'integrity_Gateway_Out_valid' has both active<BR>&nbsp;&nbsp; and =
tristate=20
drivers</FONT>"</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>By checking the top level entity =
'integrity', It=20
was surprising to find that the output port of the entity=20
'integrity_Gateway_Out_valid' and 'integrity_Gateway_Out' were specified =
as=20
'<FONT color=3D#ff0000>inout</FONT>' rather than '<FONT=20
color=3D#ff0000>out</FONT>'!! What is the problem?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2><FONT color=3D#ff0000>entity</FONT> =
integrity <FONT=20
color=3D#ff0000>is</FONT> <BR>&nbsp; <FONT =
color=3D#ff0000>generic</FONT>=20
(<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_In_arith: integer :=3D=20
xlSigned;<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_In_bin_pt: integer =
:=3D=20
0;<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_In_width: integer :=3D=20
8;<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_Out_arith: integer :=3D=20
xlUnsigned;<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_Out_bin_pt: integer =
:=3D=20
0;<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_Out_width: integer :=3D =
8<BR>&nbsp;=20
);<BR>&nbsp; <FONT color=3D#ff0000>port</FONT> (<BR>&nbsp;&nbsp;&nbsp; =
ce: <FONT=20
color=3D#ff0000>in std_logic</FONT>;<BR>&nbsp;&nbsp;&nbsp; clk: <FONT=20
color=3D#ff0000>in std_logic</FONT>;<BR>&nbsp;&nbsp;&nbsp; clr: <FONT=20
color=3D#ff0000>in std_logic</FONT>;<BR>&nbsp;&nbsp;&nbsp; =
integrity_Gateway_In:=20
<FONT color=3D#ff0000>in std_logic_vector</FONT> =
(integrity_Gateway_In_width - 1=20
downto 0);<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_In_valid: <FONT=20
color=3D#ff0000>in std_logic</FONT>;<BR>&nbsp;&nbsp;&nbsp; =
integrity_Gateway_Out:=20
<FONT color=3D#ff0000><U>inout</U></FONT> <FONT=20
color=3D#ff0000>std_logic_vector</FONT> (integrity_Gateway_Out_width - 1 =
downto=20
0);<BR>&nbsp;&nbsp;&nbsp; integrity_Gateway_Out_valid: <FONT=20
color=3D#ff0000><U>inout</U></FONT> <FONT =
color=3D#ff0000>std_logic</FONT><BR>&nbsp;=20
);<BR><FONT color=3D#ff0000>end </FONT>integrity;</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Anybody met similiar problem as above? =
if there=20
are, how do u guys fix it?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Thanks a lot in advance.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2>Jianyong</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial size=3D2></FONT>&nbsp;</DIV></BODY></HTML>

------=_NextPart_000_000F_01C10EF4.BEA8FF00--

Article: 33098
Subject: Re: Coolrunner: availability
From: Richard Dungan <postmaster@[127.0.0.1]>
Date: Tue, 17 Jul 2001 19:26:21 +0100
Links: << >> << T >> << A >>

"Martin Rice" <jmrice@ntlworld.com> wrote:

>Having just written some teaching materials based on the 5032 ISP device, I find the part has disappeared.  Do I have to re-write everything, and design a new target board?

Bad luck. AFAIK the 5032 has been canned. The Atmel ATF1502 is a drop-in
replacement as long as you do not need the very low power consumption of
the 5032.

It probably comes down to what kind of design entry you have used, but I
have certainly used the Atmel parts as drop-replacements with no
problems.

Richard

------------Richard Dungan-------------
Radix Electronic Designs, Orpington, UK
   richardATradixDASHdesignDOTcoDOTuk
    Web page: www.radix-design.co.uk
---------------------------------------

Article: 33099
Subject: Drive strength of Xilinx DONE pin
From: ldoolitt@recycle.lbl.gov (Larry Doolittle)
Date: 17 Jul 2001 18:34:34 GMT
Links: << >> << T >> << A >>

I have scanned all the Spartan-II/Virtex-I documentation I can find, 
and no place can I find the drive strength of the DONE pin.  Is it 
settable in the bitstream like a user I/O [*], or does it take a 
default value, and if so, what is it?

    - Larry Doolittle   <LRDoolittle@lbl.gov>

[*] That would only half make sense.  The pull-up (when DriveDONE
is configured as documented in XAPP176) only applies after the
configuration is loaded and CRC verified.  Logically, however, the 
pull-down strength can't be configured, because that happens before 
any configuration bits are read.

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