Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Laurent Gauch wrote: > With the Xilinx Design Manager you will be able to convert easily your > EDF file to a VHD file, but this VHDL file will be difficult to use, > because it will perform the design in the technology primitives format > (Lut ... FF ...). These vhd file are used to do post-simulation (after P&R). > > Laurent > www.amontec.amontec > You don't have to go as far as P&R. Take the EDIF in through NGDBUILD, Use NGD2VHDL to produce a netlist based on the simprims primitives, then (hardish part) write a Perl script to convert the primitives to VHDL RTL code. Now you will have a totally incomprehensible but hopefully synthesisable piece of VHLD. If you are lucky the EDIF netlist has hierarchy info you can preserve with the -r (?) flag to NGDBUILD.Article: 32101
The analog devices table looks good to me. If you stay in the same quadrant the output is 00. If you rotate 90 CCW the output is 10. If you rotate 90 CW you get 01. And if you rotate 180 degrees you get 11. So you table is correct except for the (phase shift) column. > 01 | 11 > ----------- > 00 | 10 > (Current Input) (Current Output) (Next Output) (Phase Shift) > -------------------------------------------------------------------------- ------------------------- > 00 11 11 180 > 00 01 01 90 > 00 00 00 0 > 00 10 10 -90 > 01 11 01 90 > 01 01 00 0 > 01 00 10 -90 > 01 10 11 180 > 11 11 00 0 > 11 01 10 -90 > 11 00 11 180 > 11 10 01 90 > 10 11 10 -90 > 10 01 11 180 > 10 00 01 90 > 10 10 00 0 For the intel table I think you have the Next Output column and the Current Output columns reversed. You'll see that they agree with the AD table above. By the way there is no simple formula to calculate the output based on the current and previous decision. You have to use a look up table. -Clark Pope "Edward" <edlee@gpetech.com> wrote in message news:3b27b4f1.421218359@news.bctel.net... > I'm building a differential QPSK encoder using a Xilinx FPGA. I have > looked at the data sheets of many off-the-shelf encoder chips, and > each one is using a different encoding table. > > The Intel constelation and differential encoding table is like this : > > 01 | 11 > ----------- > 00 | 10 > > (Current Input) (Current Output) (Next Output) (Phase Shift) > -------------------------------------------------------------------------- ----------------------- > 00 00 00 0 > 00 01 01 -90 (CW) > 00 10 10 90 (CCW) > 00 11 11 180 > 01 00 01 -90 (CW) > 01 01 11 180 > 01 10 00 0 > 01 11 10 90 (CCW) > 10 00 10 90 (CCW) > 10 01 00 0 > 10 10 11 180 > 10 11 01 90 (CCW) > 11 00 11 180 > 11 01 10 90 (CCW) > 11 10 01 -90 (CW) > 11 11 00 0 > > > The Analog Devices is like this : > > (Current Input) (Current Output) (Next Output) (Phase Shift) > -------------------------------------------------------------------------- ------------------------- > 00 11 11 0 > 00 01 01 0 > 00 00 00 0 > 00 10 10 0 > 01 11 01 90 > 01 01 00 90 > 01 00 10 90 > 01 10 11 90 > 11 11 00 180 > 11 01 10 180 > 11 00 11 180 > 11 10 01 180 > 10 11 10 270 > 10 01 11 270 > 10 00 01 270 > 10 10 00 270 > > > If I use the encoding formula, > > next output = current input (xor) current output > > to verify the table data, the Intel table is totally wrong. But the > AD table is not 100% correct. The two entries, (01- 11 - 01) and > (10 - 11 - 10), should be, (01 - 11 - 10) and (10 - 11 - 01), > according to the above formula. > > In addition, the phase shift part of the AD table is reasonable. But > I cannot make any sense out of the Intel phase shift part. > > What should be the correct table (formula and phase shift) for > encoding differential QPSK data ? > > Can someone shed me some light on this ? Thanks. > > > Edward > >Article: 32102
Sony (www.sel.sony.com) has a real-time MPEG chip that looked very good. Also, check out C-Cube (www.c-cube.com). All MPEG solutions are lossy. If you watch DVDs, however, you will agree that the compression is hardly noticeable. "Jason Daughenbaugh" <jad@aedinc.net> wrote in message news:368276e0.0106121152.3e69be8f@posting.google.com... > Hello all, > > I am looking for any information on video compression/decompression > on an FPGA. I am interested in IP cores, papers on implementation, > etc. I don't want algorithms that are too lossy - lossless or near > lossless are all I can consider. JPEG-2000, JPEG-LS, or others. Can > MPEG-4 or MPEG-7 be near-lossless? > > We want to be able to process 24 bit RGB at 45Mpix/s or faster. I > don't think that DSPs can do it, a massively parallel FPGA > architecture or an ASIC are probably the only choices. > > I have looked at the ADV-JP2000 Codec. It is a cool IC, but can only > do 10Mpix/s (with only one color component, slow with more?). I would > also be interested in any similar chips (but faster) that might be > able to do this processing, and then I could glue it to an FPGA. > > I have little experience with video CODECs, so I would appreciate any > advice on where to look. > > Thanks! > Jason Daughenbaugh > http://www.aedinc.net >Article: 32103
Heinrich, It looks as though you've found a way to use a non-globacl clock for your FIFO, so I have one piece of advice: ** Don't do it!!** Nets that are not global clock nets have not-very-well-controlled skew. Which means that when your FIFO is updated, the clock is not going to get to all the flip-flops controlling your FIFO at the same time. This will cause race conditions, which will cause really wierd behavioour that is really difficult to debug. > My design > contains four FIFOs, each driven by an individual WR_CLK, and one RD_CLK > that is common to all FIFOs. Therefore I have five clocks incoming > directly from the outside, but only four GCLK inputs. The RD_CLK is fast > and is also used in many other parts, so it should be supplied from one > GCLK input, but all four WR_CLKs are much slower and drive only the > FIFOs, so they could be supplied from other inputs. If your write clocks are much slow, I would suggest re-synchronizing them to the read clock, and just using one clock in your design. Hope this helps, -KentArticle: 32104
> Anyways, I downloaded WebPACK because I'm doing an extracurricular > project that needed some sort of PLD. (You know, separation of home and > work -- don't work on home projects at work, etc.) Have you tried Xilinx Student Edition 2.1i ($55 from http://www.xess.com)? It's basically the commercial version of Xilinx Foundation 2.1i, minus the synthesis constraints editor. The package/product description says it supports up to a Virtex-50, Spartan2-150, and XC4010. In fact, the tool has full device support up to 'Foundation Express' level. That means XCV-1000/1000E, XC40xx (all devices), Spartan2-150 (alas, no Spartan2-200 support, sigh..gr...) At least I had no trouble compiling an XCV-300 design (not XCV-300E.) Assuming you don't need support for an ultra-new device, like the Coolrunner XPLA3 or such, you should try it... Downside is the project manager is a lot of legacy 16-bit code. It's horrible. Crashes often, doesn't multitask well in background, etc. I had forgotten the characteristics of 16-bit Windows apps under Win9x, but XSE1.3, 1.5 and 2.1i reminded me :) (Thank goodness Xilinx moved to a new 32-bit codebase with Foundation-ISEArticle: 32105
I'm looking for an Ethernet MAC and a 3DES core either specifically Xilinx or available as source so I can port it. Xilinx has some stuff available but: o The Ethernet stuff is only the Tx/Rx blocks & I'm looking/hoping for something more comprehensive. o The 3DES core uses 70% of the largest Spartan2. Maybe this is normal but I really need something smaller. For the 3DES - is there a good description anywhere of the algorithm viewed from a h/w perspective ? In case I have to write the code myself.Article: 32106
Hi,
I asm looking for a Floppy-Disc-Controller Core for an FPGA. Does
anybody know if soemone is selling such a core ? Is there perhaps a free
implementation available somewhere ?
Matthias
--
-------------------------------------------------
\ Matthias Fuchs \
\ esd electronic system design Gmbh \
\ Vahrenwalder Straße 205 \
\ D-30165 Hannover \
\ email: matthias.fuchs@esd-electronics.com \
\ phone: +49-511-37298-0 \
\ fax: +49-511-37298-68 \
--------------------------------------------------
Article: 32107Hello Rick, Thank you for your answer. I have tried to convert the NGD file to VHD file. I have now a nice and incomprehensible file of 29000 lines of code with all the simprims in it (and this is the smallest LCA). I tried to synthesize this file with Leonardo without converting the primitives to VHDL RTL mode (Just trying). It didn't work as you probably knew. You are talking about 'convert the primitives to VHDL RTL (using Perl, too much for me) ', what does it mean? The errors in Leonardo are : ERROR, 'X_ONE' is not a component. ERROR, 'X_AND4' is not a component. ERROR, 'X_BUF' is not a component. ... I guess this are Xilinx parts X_* and Leonardo doesn't identify them, I changed the name from X_BUF to BUF and the resutl was the same. So, that magic Perl script what should it do? Thank you in advance. Ulises Hernandez "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3B27F452.9C8CC2A2@algor.co.uk... > > > Laurent Gauch wrote: > > > With the Xilinx Design Manager you will be able to convert easily your > > EDF file to a VHD file, but this VHDL file will be difficult to use, > > because it will perform the design in the technology primitives format > > (Lut ... FF ...). These vhd file are used to do post-simulation (after P&R). > > > > Laurent > > www.amontec.amontec > > > > You don't have to go as far as P&R. Take the EDIF in through NGDBUILD, Use > NGD2VHDL to produce a netlist based on the simprims primitives, then (hardish > part) write a Perl script to convert the primitives to VHDL RTL code. > > Now you will have a totally incomprehensible but hopefully synthesisable piece of > VHLD. > > If you are lucky the EDIF netlist has hierarchy info you can preserve with the -r > (?) flag to NGDBUILD. > > >Article: 32108
Stephane, I didn't read your first posting, but it is not to hard implementing a jtag interface to the PC. I.e. by a parallel port. I am implementing one in Java for our hardware. Basically we do the same as you, we program the flash via a microcontroller with jtag. Email me directly if you wan't more information. Richard stephane wrote: > First of all, thanks to you all for answering. > > So yes it's possible !! > > This time the question comes from the software team. > As this will be controled by a PC, they would like to know what will be > the amount of work to realize a software for programming the system > flash, the EPC2 and for testing the APEX which will come in BGA. > > They argu that all the last experiences in other services were not > successful because of the difficulty to create the JTAG sequences. > > So is it so complex to implement ? > > Stephane. > Thales microelectronics. -- Quest Innovations tel: +31 (0) 227 604046 http://www.quest-innovations.comArticle: 32109
Hi all,Article: 32110
Matthias Fuchs <matthias.fuchs@esd-electronics.com> wrote in message
news:3B263EBC.C4BE0EE7@esd-electronics.com...
> Could you post the hdl code of your "IOB-primitive" ? I still have
> problems with tristate reg and io reg in the IOB !
Sorry for delay Matthias, didn't see your reply, have attached both prim &
vec for completeness - comments are a bit verbose but I've left them too.
best,
Fred (dave)
ps: I had lots of trouble in getting this to work, in the end, I opened up
FPGA editor & coded for the structure that I saw eg. the tristate control
invert function is before the tristate register, so I coded an inverter
outside (before) the clocked process - it (the tool(s)) was too dumb to
infer it but did absorb it into the dedicated IOB resource.
Code follows:
begin 666 io_oe_reg_prim.txt
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+0T*+2T@:6]?;V5?
M<F5G7W!R:6TN=FAD("A214=)4U1%4D5$($]%*0T*+2T@1&%V:60@36-,96]D
M#0HM+0T*+2T@4F5G:7-T97)E9"!I+V\@=VET:"!O92!F;W(@<VEN9VQE($E/
M0G,@;VX@6%A86%@@5FER=&5X)W,N#0HM+0T*+2T@06X@:2]O(&9U;F-T:6]N
M('=I=&@@;W5T<'5T(&5N86)L92!F;W(@82!S:6YG;&4@24]"+B!);G!U="P@
M;W5T<'5T(&%N9 T*+2T@=&AE(&]U='!U="!E;F%B;&4@8V]N=')O;"!A<F4@
M<F5G:7-T97)E9"!W:71H('-E<&%R871E(&-L;V-K(&5N86)L97,@86YD#0HM
M+2!A(&-O;6UO;B!A<WEN8VAR;VYO=7,@<F5S970@*&EN=&5N9&5D(&9O<B!S
M:6T@;VYL>2DN(%1H92!6:7)T97@@87)C:&ET96-T=7)E#0HM+2!D:6-T871E
M<R!A(&-O;6UO;B!C;&]C:R H8G5T(&YO="!P:&%S92D@86YD(')E<V5T+@T*
M+2T-"BTM($YO=&5S.@T*+2T@,2X@57-E('-I;F=L>2!O<B!W:71H(&EO7V]E
M7W)E9U]V96,N=FAD(&9O<B!W:61E('!A=&AS+@T*+2T@,BX@26YT96YD960@
M9F]R(')E9VES=&5R960@=')I<W1A=&4@9&%T82!P871H<R!E9RX@9&%T82!B
M=7-S97,N#0HM+2 S+B!4:&4@=7-E(&]F(&%N(&DO;R!P<FEM:71I=F4@:7,@
M9&EC=&%T960@8GD@9&EF9FEC=6QT>2!I;B!C;VYS=')A:6YI;F<-"BTM('1O
M;VQS('1O('!L86-E(')E9VES=&5R<R H<&%R=&EC=6QA<FQY('1R:7-T871E
M(&-O;G1R;VP@<F5G:7-T97)S*2!I;B!6:7)T97@-"BTM($E/0G,N(%1O('!L
M86-E('1H:7,@;&]G:6,@96YT:71Y(&EN('1H92!)3T(L('1H92!S>6YT:"!T
M;V]L(')E<75I<F5S('1H90T*+2T@(DE/0B(@871T<FEB=71E('1O(&)E('-E
M=" B=')U92(@7V%N9%\@=&AE(&EM<&QE;65N=&%T:6]N('1O;VP@<F5Q=6ER
M97,-"BTM(")U<V4@24]"<R(@=&EC:V5D(&]R(&%P<&QY(&UA<'!E<B!O<'1I
M;VX@(BUP<B!B(BX-"BTM(#0N(%1H92!I;G!U="!R96=I<W1E<B!A='1R=6)U
M=&4@(DY/1$5,05DB(&]R(")-141$14Q!62(@;75S="!S970@:6X@=&AE(%5#
M1@T*+2T@9FEL92!I9B!T:&4@9&5F875L="!P97)F;W)M86YC92!O9B!F=6QL
M(&1E;&%Y(&ES(&YO="!R97%U:7)E9"X-"BTM#0HM+2!$871E.B P-2\P,2\P
M,0T*+2T-"BTM(%)E=CH@," P-"\P,2\P,0T*+2T-"BTM(%)E=CH@,&$-"BTM
M($]%(')E9R!C:&%N9V5D('1O(%13(')E9R!W:71H(&5X=')A(&EN=B!T;R!S
M871I<V9Y('1O;VP@<F5Q;71S#0HM+0T*+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+0T*#0IL:6)R87)Y($E%144[#0IU<V4@245%12YS=&1?
M;&]G:6-?,3$V-"YA;&P[#0H-"F5N=&ET>2!I;U]O95]R96=?<')I;2!I<PT*
M("!P;W)T("@-"B @(" @(" @<G-T(#H@:6X@<W1D7VQO9VEC.PT*(" @(" @
M("!C;&L@.B!I;B!S=&1?;&]G:6,[#0H@(" @(" @(&1?;W5T(#H@:6X@<W1D
M7VQO9VEC.PT*(" @(" @("!D7V]U=%]C92 Z(&EN('-T9%]L;V=I8SL-"B @
M(" )"61?;W5T7V]E(#H@:6X@<W1D7VQO9VEC.PT*(" @(" @("!D7V]U=%]O
M95]C92 Z(&EN('-T9%]L;V=I8SL-"B @(" )"61?:6Y?<B Z(&]U="!S=&1?
M;&]G:6,[#0H@(" @(" @(&1?:6Y?8V4@.B!I;B!S=&1?;&]G:6,[#0H@(" @
M(" @('!I;E]D870@.B!I;F]U="!S=&1?;&]G:6,-"B @(" @(" @*3L-"F5N
M9"!I;U]O95]R96=?<')I;3L-"@T*87)C:&ET96-T=7)E(&EO7V]E7W)E9U]P
M<FEM7V%R8V@@;V8@:6]?;V5?<F5G7W!R:6T@:7,-"BTM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2T-"BTM('-I9VYA;"!D96-L87)A=&EO;G,-
M"BTM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2T-"B @<VEG;F%L
M(&1?;W5T7W(@.B!S=&1?;&]G:6,[#0H@('-I9VYA;"!D7V]U=%]T<U]R(#H@
M<W1D7VQO9VEC.PT*("!S:6=N86P@9%]O=71?=',@.B!S=&1?;&]G:6,[#0H@
M('-I9VYA;"!D7V]U=%]T<U]C92 Z('-T9%]L;V=I8SL-"@T*8F5G:6X-"B @
M+2T@<F5G:7-T97(@:6YP=70@9&%T82P@;W5T<'5T(&1A=&$@86YD(&]U='!U
M="!E;F%B;&4L('=I=&@@<V5P87)A=&4@8VQO8VL-"B @+2T@96YA8FQE<PT*
M("!I;U]O95]R96=?<')I;3H@<')O8V5S<R H8VQK+"!R<W0I#0H@(&)E9VEN
M("TM(&EO7V]E7W)E9U]P<FEM#0H@(" @:68@*')S=" ]("<Q)RD@=&AE;@T*
M(" @(" @9%]O=71?<B \/2 G,"<[#0H@(" @("!D7V]U=%]T<U]R(#P]("<Q
M)SL-"B @(" @(&1?:6Y?<B \/2 G,"<[#0H@(" @96QS:68@<FES:6YG7V5D
M9V4H8VQK*2!T:&5N#0H@(" @("!I9B H9%]O=71?8V4@/2 G,2<I('1H96X-
M"B @(" @(" @9%]O=71?<B \/2!D7V]U=#L-"B @(" @(&5N9"!I9CL-"B @
M(" @(&EF("AD7V]U=%]T<U]C92 ]("<Q)RD@=&AE;@T*(" @(" @("!D7V]U
M=%]T<U]R(#P](&1?;W5T7W1S.PT*(" @(" @96YD(&EF.PT*(" @(" @:68@
M*&1?:6Y?8V4@/2 G,2<I('1H96X-"B @(" @(" @9%]I;E]R(#P]('!I;E]D
M870[#0H@(" @("!E;F0@:68[#0H@(" @96YD(&EF.PT*("!E;F0@<')O8V5S
M<R!I;U]O95]R96=?<')I;3L-"@T*(" M+2!C;VYN96-T('5P(&]E*'1S*2!E
M;&5M96YT#0H@("TM(&YO=&4Z(&ET(&ES(&YE8V5S<V%R>2!T;R!I;G9E<G0@
M;V4@=&\@=',@;W5T<VED92!T:&4@8VQO8VME9"!P<F]C97-S(&9O<@T*(" M
M+2!T;V]L<R!T;R!I;F9E<B!T:&4@<')I;6ET:79E(&QA>6]U="!C;W)R96-T
M;'D-"B @<&EN7V1A=" \/2!D7V]U=%]R('=H96X@9%]O=71?='-?<B ]("<P
M)R!E;'-E("=:)SL-"B @9%]O=71?=',@/#T@;F]T(&1?;W5T7V]E.PT*("!D
M7V]U=%]T<U]C92 \/2!D7V]U=%]O95]C93L-"@T*96YD(&EO7V]E7W)E9U]P
+<FEM7V%R8V@[#0H`
`
end
begin 666 io_oe_reg_vec.txt
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+0T*+2T@:6]?;V5?
M<F5G7W9E8RYV:&0@*%)%1TE35$52140@3T4I#0HM+2!$879I9"!-8TQE;V0-
M"BTM#0HM+2!!(&UI9"!L979E;"!E;G1I='D@=7-E9"!T;R!C<F5A=&4@;75L
M=&EP;&4@:6YS=&%N8V5S(&]F('1H92!P<FEM:71I=F4-"BTM(&EO7V]E7W)E
M9U]P<FEM+G9H9 T*+2T-"BTM($1A=&$@=VED=&@@:7,@<&%S<V5D(&%S(&$@
M9V5N97)I8PT*+2T-"BTM(%)E9VES=&5R960@:2]O('=I=&@@<F5G:7-T97)E
M9"!O92!F;W(@;75L=&EP;&4@24]"<R!O;B!86%A86"!6:7)T97@G<RX-"BTM
M#0HM+2!!;B!I+V\@9G5N8W1I;VX@=VET:"!O=71P=70@96YA8FQE(&9O<B!M
M=6QT:7!L92!)3T(N($EN<'5T<RP@;W5T<'5T<R!A;F0-"BTM('1H92!O=71P
M=70@96YA8FQE(&-O;G1R;VP@87)E(')E9VES=&5R960@=VET:"!S97!A<F%T
M92!C;&]C:R!E;F%B;&5S("AP97(-"BTM(&)A;FLI(&%N9"!A(&-O;6UO;B!A
M<WEN8VAR;VYO=7,@<F5S970@*&EN=&5N9&5D(&9O<B!S:6T@;VYL>2DN(%1H
M92!6:7)T97@-"BTM(&%R8VAI=&5C='5R92!D:6-T871E<R!A(&-O;6UO;B!C
M;&]C:R H8G5T(&YO="!P:&%S92D@86YD(')E<V5T+@T*+2T-"BTM($YO=&5S
M.@T*+2T@,2X@26YT96YD960@9F]R(')E9VES=&5R960@=')I<W1A=&4@9&%T
M82!P871H<R!E9RX@9&%T82!B=7-S97,-"BTM(#(N(%1H92!U<V4@;V8@:2]O
M('!R:6UI=&EV97,@:7,@9&EC=&%T960@8GD@9&EF9FEC=6QT>2!I;B!C;VYS
M=')A:6YI;F<-"BTM('1O;VQS('1O('!L86-E(')E9VES=&5R<R H<&%R=&EC
M=6QA<FQY('1R:7-T871E(&-O;G1R;VP@<F5G:7-T97)S*2!I;B!6:7)T97@-
M"BTM($E/0G,N(%1O('!L86-E('1H:7,@;&]G:6,@96YT:71Y(&EN('1H92!)
M3T(L('1H92!S>6YT:"!T;V]L(')E<75I<F5S('1H90T*+2T@(DE/0B(@871T
M<FEB=71E('1O(&)E('-E=" B=')U92(@7V%N9%\@=&AE(&EM<&QE;65N=&%T
M:6]N('1O;VP@<F5Q=6ER97,-"BTM(")U<V4@24]"<R(@=&EC:V5D(&]R(&%P
M<&QY(&UA<'!E<B!O<'1I;VX@(BUP<B!B(BX-"BTM#0HM+2!$871E.B P-2\P
M,2\P,0T*+2T-"BTM(%)E=CH@, T*+2T-"BTM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2T-"@T*;&EB<F%R>2!I965E.PT*=7-E(&EE964N<W1D
M7VQO9VEC7S$Q-C0N86QL.PT*#0IE;G1I='D@:6]?;V5?<F5G7W9E8R!I<PT*
M("!G96YE<FEC("A)3U]724142" Z(&YA='5R86PI.PT*("!P;W)T("@-"B @
M(" @(" @<G-T(#H@:6X@<W1D7VQO9VEC.PT*(" @(" @("!C;&L@.B!I;B!S
M=&1?;&]G:6,[#0H@(" @(" @(&1?;W5T(#H@:6X@<W1D7VQO9VEC7W9E8W1O
M<B@H24]?5TE$5$@M,2D@9&]W;G1O(# I.PT*(" @(" @("!D7V]U=%]C92 Z
M(&EN('-T9%]L;V=I8SL-"B @(" @(" @9%]O=71?;V4@.B!I;B!S=&1?;&]G
M:6,[#0H@(" @(" @(&1?;W5T7V]E7V-E(#H@:6X@<W1D7VQO9VEC.PT*(" @
M(" @("!D7VEN7W(@.B!O=70@<W1D7VQO9VEC7W9E8W1O<B@H24]?5TE$5$@M
M,2D@9&]W;G1O(# I.PT*(" @(" @("!D7VEN7V-E(#H@:6X@<W1D7VQO9VEC
M.PT*(" @(" @("!P:6Y?9&%T(#H@:6YO=70@<W1D7VQO9VEC7W9E8W1O<B@H
M24]?5TE$5$@M,2D@9&]W;G1O(# I#0H@(" @(" @("D[#0IE;F0@:6]?;V5?
M<F5G7W9E8SL-"@T*87)C:&ET96-T=7)E(&EO7V]E7W)E9U]V96-?87)C:"!O
M9B!I;U]O95]R96=?=F5C(&ES#0HM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM#0HM+2!S:6=N86P@9&5C;&%R871I;VYS#0HM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM#0HM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM#0HM+2!C;VUP;VYE;G0@9&5C;&%R871I;VYS#0HM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM
M+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM+2TM#0H)8V]M<&]N96YT
M(&EO7V]E7W)E9U]P<FEM#0H)<&]R=" H#0H)"7)S=" Z(&EN('-T9%]L;V=I
M8SL-"@D)8VQK(#H@:6X@<W1D7VQO9VEC.PT*"0ED7V]U=" Z(&EN('-T9%]L
M;V=I8SL-"B @("!D7V]U=%]C92 Z(&EN('-T9%]L;V=I8SL-"@D)9%]O=71?
M;V4@.B!I;B!S=&1?;&]G:6,[#0H@(" @9%]O=71?;V5?8V4@.B!I;B!S=&1?
M;&]G:6,[#0H)"61?:6Y?<B Z(&]U="!S=&1?;&]G:6,[#0H@(" @9%]I;E]C
M92 Z(&EN('-T9%]L;V=I8SL-"@D)<&EN7V1A=" Z(&EN;W5T('-T9%]L;V=I
M8PT*"0DI.PT*("!E;F0@8V]M<&]N96YT.PT*#0IB96=I;B M+2!I;U]O95]R
M96=?=F5C7V%R8V@-"@T*("!',2 Z(&9O<B!)(&EN(# @=&\@*$E/7U=)1%1(
M+3$I(&=E;F5R871E#0H-"@E555<@.B!I;U]O95]R96=?<')I;0T*"0EP;W)T
M(&UA<" H#0H@(" @(" @( D)"7)S=" ]/B!R<W0L#0H@(" @(" @( D)"6-L
M:R ]/B!C;&LL#0H@(" @(" @( D)"61?;W5T(#T^(&1?;W5T*$DI+ T*"0D)
M"0D@(" @9%]O=71?8V4@/3X@9%]O=71?8V4L#0H@(" @(" @( D)"61?;W5T
M7V]E(#T^(&1?;W5T7V]E+ T*(" @( D)"0D)9%]O=71?;V5?8V4@/3X@9%]O
M=71?;V5?8V4L#0H@(" @(" @( D)"61?:6Y?<B ]/B!D7VEN7W(H22DL#0H@
M(" @"0D)"0ED7VEN7V-E(#T^(&1?:6Y?8V4L#0H@(" @(" @( D)"7!I;E]D
M870@/3X@<&EN7V1A="A)*0T*(" @(" @(" )"0DI.PT*#0H@(&5N9"!G96YE
E<F%T92!',3L-"@T*96YD(&EO7V]E7W)E9U]V96-?87)C:#L-"@``
`
end
Article: 32111Jason, > We want to be able to process 24 bit RGB at 45Mpix/s or faster. I > don't think that DSPs can do it, a massively parallel FPGA > architecture or an ASIC are probably the only choices. We have implemented several (Convolution kernel, FFT...) massively=20 parallel architectures in Virtex II FPGAs. We have developed tools for=20= auto generating HDL code from a set of parameters. These tools make the = process much simpler than coding it directly in VHDL or Verilog and make= s=20 the resulting IP Core very flexible as it is parameter based. Virtex II is a very good choice for these algorithms as long as the=20 application can afford the device cost as 45Mpix/s will require a large = Virtex II device. Let me know if we can be of any assistance in getting this core develope= d=20 for you. Regards,=20 Tom Dillon Dillon Engineering, Inc. http://www.dilloneng.comArticle: 32112
This is a multi-part message in MIME format. --------------34FCC950A33D966FCB1D0C01 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Paul, <p>The XPLA3 parts will be in the Emerald software alongside the 9500XX parts....ie 4.1i which will be out in 3ish months.. <p>Dave <p>Paul Taylor wrote: <blockquote TYPE=CITE>Hello Peter. <br>I noticed last year that Coolrunner parts aren't selectable in the <br>Foundation <br>base software. Do you think they might be in the future? <p>Thanks, Paul. (p.s. you posted HTML! I changed the Format to plain <br>text.) <p>> If you need CPLDs, CoolRunner is the way to go!</blockquote> </html> --------------34FCC950A33D966FCB1D0C01 Content-Type: text/x-vcard; charset=us-ascii; name="dhawke.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for David Hawke Content-Disposition: attachment; filename="dhawke.vcf" begin:vcard n:Hawke;David Hawke tel;cell:(+44) 778 875 5002 tel;work:(+44) 870 7350 517 x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/smvirtex.gif" alt="Xilinx"> version:2.1 email;internet:dhawke@xilinx.com title:XILINX Field Applications Engineer adr;quoted-printable:;;Xilinx Northern Europe=0D=0ABenchmark House;203 Brooklands road;Weybridge;; x-mozilla-cpt:;2672 fn:David Hawke end:vcard --------------34FCC950A33D966FCB1D0C01--Article: 32114
isu@btae.mam.gov.tr (I. Servan Uzun) wrote in message news:<018601c0f3d9$006b78f0$f001120a@oracles>... > Hi, > > I am using Altera PCI developement Kit (PCI-BOARD/A4E) but > I can not manage to reconfigure it by FLASH or JTAG? > > Could you please help me how I can configure APEX device by > JTAG? > > > Regards > Servan Uzun > > > > -- Please refer to application note 116 for generic configuration questions. http://www.altera.com/literature/lit-apx.html BrianArticle: 32115
Rick Filipkiewicz schrieb: > > I'm looking for an Ethernet MAC and a 3DES core either specifically > Xilinx or available as source so I can port it. Xilinx has some stuff > available but: > > o The Ethernet stuff is only the Tx/Rx blocks & I'm looking/hoping for > something more comprehensive. > > o The 3DES core uses 70% of the largest Spartan2. Maybe this is normal > but I really need something smaller. > > For the 3DES - is there a good description anywhere of the algorithm > viewed from a h/w perspective ? In case I have to write the code myself. https://www.cosic.esat.kuleuven.ac.be/des/ http://www.free-ip.com -- MFG FalkArticle: 32116
Wouldn't it be great if finally we could all enjoy of a high-capacity, high reliability, carrier class optical network? Well don't be part of the problem, come and BE the solution. We are hiring several FPGA and Hardware Engineers with a passion for being in the front seat of designing the next revolution in optical networking products. This is not a company guided by the thrill of easy money (although there is plenty of financial incentives), here reliable designs, lined up customers, and technological innovation are the forces behind the great team of engineers. Come and participate with your own ideas and develop your own projects. If you have experience (at least 3 years) in Board level FPGA design then come and participate!!! We are looking for people who can take on full responsibility for their projects, and who have successfully lived through the full development lifecycle. Have you participated ( I mean REALLY participated) in subsystem definition, component selection, logic design, characterization, and verification of commercial level ASICs? Then come apply today and find out more about the advantages of working and living in the heart of Texas! This Dallas company offers a challenging but casual environment, full benefits, excellent compensation, a financially stable future (and did I mention they give great stock options?). See what all the fuzz is about, send your resume and cover letter right now! Please email your resume to agautier@scientific.com in plain ascii text format (refer to JO# JO56418APM in your response) or fax to the number listed below. To help us expedite our response, please include information on your current salary status and expectations. If you'd like to be considered for other positions similar to the one described above, please provide input on relocation preferences in the U.S. Scientific Placement staff members are knowledgeable specialists in niche technology job markets (Multimedia, E-Commerce, Networking/Telecom, Games, Embedded Systems, Hardware, and platforms that include: Macintosh, Windows, and Unix). We can provide advice on resume quality, salary levels, and the demand for certain skills. Scientific Placement enjoys a national reputation for professionalism, competence, and ethics. Our clients are scattered nationwide and clustered wherever there is a high technology developer community. Fees are employer paid. For additional information, please visit our web site. Anjanette Gautier Associate Scientific Placement, Inc 512-331-0302 512-331-1828 fax agautier@scientific.comArticle: 32117
Ulises Hernandez wrote:
> Hello Rick,
>
> Thank you for your answer.
>
> I have tried to convert the NGD file to VHD file.
> I have now a nice and incomprehensible file of 29000 lines of code with all
> the simprims in it (and this is the smallest LCA).
>
> I tried to synthesize this file with Leonardo without converting the
> primitives to VHDL RTL mode (Just trying). It didn't work as you probably
> knew.
> You are talking about 'convert the primitives to VHDL RTL (using Perl, too
> much for me) ', what does it mean?
> The errors in Leonardo are :
>
> ERROR, 'X_ONE' is not a component.
> ERROR, 'X_AND4' is not a component.
> ERROR, 'X_BUF' is not a component.
> ...
>
> I guess this are Xilinx parts X_* and Leonardo doesn't identify them, I
> changed the name from X_BUF to BUF and the resutl was the same.
> So, that magic Perl script what should it do?
>
> Thank you in advance.
> Ulises Hernandez
>
The problem here is that when the Xilinx NGD2VHD tool generates a simulation
netlist using the ``simprims'' primitive library. But when a synthesis tool
generates an EDIF netlist it instantiates primitives from the ``unisims'' lib.
Therefore what you have to do is one of these things:
A: map the simprims objects to functionally equivalent unisims ones. This is a
non-trivial task since e.g. there a simprims object called X_FF which has an
async set, async reset, and a clock enable. Depending on how a particular X_FF
is wired up you might have to map it to an of these unisims:
FD, FDC, FDP, FDCP, FDCE, ..... etc etc.
Perl could do this but its very easy to get wrong.
B: Write a synthesisable RTL model for each simprim. You'd want to start from
the simprims VHDL simulation models so you get the functionality right and
probably use Perl to go through the VHDL netlist replacing `X_' with e.g.
`SYNTH_SPRIM_'.
C: Go direct & convert each simprim occurence to RTL. I can't remember VHDL well
enough but an X_FF with an async reset & clock enable would look something like
this in verilog:
X_FF (
.CLK(clock),
.I(din),
.O(dout),
.SET(1'b0),
.RST(async_reset),
.CE(clock_en)
);
The Perl would have to replace that with:
always @(posedge clock or posedge async_reset)
if (async_reset)
dout <= 1'b0;
else
if (clock_en)
dout <= din;
Note that although you asked for VHDL I think the Verilog route would be much
easier.
Article: 32118Rick, We are working on a DES and 3DES app. note. This will be available in the next few weeks but this is a very high speed implementation targeted for Virtex-E/Virtex-II and may not fit in a Spartan-II. What kind of performance are looking for? Free-IP offers two versions of DES core, one for performance and the other optimized for area/resources used. DES has 16 iterations of block ciphering, and in order to save resources, you can implement a single ciphering engine and this can be used iteratively. For further info, refer http://www.free-ip.com/DES/index.html Three of these DES cores can be cascaded to implement 3DES. Some good references are Schneier, B., Applied Cryptography, John Wiley and Sons, 1996. FIPS, “Data Encryption Standard”, Federal Information Processing Standards Publication 46-3, 1999 October 25, available at http://csrc.nist.gov/publications/fips/fips46-3/fips46-3.pdf http://www.darkside.com.au/bitslice/ Hope this helps !!! -Vikram Xilinx Applications Rick Filipkiewicz wrote: > I'm looking for an Ethernet MAC and a 3DES core either specifically > Xilinx or available as source so I can port it. Xilinx has some stuff > available but: > > o The Ethernet stuff is only the Tx/Rx blocks & I'm looking/hoping for > something more comprehensive. > > o The 3DES core uses 70% of the largest Spartan2. Maybe this is normal > but I really need something smaller. > > For the 3DES - is there a good description anywhere of the algorithm > viewed from a h/w perspective ? In case I have to write the code myself.Article: 32119
There are a number of very high quolity Eng. here in the UK working with ATM, iSCSI and Gigabit-E... Shame they are no big compainys in the US willing to use these people and/or there compainy!? cyber_spook_man Anjanette Gautier wrote: > Wouldn't it be great if finally we could all enjoy of a high-capacity, > high reliability, carrier class optical network? > > Well don't be part of the problem, come and BE the solution. > > We are hiring several FPGA and Hardware Engineers with a passion for being > in the front seat of designing the next revolution in optical networking > products. This is not a company guided by the thrill of easy money (although > there is plenty of financial incentives), here reliable designs, lined > up customers, and technological innovation are the forces behind the > great team of engineers. Come and participate with your own ideas and > develop your own projects. > > If you have experience (at least 3 years) in Board level FPGA design then > come and participate!!! > > We are looking for people who can take on full responsibility for their > projects, and who have successfully lived through the full development > lifecycle. Have you participated ( I mean REALLY participated) in subsystem > definition, component selection, logic design, characterization, and verification > of commercial level ASICs? > > Then come apply today and find out more about the advantages of working > and living in the heart of Texas! This Dallas company offers a challenging > but casual environment, full benefits, excellent compensation, a financially > stable future (and did I mention they give great stock options?). See > what all the fuzz is about, send your resume and cover letter right now! > > Please email your resume to agautier@scientific.com in plain ascii text > format (refer to JO# JO56418APM in your response) or fax to the number > listed below. > > To help us expedite our response, please include information on your current > salary status and expectations. If you'd like to be considered for other > positions similar to the one described above, please provide input on > relocation preferences in the U.S. > > Scientific Placement staff members are knowledgeable specialists in niche > technology job markets (Multimedia, E-Commerce, Networking/Telecom, Games, > Embedded Systems, Hardware, and platforms that include: Macintosh, Windows, > and Unix). > > We can provide advice on resume quality, salary levels, and the demand > for certain skills. Scientific Placement enjoys a national reputation > for professionalism, competence, and ethics. Our clients are scattered > nationwide and clustered wherever there is a high technology developer > community. Fees are employer paid. For additional information, please > visit our web site. > > Anjanette Gautier > Associate > Scientific Placement, Inc > 512-331-0302 > 512-331-1828 fax > agautier@scientific.comArticle: 32120
For the record, XST was purchased by Xilinx from a company called Minc, which in turn was formed from two companies, Synario and IST. IST originally developed what is now called XST. Metamor was a (very) small company that produced a VHDL synthesis tool that Xilinx, Synario, and others licensed. In the time that we licensed it, Metamor was not fully 93 compliant, although it did support a subset of 93 features. The original problem that started this thread should be corrected when our 4.1i software is released later this summer. Speaking only for myself and not Xilinx, -Dennis McCrohan Rick Filipkiewicz wrote: > "Andy Peters > > > Rick Collins wrote: > > > I vaguely remember a compilier that came with Foundation before > > > they started shipping FPGA Express. If I remember correctly, it was > > > Metamore. Anyone know if this is correct? Is this the tool that became > > > XST? > > > > XST doesn't look like the Metamor tool, which was probably little more > > than a stop-gap synthesis solution before Xilinx inked the deal with > > Synopsys for FPGA Express. > > > > and stepped back from VHDL-93 (Metamor) to VHDL-1887 (Synopsys).Article: 32121
http://www.optimagic.com/ Try the vendor summary table & the device summary table! Sven Heithecker wrote: > Hi, > > I am looking for a FPGA guide or something like that where I can find > - an overview of all FPGAs available > - comparsion of the different FPGA types (how many gates, how many useable > gates, available speed,...) > > Free internet access is preferred, but not necessary. > > Sorry if this question was aked before, I am new to this group. > > Regards, Sven > > -- > Sven Heithecker IDA, Hans-Sommer-Str. 66 > Technical University of Braunschweig 38106 Braunschweig > Tel. +49-(0)531-391-3751(voice)/4587(fax) Germany > http://www.ida.ing.tu-bs.de/~svenh heithecker@ida.ing.tu-bs.deArticle: 32122
I have several legacy Xilinx FPGA that were designed via gate-level techniques before VHDL became the de-facto design entry methdology -- The best methodology was to write the VHDL myself. IOW I inferred all the gate level design into VHDL. Generating VHDL yourself you will end up w/ code that has structure and some sense behind it ... Ulises Hernandez wrote: > Hello to the group, > > I am currently working in FPGA designs. We are now investigating if is > possible to upgrade a design. This is an old design which was implemented in > a XC5215 FPGA and was built using schematics :-((, the schematics were done > using Mentor Graphics tools. This tool generates the EDF file which you use > for the build process, we will probably migrate this design to the Spartan > II family. But my personal challenge will be to pass them to VHDL. It is a > nightmare I know, os I would like to know if someone knows some software to > convert to VHDL a EDF file o convert to VHDL a schematic using Mentor tools. > There must be something, to pass it to Verilog will do but it much better to > VHDL. Maybe the VHDL generated is quite poor but easier to modify than the > schematics. > > Thank you to all in advance. > > Ulises Hernandez > Design EngineerArticle: 32123
We observe a problem when programming a Virtex II XC2V1000 if the device is not at the end of the configuration chain. We used a concatenated configuration bitstream (generated by Xilinx PROM file formatter). During the configuration, the XC2V1000 FPGA receive the appropriate bitstream but don't transfer by DOUT pin the next bitstream to the next device of the chain. In more the INIT pin is drived low to indicate an error. -> Our configuration clock is 4MHZ -> We used the ServicePack #8 -> The configuration EEPROM is XC18V04vq. If someone have an idea, could you share it. martin_forest@nmss.com ThanksArticle: 32124
Optimagic was last updated July 2000. Nice historical document, but not so relevant anymore. Unfortunately. Performance has gone up, stock price has gone down. Go figure ! Peter Alfke =============================== Joe wrote: > http://www.optimagic.com/ > > Try the vendor summary table & the device summary table! > > Sven Heithecker wrote: > > > Hi, > > > > I am looking for a FPGA guide or something like that where I can find > > - an overview of all FPGAs available
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z