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Hi, I want to redesign our PCI-Card, replacing the PCI-Controller with an FPGA. Whats about the BIOS Booting Sequence? Can I programm the Spartan2-FPGA containing the PCI-Interface after booting of BIOS is complete? Or is the only way that I use two FGPAs one with the PCI Interface which has an SEPROM to come up before BIOS searches the PCI-Devices and the second FPGA that can be programmed later? thanks 4 hints peterArticle: 31526
"Paul Taylor" <p.taylor@ukonline.co.uk> skrev i meddelandet news:hmwQ6.12669$8Z5.772755@monolith.news.easynet.net... > Hello Peter. > I noticed last year that Coolrunner parts aren't selectable in the > Foundation > base software. Do you think they might be in the future? > > Thanks, Paul. (p.s. you posted HTML! I changed the Format to plain > text.) > > > > If you need CPLDs, CoolRunner is the way to go! > > I thought (some) Coolrunner's already went! (Sorry could not resist :-) -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel SwedenArticle: 31527
I am trying to install Xilinx Alliance 3.x Software on a Pentium 4 system. During installation I receive a message that states "java.exe has caused errors and has been closed ..." According to the Xilinx website this is due to the fact that the Pentium 4 isn't compatible with the Java Runtime Environment and that the latest version needs to be downloaded form the Sun website. I did this, and I still get the same error. Has anyone ran into this problem and been able to solve it? Or does Xilinx have a patch for their software? Thanks, ShaneArticle: 31528
It appears that the tools for the SFL language support conversion to Verilog or VHDL. Is it possible someone can convert this 8080 processor core into Verilog or VHDL. Then it could be used with the Xilinx tools for creating a 8080 clone... MarkArticle: 31529
Peter Lang wrote: > Hi, > I want to redesign our PCI-Card, replacing the PCI-Controller > with an FPGA. > Whats about the BIOS Booting Sequence? > Can I programm the Spartan2-FPGA containing the PCI-Interface > after booting of BIOS is complete? > > Or is the only way that I use two FGPAs one with the > PCI Interface which has an SEPROM to come up > before BIOS searches the PCI-Devices and > the second FPGA that can be programmed later? This is the only realistic way without rebooting. Theoreticall it is possible to have a PCI interface in one portion of a Virtex/Spartan family and to reprogram the other parts of the chips through PCI. But there is no tool support for this and it is very risky. The initial configuration still needs to come from a prom. If you do not need dynamic reconfiguration but only want to do field updates you can store the configuration in a flash PROM that can be written via PCI. The new configuration is then available after reset. We do this in our FPGA board. As you seem to be german, you can look it up: http://www.em.informatik.uni-frankfurt.de/~prak/platine/index.html A CPLD and FLASH is easier to get and cheaper than a configuration PROM anyway. Kolja SulimmaArticle: 31530
TW9ybiwNCg0KPiBXZXIgaGF0IEVyZmFocnVuZyBtaXQgZGVyIEFuYmluZHVuZyBlaW5lcyBG UEdBIGF1ZiBlaW5lbSBQQ0kgLSBCb2FyZCBhbg0KPiBkZW4gUENJIC0gQnVzLiBEYXp1IGJl bnV0emUgaWNoIGRlbiBQTFggQmF1c3RlaW4gUENJIDkwNTIuIEljaCBt9mNodGUNCj4gZWlu ZW4gU1JBTSwgZGFzIG1pdCBkZW0gRlBHQSB2ZXJidW5kZW4gaXN0IPxiZXIgZGVuIFBDSSAt QnVzIGF1c2xlc2VuLg0KPiBXZXIgaGF0IFRpcHBzIG9kZXIgYXVjaCBCZWlzcGllbHByb2dy YW1tZSBpbiBWSERMIGRpZSBkaWVzZXMNCj4gYmV3ZXJrc3RlbGxpZ2VuLiBXb3JhdWYgbXVz cyBpY2ggYmVpbSBwcm9ncmFtbWllcmVuIGRlcyBGUEdBIGFjaHRlbi4NCj4NCg0KWW91IGFy ZSB0YWxraW5nIGFib3V0IHR3byBkaWZmZXJlbnQgdGFza3MuIEZpcnN0IHlvdSBoYXZlIHRv IGNvbmZpZ3VyZQ0KeW91ciBGUEdBIHdpdGggYSBkZXNpZ24sIHBlcmhhcHMgaW1wbGVtZW50 ZWQgd2l0aCBWSERMLg0KVGhlIHNlY29uZCB0YXNrcywgaXMgdG8gZXN0YWJsaXNoIGEgY29t bXVuaWNhdGlvbiBiZXR3ZWVuIHRoZSBwYyBhbmQgdGhlDQpwY2ktY2FyZCBhbmQgdGhlIG1v dW50ZWQgY29tcG9uZW50cy4NCg0KSGF2ZSB5b3UgZGVzaWduZWQgdGhpcyBwY2ktY2FyZCB5 b3Vyc2VsZiA/DQoNCmNpYW8NCkr2cmcNCg0KArticle: 31531
TW9ybiwNCg0KPiBXaG8gaGF2ZSB0aGUgZXhwZXJpZW5jZSB3aXRoIHRoZSBGUEdBIG9uIGEg UENJLWJvYXJkIHRvIGNvbm5lY3QgYQ0KPiBQQ0ktYnVzLCB3aXRoIHVzaW5nIHRoZSBQTFgt ZGV2aWNlOiBQQ0kgOTA1Mi4gQW4gU1JBTSBpcyBjb25uZWN0IHdpdGgNCj4gdGhlIEZQR0Eg YW5kIHRoaXMgZGV2aWNlIHNob3VsZCBiZSByZWFkIGZyb20gdGhlIFBDSS1idXMgKDMyIEJp dCBhY2Nlc3MpDQo+DQo+IFdobyBoYXZlIHRpcHMgb3IgZXhhbXBsZS1zb3VyY2Uvc3RhbmRh cmQtc291cmNlIGluIFZIREwsIHRoYXQgdGhpcyBjYW4NCj4gbWFuYWdlID8gV2hhdCB0aGlu Z3MgSSBtdXN0IG9ic2VydmUgPw0KPg0KPiBUaGFua3MgIQ0KPiBNYXJpbw0KDQpZb3UgYXJl IHRhbGtpbmcgYWJvdXQgdHdvIGRpZmZlcmVudCB0YXNrcy4gRmlyc3QgeW91IGhhdmUgdG8g Y29uZmlndXJlDQp5b3VyIEZQR0Egd2l0aCBhIGRlc2lnbiwgcGVyaGFwcyBpbXBsZW1lbnRl ZCB3aXRoIFZIREwuDQpUaGUgc2Vjb25kIHRhc2tzLCBpcyB0byBlc3RhYmxpc2ggYSBjb21t dW5pY2F0aW9uIGJldHdlZW4gdGhlIHBjIGFuZCB0aGUNCnBjaS1jYXJkIGFuZCB0aGUgbW91 bnRlZCBjb21wb25lbnRzLg0KDQpIYXZlIHlvdSBkZXNpZ25lZCB0aGlzIHBjaS1jYXJkIHlv dXJzZWxmID8NCg0KY2lhbw0KSvZyZw0KDQoNCg==Article: 31532
> I built the cable myself for around $15 worth of parts from Radio Shack.
> Suprisingly, they stocked everything that is needed. Boy is it ugly
> though... next one I build will be prettier, I think.
Is this a download cable to configure the devices via JTAG
(like the altera byte blaster)?
If so can you send me the pin out?
Martin
--
Whant to see the evolution of a Java processor?
http://www.jopdesign.com
Article: 31533Thanks very much for your hard work on this, folks! Brian Dipert Technical Editor: Memory, Multimedia and Programmable Logic EDN Magazine: http://www.ednmag.com Contributing Editor, CommVerge Magazine: http://www.commvergemag.com 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (voice), (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.pacbell.net Visit me at http://members.aol.com/bdipertArticle: 31534
ignoreArticle: 31535
Hi Kent, Thanks for the reply it makes sense now. I can see the potential problem but in this instance the "ClkEn" is related to "Clk" as not to be a problem (in this instance). The design is a conversion from a Lattice PLD and my first venture into Xilinx and modelsim so I have to learn what the warnings really mean. I also have seen warnings such as Gonzalo mentioned below an wonder how to find them. Being a novice expect a few more questions :-). Cheers Dave "Kent Orthner" <korthner@hotmail.nospam.com> wrote in message news:wku226uu20.fsf@hotmail.nospam.com... > Hi, Dave. > > A gated clock is when you have something like the following: > > > NewClk <= Clk and ClkEn; > > This (in theory) gives you a clk signal derived from 'Clk', using 'ClkEn' > as an enable. It is called a 'gated' clock because it is derived from > Clk via some sort of logic gate, in this case an and gate. > > Using a gated clock is generally considered a Very Bad Thing. > > The first problem is if your ClkEn signal changes at some point when Clk > is not low. The signal on NewClk will include a glitch or poorly formed > pulse. > > The second problem is that there is a delay through the and gate. If you > are using Clk anywhere else in your circuit, perhaps without an enable, or > with a different enable, you are going to get your clock edges at different > times, leading to race conditions and skew problems. > > In short, using gated clocks causes a nice, reliable, synchronous design > to have all sorts of nasty asynchronous & skew-related problems. > > Unfortunately, none of these problems will show themselves in your regular > functional simulation, since usually you simulate thihgs with zero-delay. > If you do post-place & route simulation with delays, you will probably see > problems. > > when Xilinx's warning says to use the 'CE' pin, that is the enable pin on > the Flip-flop that can be used instead of modifying the clock itself. > > To use the CE pin, at least in VHDL, you need to do something like this: > > process( Clk ) is > begin > if Clk'event and Clk = '1' then -- Rising edge of Clk > if ClkEn = '1' then -- Synchronous enable. This causes ClkEn > -- to be connected to the FF's CE pin. > outsig <= insig; > end if; --enable > end if; --clk > end process; > > Hope this helps. > -Kent > > > "Speedy Zero Two" <david@manorsway.freeserve.co.uk> writes: > > I have a large design which when targeting a 300 series devices gives > > several warning, (like below). > > As this is an internal node how do I find out what to change to correct it. > > > > Cheers > > Dave > > > > > > WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net MUX_OBUF is > > sourced > > by a combinatorial pin. This is not good design practice. Use the CE pin > > to > > control the loading of data into the flip-flop.Article: 31536
Allan Herriman wrote: > Hi Peter, > > Are you able to post a (link to) the circuit? I can see its description > in the databook, but no internal details. We normally don't publish circuit details down at that level. It is a variation on "my" circuit described in XCell#24, with programmable polarity added to it. > > > AIUI, this circuit must contain bistable elements, and therefore is > subject to metastability. Thus there is a finite (albeit small) chance > that the output will be corrupted when switching clocks. Or am I > missing something? > > From the description, it looks like there's half a clock cycle worth of > metastability resolution time, which should be enough to reduce the > probability of failure to something that is vanishingly small. Is this > how you made it "fail safe?" Yes, exactly. There was a spirited discussion between Phil Freidin, Bob Perlman and me ( see, I don't use "myself", I learned grammar the good old way!) on this newsgroup, shortly after that article was published. Perhaps you can fish it out of the (excellent) archive. And remember, the circuit is built out of lean and mean dedicated logic and flip-flops, where matastability resolves extremely fast. Greetings PeterArticle: 31537
Anders Ramdahl wrote: > Peter's cirquit requires both clocks to be operational in order to > switch. You cannot make that assumption in a hich reliability system. > It will reduce the reliability of the system. > > I would be very careful about using these glitch free global clock MUXes > of the Virtex II in a fault tolerant or high reliability system. I hope > the glitch free feature can either be disabled or that it allows > switching from a dead clock to a working one. > Anders is basically right. That's not what this circuit was intended to do. It was meant to switch between two free-running clocks, or to enable/disable a clock. No problem with "disabling" it: You just don't connect the second input and don't use the select input. If I remember right ( I am at home without access to documentation ) you can switch away from a dead clock if it is parked at one of its two levels, but not at the other. I maintain, it's a nice circuit when you switch between two free running clock frequencies, e.g. to save power. Beats our classical recommendation of using CE and always running the clock full-speed everywhere. Tack för hjälpen, Anders. Peter Alfke, Xilinx ApplicationsArticle: 31538
How to search the comp.arch.fpga archive at www.fpga-faq.com Searching should be intuitive to experienced web-wienies . It looks intuitive, with google search, but at least for a little while it will be messy, because the search engine is working on stale data. Most of the Archive pages now have a Google search box. Type the keywords and click search. The result for 'metastability' is quite long . Unfortunately, Google is still working from its scan of the website of a few weeks ago, and the article numbers have all changed. This is a one time only problem, as the article numbers are not expected to change again. Once Google re-indexes the site, the problem will go away. Here is a fragment of a search, and here's how to use it until the the search problem is resolved. >comp.arch.fpga archives - threads starting aug 2000 >... to Orcad conversion 24322: 00/08/10: John L. Smith: Further FPGA metastability >questions 24329: 00/08/10: rickman: Re: Further FPGA metastability questions ... >www.fpga-faq.com/archives/threads_2000_08.html - 101k - Cached - Similar pages > >comp.arch.fpga archives - authors (d) >... 9366: 98/03/20: Re: Dual port Dale Pontius: 8196: 97/12/10: Re: what is metastability >time of a flip_flop 8217: 97/12/11: Re: what is metastability time of a ... >www.fpga-faq.com/archives/authors_d.html - 101k - Cached - Similar pages > >comp.arch.fpga archives - messages from 29625 >... Consultant Synchronous Design, Inc. Oviedo, FL USA Article: 29630 Subject: Re: Metastability >From: Magnus Homann <d0asta@licia.dtek.chalmers.se> Date: 10 Mar ... >www.fpga-faq.com/archives/29625.html - 54k - Cached - Similar pages The first entry is a threads listing, and identifies the article as 24322. If you follow the link, you get the correct CURRENT copy of the threads listing for 8/2000, and if you do a simple text search, you will find that 24322 is not even on the page. If you follow the 'cached' link you will get to the copy of the page that Google is working from (the old stale one) and here you will find the 24332 article ref, and the rest of the thread titles. This wont help you, as the current article numbered 24322 has nothing to do with metastability. The second entry identifies Dale Pontius and article 8196. If you follow the link, you get the index of all authors names starting with D. If you search for 'Dale Pontius' within this page, you find the CURRENT article number is actually 8356. Follow this and read about metastability. follow the '<< T >>' to follow the thread The cached verstion of this link is not of much use for anything. The third entry identifies an actual article (message 29630). If you follow the main link, you will get the current version of this page, which does not contain the article you want, because 29630 in the CURRENT archive has nothing to do with metastability. But the cached copy of this page does have the article you are looking for. Threading wont work though, because the threading is based on current article numbers, not cached article numbers. All this will be resolved when Google re-indexes the archive. Till then, using the second example seems the best bet, as it (with effort) gets you to the article you want, and threading works. Sorry this didn't just wake up perfectly, but that's the way it is. Philip =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 31539
That patent is applied, but not granted yet. And, for a US patent, that means the description is not publicly available. The grandfather of this idea has been patented as US 6,204,695, issued March 20, 2001. But that is just a clock gating circuit, not a clock multiplexer. Peter Alfke ================================== Kolja Sulimma wrote: > Peter could for example post the patent ID. > > Kolja SulimmaArticle: 31540
I am designing a multi-function peripheral for a microcontroller using a Xilinx Spartan II. I have created an initial design that uses the read and write signals from the microcontroller in an asynchronous fashion. The VHDL compiler warns about using these signals as clocks, so I'm wondering if this is the best design approach. I was thinking I would use the write signal to clock the data into the Xilinx, and then run it through some logic to synchronize it with the Xilinx clock (which will be the same as the processor's clock). The microcontroller has a clock output signal, but I'm not sure if the write or read strobes are synced with the clock. I would think the latter would be the preferred approach if the microcontroller's read and write strobes are derived from the microcontroller's clock. What is the preferred design approach when interfacing with the read and write signals of a microcontroller? Thank you very much, Greg CaryArticle: 31541
When I did an interface between an AVR and a FPGA I latched the data using the strobes, detected the edge of the strobe and then clocked the data into a register afterwards. This worked without generating errors, but left ME unhappy.... -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel Sweden "Greg Cary" <gcary@multifeeder.com> skrev i meddelandet news:UxSQ6.2712$YC5.200296@news.uswest.net... > I am designing a multi-function peripheral for a microcontroller using a > Xilinx Spartan II. I have created an initial design that uses the read and > write signals from the microcontroller in an asynchronous fashion. The VHDL > compiler warns about using these signals as clocks, so I'm wondering if this > is the best design approach. I was thinking I would use the write signal to > clock the data into the Xilinx, and then run it through some logic to > synchronize it with the Xilinx clock (which will be the same as the > processor's clock). The microcontroller has a clock output signal, but I'm > not sure if the write or read strobes are synced with the clock. I would > think the latter would be the preferred approach if the microcontroller's > read and write strobes are derived from the microcontroller's clock. > > What is the preferred design approach when interfacing with the read and > write signals of a microcontroller? > > Thank you very much, > > Greg Cary > > >Article: 31542
"Greg Cary" <gcary@multifeeder.com> writes: > What is the preferred design approach when interfacing with the read and > write signals of a microcontroller? I'm not yet an expert on this, but my $0.02 worth is: FIFOs can be very helpful. You can use them to buffer the data (and perhaps address) on writes. For reads, you can use a FIFO for a data register. If you have other read-only registers that give status information (and don't cause side effects), it's probably OK to access them asynchronously from the host side. Or you could use dual-port RAM. Generally you want the host side to be a separate clock domain from the rest of your design, and to make sure that the interface between the clock domains is simple and uses "safe" constructs. You don't want the host read or write strobes to directly control any logic in your device. With FIFOs or DPRAM you avoid this. If you *must* have the read or write strobe control any internal logic, make sure you run them through synchronizers.Article: 31543
Aaron Nabil wrote:
>
> Atmel ATV750/ATF750.
Nice small device, we have used them for years.
For this, your Abel pathways are somewhat restricted
- it does not have a 'open' fitter like the bigger CPLDs.
I would suggest the Atmel WinCUPL - it's free on their web, and you can
also PgmrEditor/Command-line operate it. It has ATF750x support inbuilt.
CUPL and ABEL are broadly similar, and are close to identical at the
lowest usage levels like
Reg.ck = Name;
Reg.d = Node1 & Node2
# Node2 & Node3;
CUPL has a preprocessor, with conditional defines, that we use a lot.
It also has MACRO and Function abilities, and allows good expression
layering.
ABEL has WHEN.. and IF.. and allows Field+1 expressions - if you have
used
any of these, you will need to recode for cupl.
ABEL produces EQN report files, that are low level, so quite portable.
If you already have an old (complete) abel project dir, and need small
changes, import of those into CUPL is a good pathway.
-jg
> -a
> > Aaron Nabil wrote:
> > >
> > > Got an old copy of ABEL around? I need one for a project,
> > > the complete kit (ie, legal) with a key. Prefer version 6
> > > but 5 might work.
Article: 31544Simon wrote: > If you get no joy, I can send you the one that came free > with my Burch kit. It's only a 'cd single' size, but I > think it's got everything on it. (I had already d/l'd all > the software :-) Hmm another good point for the FPGA kit!Article: 31545
I just made a connection (finally!). "Kent Orthner" <korthner@hotmail.nospam.com> wrote in message news:wkpucuutxn.fsf@hotmail.nospam.com... > "Dave Feustel" <dfeustel@mindspring.com> writes: > > I had tried this a couple of times but I can't seem to get there from 'here'. > > (I get dns/server error msg) > > > > "Ray Andraka" <ray@andraka.com> wrote in message news:3B09A644.6F8725C6@andraka.com... > > > http://www.aldec.com > > > > > > Dave Feustel wrote: > > > > > > > > What is the URL for Aldec? > > > > > > I just checked. www.aldec.com works fine from here. (I'm in Japan) > > But I *have* found the website to be a bit flaky . . kind of off again > on again. Any time it was off, it came back on in a matter of hours. > > -kentArticle: 31546
Dave Feustel wrote: > > What is the FPGA kit? Burch makes a several low cost FPGA boards that can be used for FPGA experimentation. Some of the boards are in kit form that you assemble yourself. http://www.burched.com.au/index.html -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Luna family of Octal Computers" http://www.jetnet.ab.ca/users/bfranchuk Updated - Now with schematics.Article: 31547
Orcad CAPTURE has a builtin facility for generating schematic symbols from the one or more files in the Xilinx/Altera database. Look in TOOL/GENERATE PART. Works great, much more reliable than hand-entering a jillion pin numbers and pin names (for the umpteenth time), not ot mention the brain-numbing experience of *checking* the symbol for boo-boos. -- Bob Elkind, eteam@aracnet.com FPGA weenie for hire! "Alfred M." wrote: > ANyone have any Orcad Capture symbols for Virtex II. Particulatly in the BF957 package?Article: 31548
bob elkind <eteam@aracnet.com> writes: > "Alfred M." wrote: > > > ANyone have any Orcad Capture symbols for Virtex II. Particulatly > > in the BF957 package? > > Orcad CAPTURE has a builtin facility for generating schematic > symbols from the one or more files in the Xilinx/Altera database. > > Look in TOOL/GENERATE PART. > > Works great, much more reliable than hand-entering a jillion pin > numbers and pin names (for the umpteenth time), not ot mention the > brain-numbing experience of *checking* the symbol for boo-boos. That's fine for just drawing schematics but if you try and do a PCB layout based on that netlist you end up with a whole load of pads on the footprint with no matching connections in the netlist. OrCAD baulked last time I did this but that was in v9.1 and things may have changed since then. Chris -- Chris Eilbeck mailto:chris@yordas.demon.co.ukArticle: 31549
Chris, Could you elaborate on the problem? Was this a layout program issue, a netlister issue, etc. etc. ? Alfred M., are we homig in on your original post, or are we off on a new trail? Regards, Bob Elkind, the e-team, FPGA/ASIC design eteam@aracnet.com Chris Eilbeck wrote: > bob elkind <eteam@aracnet.com> writes: > > "Alfred M." wrote: > > > > > ANyone have any Orcad Capture symbols for Virtex II. Particulatly > > > in the BF957 package? > > > > Orcad CAPTURE has a builtin facility for generating schematic > > symbols from the one or more files in the Xilinx/Altera database. > > > > Look in TOOL/GENERATE PART. > > > > Works great, much more reliable than hand-entering a jillion pin > > numbers and pin names (for the umpteenth time), not to mention the > > brain-numbing experience of *checking* the symbol for boo-boos. > > That's fine for just drawing schematics but if you try and do a PCB > layout based on that netlist you end up with a whole load of pads on > the footprint with no matching connections in the netlist. OrCAD > baulked last time I did this but that was in v9.1 and things may have > changed since then. > > Chris > -- > Chris Eilbeck mailto:chris@yordas.demon.co.uk
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