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http://www.geocities.com/forsale88/xilinx/xilinx_fpgademo.jpg Hello Gurus, I would like your expert opinion on the "Xilinx FPGA Demonstration Evaluation Board". I am considering buying this board for learning and stuffs because I know someone who is selling one. The picture of the board is as shown in the link above. http://www.geocities.com/forsale88/xilinx/xilinx_fpgademo.jpg This board includes the XC3020A-7 PC68C FPGA and XC4003A-5 PC84C FPGA. However, it only comes with the board an no softwares or cables or whatever. If I purchase this board from him, what else do I need to get before I can actually plug it into my computer and start programming and seeing all the great things it can do? I suppose you need the software to at least compile the VHDL/Verilog codes and downloading it to this board. How much $$$ money $$$ do I need to spend to buy these softwares. How much will the cable for communicating with this board cost? Thanks in advance for your reply.Article: 31501
Tim, I made a mistake in posting this. It was meant for Philip only. Regarding DAC on June 18. Good idea. I will push our purchasing people to put some fire under the manufacturer. Should be possible. If it works, you can take credit for it. :-) Greetings Peter Tim wrote: > Peter > > Will copies be available at DAC? > > Peter Alfke wrote in message <3B109A36.1181949E@earthlink.net>... > >Good job! You guys must be proud, an I hope many readers will pat you on > the > >back. > >Question: How does the search work? "metastability" or "LFSR" should get > many > >hits... > > > >I have a self-burnt "early-bird" copy of the 2001 data book plus lots of > stuff > >(600 MB), and I think it is user-friendly, nothing to install etc. > >I'll mail it to you if you e-mail me your address. > > > >Greetings > >PeterArticle: 31502
Kent Orthner schrieb: > > > 1. Is this a really stupid way of doing it? Should I simply forget > about using a FPGA for this? To summarze it, you want a glitch free switching of two clocks, right ?? This can be easy done with one of Peters tricky circuits. Peter Alfke wrote a little article about glitch free clock switching in XCell Nr ???, Sorry dont know the number now. I will have a look at my archiv on Tuesday. It just takes two FlipFlops and 2 LUTs, fits easyly in the smallest CPLD (Even a 20V8 would do the job) > 4. Any other comments or suggestions would be greatly appreciated. > -- MFG FalkArticle: 31503
SN wrote: > http://www.geocities.com/forsale88/xilinx/xilinx_fpgademo.jpg > > Hello Gurus, > > I would like your expert opinion on the "Xilinx FPGA Demonstration > Evaluation Board". I am considering buying this board for learning > and stuffs because I know someone who is selling one. The picture of > the board is as shown in the link above. > > http://www.geocities.com/forsale88/xilinx/xilinx_fpgademo.jpg > > This board includes the XC3020A-7 PC68C FPGA and XC4003A-5 PC84C FPGA. > However, it only comes with the board an no softwares or cables or > whatever. > > If I purchase this board from him, what else do I need to get before I > can actually plug it into my computer and start programming and seeing > all the great things it can do? I suppose you need the software to at > least compile the VHDL/Verilog codes and downloading it to this board. > How much $$$ money $$$ > do I need to spend to buy these softwares. How much will the cable > for communicating with this board cost? Thanks in advance for your > reply. The first stop for the s/w is the Xilinx WebPack toolkit available free from Xilinx's web site **BUT** The devices on this board are 4 or 5 device generations behind the current ones so I would be very careful to check that the s/w still supports them. Best would be to download the tools & build one of the examples _before_ you commit yourself to buying the board. WebPack supports all the CPLDs, Spartan2s, and also the Virtex XCV300E and has a free synth tool called XST. On the question of cables: The cheapest is the ``Parallel-III'' which plugs into a Centronics port but, once again, you'll need to know how the board is supposed to be programmed. You might actually be better off spending a few more $$ to buy a modern Spartan2 or VirtexE development board. I believe there's a reasonably cheap one from some Australian outfit whose name escapes me at the moment [appeal to the collective NG memory ...].Article: 31504
This is a fairly old board. The 3020A is still supported in some versions
of the SW, but the 4003A is not supported by any current version of
the SW.
Free SW from Xilinx (WebPack) is the cheapest way to get started,
but I would recomend downloading it and seeing if it handles the
3020A. Note that the 3020A is now seriously retro FPGA and probably
not the best starting point for a learning experience. There are several
boards available that use more current technology from companies
such as Xess and burched
http://www.xess.com
http://www.BurchED.com.au
You will also find info on these web sites about the recomended sw
for their boards.
Good luck
Philip Freidin
On 28 May 2001 09:19:58 -0700, throne7@my-deja.com (SN) wrote:
>http://www.geocities.com/forsale88/xilinx/xilinx_fpgademo.jpg
>
>Hello Gurus,
>
>I would like your expert opinion on the "Xilinx FPGA Demonstration
>Evaluation Board". I am considering buying this board for learning
>and stuffs because I know someone who is selling one. The picture of
>the board is as shown in the link above.
>
>http://www.geocities.com/forsale88/xilinx/xilinx_fpgademo.jpg
>
>This board includes the XC3020A-7 PC68C FPGA and XC4003A-5 PC84C FPGA.
>However, it only comes with the board an no softwares or cables or
>whatever.
>
===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM
Article: 31505Hi Jonas, Is it a repetitive sequence of events? If it is not you may use two counters at different clock frequencies. It is quite easy to get a high resolution measurement using both counts. If it is: just count a lot of those events (accumulating the count) and then divide the result by the times you did the measure (beware with +/- 1 count error!!) Hope it helps, Gonzalo Arana Jonas Thor wrote: > > Hello! > > This is a not well defined question, but I'll ask anyway... I want to > measure, with high precision, the time between two rising edges of two > pulses. I have a reference clock, frequency F, of about 5-10 MHz, but > I need measurements much more accurate than 1/F. (The rising edges are > of course asynchronous to the reference clock.) > > What can I do in a FPGA get the best precison? What's the best I can > do without a DLL and with a DLL? > > Thanks for any advice! > > / Jonas ThorArticle: 31506
I have a piece of code that nicely instantiates a clock enable FF, This synthesizes into a CE FF under Exemplar Leonardo Spectrum: library ieee; use ieee.std_logic_1164.all; -- Clock Enable flip-flop entity e_ff is port ( d: in std_logic; ce: in std_logic; clk: in std_logic; rst: in std_logic; q: out std_logic ); end e_ff; architecture e_ff of e_ff is signal q0: std_logic; begin process(rst,clk,d,q0,ce) begin if (rst='0') then q0<='0'; elsif (clk'event and clk='1') then if (ce='0') then q0<=d; else q0<=q0; end if; end if; end process; q<=q0; end e_ff; "Kent Orthner" <korthner@hotmail.nospam.com> wrote in message news:wku226uu20.fsf@hotmail.nospam.com... > Hi, Dave. > > A gated clock is when you have something like the following: > > > NewClk <= Clk and ClkEn; > > This (in theory) gives you a clk signal derived from 'Clk', using 'ClkEn' > as an enable. It is called a 'gated' clock because it is derived from > Clk via some sort of logic gate, in this case an and gate. > > Using a gated clock is generally considered a Very Bad Thing. > > The first problem is if your ClkEn signal changes at some point when Clk > is not low. The signal on NewClk will include a glitch or poorly formed > pulse. > > The second problem is that there is a delay through the and gate. If you > are using Clk anywhere else in your circuit, perhaps without an enable, or > with a different enable, you are going to get your clock edges at different > times, leading to race conditions and skew problems. > > In short, using gated clocks causes a nice, reliable, synchronous design > to have all sorts of nasty asynchronous & skew-related problems. > > Unfortunately, none of these problems will show themselves in your regular > functional simulation, since usually you simulate thihgs with zero-delay. > If you do post-place & route simulation with delays, you will probably see > problems. > > when Xilinx's warning says to use the 'CE' pin, that is the enable pin on > the Flip-flop that can be used instead of modifying the clock itself. > > To use the CE pin, at least in VHDL, you need to do something like this: > > process( Clk ) is > begin > if Clk'event and Clk = '1' then -- Rising edge of Clk > if ClkEn = '1' then -- Synchronous enable. This causes ClkEn > -- to be connected to the FF's CE pin. > outsig <= insig; > end if; --enable > end if; --clk > end process; > > Hope this helps. > -Kent > > > "Speedy Zero Two" <david@manorsway.freeserve.co.uk> writes: > > I have a large design which when targeting a 300 series devices gives > > several warning, (like below). > > As this is an internal node how do I find out what to change to correct it. > > > > Cheers > > Dave > > > > > > WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net MUX_OBUF is > > sourced > > by a combinatorial pin. This is not good design practice. Use the CE pin > > to > > control the loading of data into the flip-flop.Article: 31507
I am currently using a XC2S100 in a datacomm design with Mentor FPGA Advantage tool suite and Alliance 3.1 . I am having an issue at reset where as the target is *not* in a reset state after configuration (DONE=TRUE) and is causing the board to hang. I do not have GSR connected inthe part due to design requirements. I would like to know if anyone has answers to the following questions: 1) CCLK on the Serial EEPROM is 2 MHz from the XC2S100 using master serial mode. Can I put the XC2S100 in Slave serial mode and supply another clock to both the serial EEPROM and the XC2S100? If so how fast could this go? Are their any issues with doing this? I know PROGRAM would have to be active. 2) Alliance 3.1 PAR configuration option says that I have a 4 MHz CCLK (default) why is there only a 2 MHz clock driven by the XC2S100? I would be great if I could make this faster! 3) Why doesn't the part come out of configuration in it's reset state? Thanks in advance Mike DelphiaArticle: 31508
--------------68EA2533AEB30DDFE582A9BE Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Falk Brunner wrote: > To summarze it, you want a glitch free switching of two clocks, right ?? > This can be easy done with one of Peters tricky circuits. Peter Alfke > wrote a little article about glitch free clock switching in XCell Nr > ???, Sorry dont know the number now. It's #24 http://www.xilinx.com/xcell/xl24/xl24_20.pdf We liked it so much, a more sophisticated version (both clock polarities as an option ) is incorporated on every Virtex-II global clock input. Peter > > I will have a look at my archiv on Tuesday. > It just takes two FlipFlops and 2 LUTs, fits easyly in the smallest CPLD > (Even a 20V8 would do the job) > > > 4. Any other comments or suggestions would be greatly appreciated. > > > > -- > MFG > Falk --------------68EA2533AEB30DDFE582A9BE Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>Falk Brunner wrote: <blockquote TYPE=CITE>To summarze it, you want a glitch free switching of two clocks, right ?? <br>This can be easy done with one of Peters tricky circuits. Peter Alfke <br>wrote a little article about glitch free clock switching in XCell Nr <br>???, Sorry dont know the number now.</blockquote> It's #24 <br><u><a href="http://www.xilinx.com/xcell/xl24/xl24_20.pdf">http://www.xilinx.com/xcell/xl24/xl24_20.pdf</a></u> <p>We liked it so much, a more sophisticated version (both clock polarities as an option ) is incorporated on every Virtex-II global clock input. <br>Peter <blockquote TYPE=CITE> <br>I will have a look at my archiv on Tuesday. <br>It just takes two FlipFlops and 2 LUTs, fits easyly in the smallest CPLD <br>(Even a 20V8 would do the job) <p>> 4. Any other comments or suggestions would be greatly appreciated. <br>> <p>-- <br>MFG <br>Falk</blockquote> </html> --------------68EA2533AEB30DDFE582A9BE--Article: 31509
Mike, I suggest you study the Virtex 2.5V data sheet, especially page 3-91 in the Xilinx 2000 data book, and also "start-up sequence" on page 3-95. XC2S, i.e Spartan-II is functionally identical with Virtex. Packages, pin-outs, speedfiles and chip sizes may differ, but the basic structure is the same. And I think the original Virtex documentation is more thorough. For example, it describes how you can easily switch to a higher CCLK rate... Peter Alfke, Xilinx Applications mjd001 wrote: > I am currently using a XC2S100 in a datacomm design with Mentor FPGA > Advantage tool suite and Alliance 3.1 . I am having an issue at reset where > as the target is *not* in a reset state after configuration (DONE=TRUE) and > is causing the board to hang. I do not have GSR connected inthe part due to > design requirements. I would like to know if anyone has answers to the > following questions: > > 1) CCLK on the Serial EEPROM is 2 MHz from the XC2S100 using master serial > mode. Can I put the XC2S100 in Slave serial mode and supply another clock to > both the serial EEPROM and the XC2S100? If so how fast could this go? Are > their any issues with doing this? I know PROGRAM would have to be active. > > 2) Alliance 3.1 PAR configuration option says that I have a 4 MHz CCLK > (default) why is there only a 2 MHz clock driven by the XC2S100? I would be > great if I could make this faster! > > 3) Why doesn't the part come out of configuration in it's reset state? > > Thanks in advance > > Mike DelphiaArticle: 31510
> The funny thing about a lawsuit won by Xilinx recently against Altera (which > I think has since been overturned) was that it was decided by a jury of > which only one person had any post-high-school education. I doubt that even > that one person had any knowledge of electronics. This seems to be a flaw > in the whole patent system. What's your point? The lawyers ALL knew that. This is SOP. The fact is, the average education of a juror is a 10th grade education, period. This was hardly a surprise to anyone involved in the case. The sides have to hire people who know HOW to explain this stuff to someone with that level of education. > Even really intelligent technical people in > non-FPGA fields, like my brother the software engineer, don't grasp the > concept of reconfigurable chips. It sounds to me like he'd be more of a programmer than an engineer. There is nothing at all wrong with being a programmer, but the use of the term "engineer" seems to be given to people who really aren't doing any engineering. Programmers are NOT necessarily engineers. Perhaps he is, I don't know... > The legal strategy seems to be mostly about spreading confusion amongst the > jury. I gather the trial was something like this: "Look at the Xilinx. It > has lookup tables. Look at the Altera. What do we see? Lookup tables! > A-ha!" That is, of course, completely ridiculous. The "strategy" is to explain things to the jury in such a way that they understand it, and can reach a fair decision. I take it you have no first hand knowledge of how cases like this work, or I don't believe you'd be saying this.Article: 31511
Hold the horses! This story is getting very misleading. Gating a clock is bad, gating it with an asynchronous signal is criminal. But using Clock Enable (in Xilinx chips) is the right thing to do, because it does NOT gate the clock, but rather manipulates a mux, so that - with CE not true -the D input of the flip-flop looks at its own Q, and the clock does nothing. That's the way to enable ( not "gate") the clock, and you should then use a global clock because it has almost no skew, i.e. the clock arrival time is the same for all flip-flops, give or take a hundred picoseconds. On the other hand: Virtex-II now has a real "clock gating and multiplexing" circuit at each global clock buffer input. But this is a sophisticated fail-safe circuit with a patent applied for... Peter Alfke, Xilinx Applications ================================================ Kent Orthner wrote: > Hi, Dave. > > A gated clock is when you have something like the following: > > NewClk <= Clk and ClkEn; > > This (in theory) gives you a clk signal derived from 'Clk', using 'ClkEn' > as an enable. It is called a 'gated' clock because it is derived from > Clk via some sort of logic gate, in this case an and gate. > > Using a gated clock is generally considered a Very Bad Thing. > > The first problem is if your ClkEn signal changes at some point when Clk > is not low. The signal on NewClk will include a glitch or poorly formed > pulse. > > The second problem is that there is a delay through the and gate. If you > are using Clk anywhere else in your circuit, perhaps without an enable, or > with a different enable, you are going to get your clock edges at different > times, leading to race conditions and skew problems. > > In short, using gated clocks causes a nice, reliable, synchronous design > to have all sorts of nasty asynchronous & skew-related problems. > > Unfortunately, none of these problems will show themselves in your regular > functional simulation, since usually you simulate thihgs with zero-delay. > If you do post-place & route simulation with delays, you will probably see > problems. > > when Xilinx's warning says to use the 'CE' pin, that is the enable pin on > the Flip-flop that can be used instead of modifying the clock itself. > > To use the CE pin, at least in VHDL, you need to do something like this: > > process( Clk ) is > begin > if Clk'event and Clk = '1' then -- Rising edge of Clk > if ClkEn = '1' then -- Synchronous enable. This causes ClkEn > -- to be connected to the FF's CE pin. > outsig <= insig; > end if; --enable > end if; --clk > end process; > > Hope this helps. > -Kent > > "Speedy Zero Two" <david@manorsway.freeserve.co.uk> writes: > > I have a large design which when targeting a 300 series devices gives > > several warning, (like below). > > As this is an internal node how do I find out what to change to correct it. > > > > Cheers > > Dave > > > > > > WARNING:DesignRules:372 - Netcheck: Gated clock. Clock net MUX_OBUF is > > sourced > > by a combinatorial pin. This is not good design practice. Use the CE pin > > to > > control the loading of data into the flip-flop.Article: 31512
These sites pays for each e-mail you read. The e-mails are marked from them so you don't have to sift thru spam to get to the payed e-mail. It is easy and works well. I did not put in my SSN # on the registration as it was not required. http://curtisjon.tripod.com/money.htmArticle: 31513
"Win Hill" <whill@mediaone.net> wrote in message news:3B126CD9.5D32311E@mediaone.net... > Aaron Nabil wrote: ... > > The Xilinx Foundation series seems more powerful than WebPACK, > with schematic capture, timing analysis, etc., but one rumor is > that they are moving to a free WebPACK as their standard package. > About stinkin' time!!!! -- EdArticle: 31514
Kent, I designed redundant telecom systems for twenty years. I used FPGAs since they were first invented (2016 and 2064 in a T1 APS). I will attempt to answer below. Austin Kent Orthner wrote: > I'm perhaps doing something really dumb, and trying to use an FPGA > for something it's not meant to do. But to a guy with a hammer, > everything looks like a nail, right? > > I'm implementing a redundant system. On each card, (There's about 6 > cards in a chassis) there will be two nominally 52MHz clock inputs. > The system controller will select which of the two clocks to use. > > I'm thinking of using an FPGA on each card to perform the clock > switching. If I feed the switched clock into a DLL, then I imagine > that the transition from one clock to the other has to be pretty smooth. > > I imagine the setup as follows (Using Spartan-II): > > Clk0 an Clk1 and Select are input pins, all going to a LUT3, which drives > ClkSelected. I can not connect this to a DLL, so I drive it off-chip, and > then back on-chip, to *then* connect it to a DLL. The output of the DLL > then goes outside to the real world where it drives a 'zero delay clock > buffer', which drives all of the devices on that card. > > I have a couple of questions that hopefully someone can help me with: > > 1. Is this a really stupid way of doing it? Should I simply forget > about using a FPGA for this? The DLL requires the next clock input rising edge to be exactly where it is supposed to be, +/- 350 ps (LF mode). If it isn't, it stops. If the clocks are switched ahead of a PLL, then the PLL's output will change in frequency slowly enough for the DLL to track it. This technique is used by many customers (PLL ahead of DLL for clock discontinuity smoothing). A DLL can track incredibly fast, ~60ps per clock edge! That adds up pretty fast for say 100 edges = +/-6 ns total period change. There are some setting s that need to be optimized (jitter filters). > > > 2. How well do the simulation models of the DLLs in the unisim library > model the real DLLs? The logic funtion is there, but the timing relationships are fixed, and not really useful for what you have in mind. > > > 3. If I use the same device in the same package with the same place & > route for the FPGA on all line cards, what can I expect my worst case > device-to-device clock skew to be? In Virtex E, the error in the DLL to the global clock bus is a fixed amount, and is less than 100 ps. There is some error from the global clock bus to any CLB and IOB on chip as well. Consult the timing report for details. I believe is is another 100 ps. > > > 4. Any other comments or suggestions would be greatly appreciated. > I use PLL's ahead of DLL's for the reasons stated above, and I use PLL's after DLL's to remove all of the jitter that results in a digital system if needed for A/D conversions, etc. DLL's are great for some things (skew management, delay control, etc). PLL's are great for some of the things they do well. > > Thanks in advance. > > -KentArticle: 31515
SN wrote in message ... >If I purchase this board from him, what else do I need to get before I >can actually plug it into my computer and start programming and seeing >all the great things it can do? I suppose you need the software to at >least compile the VHDL/Verilog codes and downloading it to this board. > How much $$$ money $$$ >do I need to spend to buy these softwares. How much will the cable >for communicating with this board cost? Thanks in advance for your >reply. I built the cable myself for around $15 worth of parts from Radio Shack. Suprisingly, they stocked everything that is needed. Boy is it ugly though... next one I build will be prettier, I think. (Side note: I'm considering building a big box with a bunch of plcc sockets, and wiring that up as a programmer. Can the schematics be easily modified to program more than one chip at a time? Is it worth the effort?) The Xilinx webpack is free. Seems to have everything necessary, even if I don't know what I'm doing. Expect a high learning curve. Thanks, JohnArticle: 31516
> You might actually be better off spending a few more $$ to buy a modern > Spartan2 or VirtexE development board. I believe there's a reasonably > cheap one from some Australian outfit whose name escapes me at the moment > [appeal to the collective NG memory ...]. > Burch Electronic Designs are the Australians, or Aussies, as we say :) http://www.BurchED.com.au We now have stocks of the B3-SPARTAN2+ board, which works with the free Xilinx Webpack software. The board has a 200K gate (!) Spartan2 device, and comes with all the cables and hardware that you will need. It is priced at less than US$120! International orders are very welcome. Best regards Tony Burch http://www.BurchED.com.au Lowest cost, easiest-to-use FPGA prototyping kits!Article: 31517
Hi, I would like to announce My80 processor core which is written with SFL. It can fit into an ALTERA EPF10K30 or an ALTERA EPF6016 CPLD. (Sorry We don't have any XLNX tools) We got CP/M boot with success, and also got Mbasic run fine on it. See more in http://shimizu-lab.et.u-tokai.ac.jp/pgm/my80/index.html Regards, Naohiko Shimizu Dept. Communication Engr./Univ. TOKAI 1117 Kitakaname Hiratsuka 259-12 Japan TEL.+81-463-58-1211(ext. 4084) FAX.+81-463-58-8320 http://shimizu-lab.et.u-tokai.ac.jp/Article: 31518
Aaron Nabil wrote: > > Got an old copy of ABEL around? I need one for a project, > the complete kit (ie, legal) with a key. Prefer version 6 > but 5 might work. > > I might be able to use Minc Synario, but I'm not sure. > > Viewlogic viewpld/propld might work. > > Please drop me a line if you have one you would like to > sell. What device(s) do you need to target ? - there were various verions of Abel/Synario. -jgArticle: 31519
On Sun, 27 May 2001 18:20:02 -0400, Kuan Zhou <zhouk@rpi.edu> wrote: >Hi, > Does anyone here know where to find the LVDS circuit >description for Virtex II? > >sincerely >------------- >Kuan Zhou > There are some good application notes on LVDS at National Semiconductor. The circuits used by the Virtex chips should not differ too much. Best regards Klaus Falser Klaus R&D Electronics Department Company : Durst Phototechnik AG Vittorio Veneto Str. 59 I-39042 Brixen Voice : +0472/810235 : +0472/810111 FAX : +0472/830980 Email : kfalser@IHATESPAMdurst.itArticle: 31520
Peter Alfke wrote: > > On the other hand: Virtex-II now has a real "clock gating and multiplexing" > circuit at each global clock buffer input. But this is a sophisticated fail-safe > circuit with a patent applied for... > Peter, If this is your little wonder circuit I hope your employers will be gating some of the royalties in your direction.Article: 31521
Peter Alfke wrote: > > Hold the horses! This story is getting very misleading. > > Gating a clock is bad, gating it with an asynchronous signal is criminal. > But using Clock Enable (in Xilinx chips) is the right thing to do, because it > does NOT gate the clock, but rather manipulates a mux, so that - with CE not > true -the D input of the flip-flop looks at its own Q, and the clock does > nothing. > That's the way to enable ( not "gate") the clock, and you should then use a > global clock because it has almost no skew, i.e. the clock arrival time is the > same for all flip-flops, give or take a hundred picoseconds. > > On the other hand: Virtex-II now has a real "clock gating and multiplexing" > circuit at each global clock buffer input. But this is a sophisticated fail-safe > circuit with a patent applied for... Hi Peter, Are you able to post a (link to) the circuit? I can see its description in the databook, but no internal details. AIUI, this circuit must contain bistable elements, and therefore is subject to metastability. Thus there is a finite (albeit small) chance that the output will be corrupted when switching clocks. Or am I missing something? From the description, it looks like there's half a clock cycle worth of metastability resolution time, which should be enough to reduce the probability of failure to something that is vanishingly small. Is this how you made it "fail safe?" Regards, Allan.Article: 31522
Peter Alfke wrote: > > Falk Brunner wrote: > > > To summarze it, you want a glitch free switching of two clocks, > > right ?? > > This can be easy done with one of Peters tricky circuits. Peter > > Alfke > > wrote a little article about glitch free clock switching in XCell Nr > > > > ???, Sorry dont know the number now. > > It's #24 > http://www.xilinx.com/xcell/xl24/xl24_20.pdf > > We liked it so much, a more sophisticated version (both clock > polarities as an option ) is incorporated on every Virtex-II global > clock input. > Peter I think the original problem is more complicated. The reason for making a redundant system is to improve the reliability of the system. Peter's cirquit requires both clocks to be operational in order to switch. You cannot make that assumption in a hich reliability system. It will reduce the reliability of the system. I would be very careful about using these glitch free global clock MUXes of the Virtex II in a fault tolerant or high reliability system. I hope the glitch free feature can either be disabled or that it allows switching from a dead clock to a working one. /Anders RamdahlArticle: 31523
> > > On the other hand: Virtex-II now has a real "clock gating and multiplexing" > > circuit at each global clock buffer input. But this is a sophisticated fail-safe > > circuit with a patent applied for... > > Hi Peter, > > Are you able to post a (link to) the circuit? I can see its description > in the databook, but no internal details. > > AIUI, this circuit must contain bistable elements, and therefore is > subject to metastability. Thus there is a finite (albeit small) chance > that the output will be corrupted when switching clocks. Or am I > missing something? > > From the description, it looks like there's half a clock cycle worth of > metastability resolution time, which should be enough to reduce the > probability of failure to something that is vanishingly small. Is this > how you made it "fail safe?" Peter could for example post the patent ID. Kolja SulimmaArticle: 31524
Atmel ATV750/ATF750. -a "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3B1331AE.7244@designtools.co.nz... > Aaron Nabil wrote: > > > > Got an old copy of ABEL around? I need one for a project, > > the complete kit (ie, legal) with a key. Prefer version 6 > > but 5 might work. > > > > I might be able to use Minc Synario, but I'm not sure. > > > > Viewlogic viewpld/propld might work. > > > > Please drop me a line if you have one you would like to > > sell. > > What device(s) do you need to target ? - there were various verions of > Abel/Synario. > > -jg
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