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Vladislav Vasilenko ha scritto nel messaggio <3B1C930E.21EEDC1F@comsys.ntu-kpi.kiev.ua>... >Hi Alfredo, > >"..Xilinx keeps the interpretation of the bitstream a closely guarded >secret.." It's >quotation from Xilinx "The Programmable Logic Data Book ". > >Best regards, Vlad. Yes, I can trust in Xilinx. But I suppose the every manufacturer has to give the full informations about the bitstream and internal structure to the companies doing the development tools... LuigiArticle: 31751
Hi, I have generated a working bit file for an XCS10XL ... do I need a BSDL file to use the Xilinx JTAG programmer? The programmer seems to be loading the generic .bsd file for the XCS10XL. Programmer keeps on complaining about the fact that my boundary scan chain has been declared incorrectly... I don't want to use any boundary scans. NewbieArticle: 31752
> > > Suprisingly, Synplify decided that this was best implemented as a > > one-hot, and used 6 flip flops and 3 LUTs. > > Usually, the best implementation of a statemachine in an FPGA is one-hot. if (log(number_of_states) + number_of_inputs_bits < 5) binary encding is allways optimal. (log DFFs and one LUT per DFF. Only a shioft register can do better) I encounter an surprisingly large amount of these small state machines. Synthesis should cope with that. Kolja SulimmaArticle: 31753
Kent Orthner <korthner@hotmail.nospam.com> writes: > I seem to remember somewhere that to specify the initial contents of a > RAM or LUT, you need to use an attribute, that the synthesizer will > not grab it from the generic. Sorry I forgot to mention this before. Ah. As an aside, is this a general rule of thumb? Passing info to simulation is done using generics and synthesis using attributes? > Take a look at Xilinx answer 10070, I think it's exactly what you're > looking for. Excellent - that clears it up. Many thanks. I did search support.xilinx.com, but failed to find that answer. > A quick question: Why do you want to instantiate the LUT4 instead of > describing what you want, and lettig the synthesizer do the rest? I have a implementation of a single twofish round. The idea is that using LUTs to explicity place the key into the circuit would make it possible (if one knew the Virtex bitstream format, and the location of how the key was placed in the circuit) to do a very simple "partial evaluation" of the key into the circuit before the circuit was loaded. For the key I actually use a series of LUT1s - this may be inefficient in terms of area, but my idea depends on my ability to locate a replace the the key simply. It is also a requirement of my project that I don't use RAM blocks (I'm trying to predict the performance of a processor that had Virtex fabric attached to it - but having large amounts of state in a processor is a bad idea, so I assume that RAM blocks wouldn't be allowed). Probably more info than you wanted to know ;) Cheers again, and to all the others that replied. Much appreciated. -- Michael Dales --- email: michael@dcs.gla.ac.uk --- tel: +44 141 330 6297 Department of Computing Science, University of Glasgow, Glasgow, G12 8QQArticle: 31754
Hello, Your code gives 3 (Lcs+FF) as expected. Just one logic level. i used FPGA-EXPRESS, but i had tp add this line when others => null; at the end of the "case" body. otherwise i got the following error cnt does not cover all the states, even it does!!!! bsulliva@altera.com (Brian_Sullivan) wrote in message news:<85de1ece.0106041356.4b5ffc83@posting.google.com>... > Hi, > > Maybe I'm misunderstanding, but you want to use 3 Logic Cells (4 input > LUT + DFFE) to make a counter that counts in the following sequence: > > 4, 7, 2, 3, 0, 1, 6, 5 > > I usually do not post as most people here are Xilinx users and > probably don't want to hear from the Altera peanut gallery, but if you > specifically state that you want 3 bits in the vector by using > STD_LOGIC, then you will achieve your goal. The code will look like > this: > > library ieee; > use ieee.std_logic_1164.all; > > entity mod8cnt is port ( > clk : in std_logic; > q : out std_logic_vector(2 downto 0) > ); > end mod8cnt; > > architecture logic of mod8cnt is > > signal cnt : std_logic_vector(2 downto 0); > > begin > > process (clk) begin > if rising_edge(clk) then > case cnt is > when "100" => cnt <= "111"; > when "111" => cnt <= "010"; > when "010" => cnt <= "011"; > when "011" => cnt <= "000"; > when "000" => cnt <= "001"; > when "001" => cnt <= "110"; > when "110" => cnt <= "101"; > when "101" => cnt <= "100"; > end case; > end if; > end process; > > q <= cnt; > > end logic; > > This gives 3 LC in an APEX20KE device through Synplify. I do not have > accesss to Xilinx tools, so I cannot comment on that. Let me know if > this helps. > > Brian Sullivan > FAE Specialist > Eastern North America > Altera CorporationArticle: 31755
Hi!
I've got a problem with assigning the global clock and
reset logic to the pins of a MAX7000 device.
The Max-Plus II gives the following kind of error messages:
Error: Illegal assignment - global clock 'button_reset' on pin 37
or
Error: Illegal assignment - global clock 'clk' on pin 28
when trying to have anything like that:
(depends which signal is trying to trigger the counter)
I'd be very grateful for any kind of advice
entity foo is
port ( clk, button_reset, button_stop : in std_logic;
out_value: out unsigned(0 to 14) );
end entity foo;
...
process is
begin
if button_reset='1' then
counter := 0;
elsif clk'event AND clk='1' then
counter := counter +1;
end if;
out_value <= conv_unsigned(counter, 15);
end process;
--
Miika
Article: 31756If it's Virtex info you're after then Xilinx App-note 151 may be of some use. -- Michael Dales --- email: michael@dcs.gla.ac.uk --- tel: +44 141 330 6297 Department of Computing Science, University of Glasgow, Glasgow, G12 8QQArticle: 31757
> > Yes, I can trust in Xilinx. > But I suppose the every manufacturer has to give the full informations > about the bitstream and internal structure to the companies doing the > development tools... Internal structure of the device, YES, for synthesis tool developers. Bitstream format, NO. The tools for generating the bitstream are, as far as I know, only made by.....Xilinx. /ThomasArticle: 31758
On 5 Jun 2001 05:04:22 -0700, finishf@yahoo.com (finish) wrote: >Hello, > >Your code gives 3 (Lcs+FF) as expected. Just one logic level. i used >FPGA-EXPRESS, but i had tp add this line >when others => null; >at the end of the "case" body. otherwise i got the following error >cnt does not cover all the states, > > even it does!!!! No. STD_LOGIC(_VECTOR) states also include 'U', 'X', 'H', 'L', 'W', '-', and 'Z'. All combinations using these are not covered in the example (they "never" are), hence the need for the "when others" clause in "all" case statements. ---- Keith ========================== >bsulliva@altera.com (Brian_Sullivan) wrote in message news:<85de1ece.0106041356.4b5ffc83@posting.google.com>... >> Hi, >> >> Maybe I'm misunderstanding, but you want to use 3 Logic Cells (4 input >> LUT + DFFE) to make a counter that counts in the following sequence: >> >> 4, 7, 2, 3, 0, 1, 6, 5 >> >> I usually do not post as most people here are Xilinx users and >> probably don't want to hear from the Altera peanut gallery, but if you >> specifically state that you want 3 bits in the vector by using >> STD_LOGIC, then you will achieve your goal. The code will look like >> this: >> >> library ieee; >> use ieee.std_logic_1164.all; >> >> entity mod8cnt is port ( >> clk : in std_logic; >> q : out std_logic_vector(2 downto 0) >> ); >> end mod8cnt; >> >> architecture logic of mod8cnt is >> >> signal cnt : std_logic_vector(2 downto 0); >> >> begin >> >> process (clk) begin >> if rising_edge(clk) then >> case cnt is >> when "100" => cnt <= "111"; >> when "111" => cnt <= "010"; >> when "010" => cnt <= "011"; >> when "011" => cnt <= "000"; >> when "000" => cnt <= "001"; >> when "001" => cnt <= "110"; >> when "110" => cnt <= "101"; >> when "101" => cnt <= "100"; >> end case; >> end if; >> end process; >> >> q <= cnt; >> >> end logic; >> >> This gives 3 LC in an APEX20KE device through Synplify. I do not have >> accesss to Xilinx tools, so I cannot comment on that. Let me know if >> this helps. >> >> Brian Sullivan >> FAE Specialist >> Eastern North America >> Altera CorporationArticle: 31759
Can anyone give me some advice about selection of software for the Xilinx devices? I was until recently using the Foundation 2.1 series tools through the unversity where I work. Now the university has switched to ISE. This would not be a problem except that they have not gotten the model sim license. Thus I cannot simulate my devices properly. So... does anyone have any advice. I need to either purchase the new software to do things right or get some sort of simulation software or whatever. I am only using the Spartan XL devices at present and probably will stick with them for the near future. I don't like the possibility of having to repurchase a license every year. We are using logicBLOX and I will require logicBLOX. Thanks, Theron HicksArticle: 31760
Can anyone give me some advice about selection of software for the Xilinx devices? I was until recently using the Foundation 2.1 series tools through the unversity where I work. Now the university has switched to ISE. This would not be a problem except that they have not gotten the model sim license. Thus I cannot simulate my devices properly. So... does anyone have any advice. I need to either purchase the new software to do things right or get some sort of simulation software or whatever. I am only using the Spartan XL devices at present and probably will stick with them for the near future. I don't like the possibility of having to repurchase a license every year. We are using logicBLOX and I will require logicBLOX. Thanks, Theron HicksArticle: 31761
Alfredo Benso wrote: > > Hi everybody, > I am a researcher at Politecnico di Torino in Italy. > I am looking for information about the format of the Xilinx configuration > bit stream. Is the format public? Is there some document or file available > explaining how to generate a stream of configuration bits for a Xiling FPGA? > > Anybody can help? Take a look at JBits, which is a Java API giving read and write access to a Virtex configuration stream. You can find details on the Xilinx web site. Or Xilinx App. Note XAPP151 gives some information too on the configuration format for Virtex. Phil -- --------------------------------------------------------------------- __ / /\/ Dr Phil James-Roxby Direct Dial: 303-544-5545 \ \ Staff Software Engineer Fax: Unreliable use email :-) / / Loki/DARPA Email: phil.james-roxby@xilinx.com \_\/\ Xilinx Boulder ---------------------------------------------------------------------Article: 31762
Hi, Exactly what device and package type in the MAX7000-family are you using? I think you should make sure that you are using a dedicated input pin GCLK for the clock signal and GCLR for the reset signal, and the location of those pins may differ between device/package combinations /Thomas "Miika Pekkarinen" <miipekk@tukki.jyu.fi> wrote in message news:9fii43$c2b@tukki.jyu.fi... > Hi! > > I've got a problem with assigning the global clock and > reset logic to the pins of a MAX7000 device. > > The Max-Plus II gives the following kind of error messages: > > Error: Illegal assignment - global clock 'button_reset' on pin 37 > or > Error: Illegal assignment - global clock 'clk' on pin 28 > > when trying to have anything like that: > > (depends which signal is trying to trigger the counter) > > I'd be very grateful for any kind of advice > > > > > entity foo is > port ( clk, button_reset, button_stop : in std_logic; > out_value: out unsigned(0 to 14) ); > end entity foo; > > ... > > process is > begin > > if button_reset='1' then > counter := 0; > elsif clk'event AND clk='1' then > counter := counter +1; > end if; > > out_value <= conv_unsigned(counter, 15); > end process; > > -- > > Miika >Article: 31763
hello, Xilinx says that with virtex Bram the user can use on chip buffering. i have a friend who is performing real time system perfectly using (still) off chip-ram. so can someone numerate me, with real examples, the advantages from using on-chip rather than off-chip buffering ( please, i am full from bottleneck and similair terminology) thanks you in advance H.SArticle: 31765
hello, Xilinx says that with virtex Bram the user can use on chip buffering. i have a friend who is performing real time system perfectly using (still) off chip-ram. so can someone numerate me, with real examples, the advantages from using on-chip rather than off-chip buffering ( please, i am full from bottleneck and similair terminology) thanks you in advance H.SArticle: 31766
miipekk@tukki.jyu.fi (Miika Pekkarinen) wrote in message news:<9fii43$c2b@tukki.jyu.fi>... > Hi! > > I've got a problem with assigning the global clock and > reset logic to the pins of a MAX7000 device. > > The Max-Plus II gives the following kind of error messages: > > Error: Illegal assignment - global clock 'button_reset' on pin 37 > or > Error: Illegal assignment - global clock 'clk' on pin 28 > > when trying to have anything like that: > > (depends which signal is trying to trigger the counter) > > I'd be very grateful for any kind of advice > > > > Whichever package you've chosen, those pins are not the dedicated global pins. If the board is already laid out and you want to keep the pins you've chosen, go to the Assign menu. Then choose Global Project Logic Synthesis... In the bottom right hand of the window will be the automatic global section. Turn those to off and the design should fit. If those pins you chose were arbitrary, just remove the assignments and MAX+PLUS II will put the signals on the dedicated pins for you (assuming the auto global is turned on). I hope this helps.Article: 31767
Noddy schrieb: > > Hi, > > I have generated a working bit file for an XCS10XL ... do I need a BSDL file > to use the Xilinx JTAG programmer? The programmer seems to be loading the > generic .bsd file for the XCS10XL. Simply use the hardware debugger and do a serial (NOT JTAG) download. (Nevertheless the bsd file should be installed) -- MFG FalkArticle: 31768
The advantage of on-chip RAM is very much faster access, freedom to choose the width from 1 bit to 36 bits, and no external pins used for address, data, and control. The disadvantage of on-chip RAM is its limited size, up to about 100 RAMs of 18 kilobits each = less than 2 megabits, i.e. less than 250 kilobytes. In all Xilinx chips you can also use the look-up tables as 16-bit RAM. That can give you one more megabit, at the high end. Peter Alfke, Xilinx Applications hristo wrote: > hello, > > Xilinx says that with virtex Bram the user can use on > chip buffering. i have a friend who is performing real > time system perfectly using (still) off chip-ram. so > can someone numerate me, with real examples, the > advantages from using on-chip rather than off-chip > buffering ( please, i am full from bottleneck and > similair terminology) > > thanks you in advance > H.SArticle: 31769
> No. STD_LOGIC(_VECTOR) states also include 'U', 'X', 'H', 'L', 'W', > '-', and 'Z'. All combinations using these are not covered in the > example (they "never" are), hence the need for the "when others" > clause in "all" case statements. > > ---- > Keith > > ========================== That is true. In most cases, the when others => null; should be used. When I ran it through, the synthesis tool I used understood that in an FPGA or CPLD only '1' and '0' can be reached.Article: 31770
On 5 Jun 2001 09:41:58 -0700, bsulliva@altera.com (Brian_Sullivan) wrote: >> No. STD_LOGIC(_VECTOR) states also include 'U', 'X', 'H', 'L', 'W', >> '-', and 'Z'. All combinations using these are not covered in the >> example (they "never" are), hence the need for the "when others" >> clause in "all" case statements. >> >> ---- >> Keith >> >> ========================== > >That is true. In most cases, the when others => null; should be used. > When I ran it through, the synthesis tool I used understood that in >an FPGA or CPLD only '1' and '0' can be reached. True, a given synthisis tool may understand only '1' and '0' and thus support only a subset of VHDL (a dangerous thing, IMO). What about simulation? Hmmm, sitting here thinking about this (and browsing Ashenden), I just realized I didn't need the "when others" clause in my FSMs because I use enumeration types (Synplify figures out the messy stuff) and have all possible states defined. ...well it doesn't hurt! ;-) ---- KeithArticle: 31771
System Generator is an admittedly young tool, that has strengths and weaknesses, some described by Kevin and others. An original goal was (and remains) to provide a system level abstraction for FPGA design, initially targeting DSP applications. This entails both bit and cycle true modeling of the system in a simulation environment, and generating an implementation from this system model. Raising the level of abstraction makes the tool usable by those (primarily or initially) more concerned with algorithm development and exploration than with (hardware) implementation details. For example, it is often easier to specify a multi-rate system or algorithm in terms of sample rates than by wiring explicit clocks, clears, and enables. Sample time and data type propagation rules supported in the simulation environment make it is possible to modify system parameters, even in the midst of a simulation, which would be cumbersome or impossible in more traditional HDL or schematic flows. At the same time, providing a bit and cycle true model ensures that the system designer can evaluate some of the costs and tradeoffs of the implementation (you certainly get useful bounds...quickly). This flexibility naturally comes at a price, which can be further accentuated by the tool's relative youth. For example, a generated implementation may not be as compact or as fast as a hand-crafted solution. System Generator targets IP cores when possible to provide hand-crafted implementations of library elements, but this will certainly not guarantee optimality under any sensible measure. That said, there are also many instances (uncontrived and realistic) where a SysGen model will give you an excellent FPGA implementation in absolutely the quickest amount of time. Compiler and logic synthesis technologies have improved over time (do you really never have to write structural HDL to get exactly the implementation you want in hardware?), and so too will visual approaches like System Generator. Although it was not conceived as a low level digital design tool, the quality of result and ability of the user to customize an implementation will certainly improve over time, through enhancements and refinements of the tool itself, as well as in the IP libraries that it targets. The opportunity for algorithm exploration and quick implementation as well as the ability to readily construct realistic test benches for DSP applications in visual tools like System Generator as opposed to the alternatives, makes the tool of (hopefully considerable) interest, even in its current form. As to Cy's original closing comment, an impartial (read "non corporate") forum/database for discussions in this area would be extremely welcome and timely. --jim Jim Hwang Vertical Products Software, Xilinx, Inc. Kevin Neilson wrote: > [cut] > > The tools work very well in terms of making a DSP design easier and perhaps > more intuitive. However problems crop up on the leading edge. Analagous is > how a compiler makes software design much easier but loses out to assembly > in very critical applications. > > If you can meet timing, everything is fine. But in one case, I couldn't > meet timing with the generated code. It was necessary to use several > tricks, like duplicating logic similar to Shannon expansion and manually > reducing fanout on critical nets. The high-level tools don't deal with > these low-level problems. Therefore I had to manually edit the code. This > was a huge task, because the source generated is functionally but nearly > unintelligible, with netnames such as n_98742 and every register set buried > in its own module. Again, it was like editing assembly generated by a C > compiler. Also, there are tricks such as using a single BRAM as two > indpendent ROMs (saving half your BRAMs) which I don't think the generation > tools can deal with. In this case, I may have saved a lot of time by > writing all the source instead of using code generated by the tool. What I > am left with is a bunch of unreadable hacked code, which cannot be modified > by anyone else (nor myself), nor can the tool be used to tweak any > parameters, because generating source from the tool again would not include > my hacks. > > In summary, I believe these tools may save time, but only when there is > plenty of margin to deal with. > > -Kevin > > "cybin" <cybin@home.com> wrote in message news:3B19B9EE.56137102@home.com... > > I've been using system Generator for three months since it's release and > > have found somewhat erratic performance. I would be interested in > > sharing my experience with other System Generator users in hopes of > > finding and sharing solutions that would be of benefit to all. Perhaps a > > data base could be constructed outside the Xilinx infrastructure for > > this purpose. > > > > Regards, > >Article: 31772
> >"..Xilinx keeps the interpretation of the bitstream a closely guarded > >secret.." It's > >quotation from Xilinx "The Programmable Logic Data Book ". > > > >Best regards, Vlad. > > > Yes, I can trust in Xilinx. > But I suppose the every manufacturer has to give the full informations > about the bitstream and internal structure to the companies doing the > development tools... No. NeoCAD had to decode it on their own, and they are the only people I know who ever decoded the Xilinx bitstream... They were bought by Xilinx some time ago... The only people who need the bitstream are the people developing the back end tools, NOT the design entry tools.Article: 31773
On Tue, 05 Jun 2001 23:32:45 +0200, Kolja Sulimma <kolja@sulimma.de> wrote: > > >"Keith R. Williams" wrote: > >> On 5 Jun 2001 09:41:58 -0700, bsulliva@altera.com (Brian_Sullivan) >> wrote: >> >> >> No. STD_LOGIC(_VECTOR) states also include 'U', 'X', 'H', 'L', 'W', >> >> '-', and 'Z'. All combinations using these are not covered in the >> >> example (they "never" are), hence the need for the "when others" >> >> clause in "all" case statements. >> >> >> >> ---- >> >> Keith >> >> >> >> ========================== >> > >> >That is true. In most cases, the when others => null; should be used. >> > When I ran it through, the synthesis tool I used understood that in >> >an FPGA or CPLD only '1' and '0' can be reached. >> >> True, a given synthisis tool may understand only '1' and '0' and thus >> support only a subset of VHDL (a dangerous thing, IMO). What about >> simulation? > >A synthesis tool generates synthesis results. >Signals in synthesis results in FPGA (And usually in CMOS ASIC, too) can >only generate the values >1, 0, Z, WH, WL and not the four other values of STD_LOGIC. >Furthermore, any of these states, including Z can not be distinguished from >1 or 0 by the hardware. Sure, but VHDL isn't hardware. It is a computer language. The language (and standard libraries) "know" that '1' and '0' don't define all possible values of std_logic. Having a compiler that knows what parts of the language/libraries are important to the resultant hardware is a dangerous thing, IMO. VHDL is reduced to hardware during mapping to the technology. At this point I don't really care if it's VHDL or not. >Because of this, a case statetement is completely defined, as far as >synthesis is concerned, if all combinations of 1 and 0 are coverd. Again, this is in the map phase of synthesis. The compiler should object to having combinations of valid values left out. I believe this behavior is specified in the language. >By decoding these combinations the circuit can then generate the values 1, >0, Z, WH and WL. >Netlist simulation will reflect this behaviour. Sure, but what about RTL simulation? I take my source code from Synplify and simulate it on ModelSim and expect the compilers to behave the same (for synthesizable code). It doesn't always work that way, but if Synplify assumed only '1' and '0', I'd be in trouble when I compiled it for synthesis. >A statement of the type > >when 'Z' => .count <= count +1; > >would result in a synthesis error anyway. Sure. So? I still want my compiler to recognize it as a valid statement. It can cry about not being able to synthesize it all it wants. >Even more so, the synthesis results in the above example are not entirely >correct: >The suggested code > >when others => null; > >specifies, that the counter must not count if the value is Z, WH, WL, X, .. > >The synthesis tools can not comply with that rule. >when others => count <= "----"; > >would be more exact with respect to that. Good point. Hmmm, gotta think about how that affects my use. ---- KeithArticle: 31774
"Keith R. Williams" wrote: > On 5 Jun 2001 09:41:58 -0700, bsulliva@altera.com (Brian_Sullivan) > wrote: > > >> No. STD_LOGIC(_VECTOR) states also include 'U', 'X', 'H', 'L', 'W', > >> '-', and 'Z'. All combinations using these are not covered in the > >> example (they "never" are), hence the need for the "when others" > >> clause in "all" case statements. > >> > >> ---- > >> Keith > >> > >> ========================== > > > >That is true. In most cases, the when others => null; should be used. > > When I ran it through, the synthesis tool I used understood that in > >an FPGA or CPLD only '1' and '0' can be reached. > > True, a given synthisis tool may understand only '1' and '0' and thus > support only a subset of VHDL (a dangerous thing, IMO). What about > simulation? A synthesis tool generates synthesis results. Signals in synthesis results in FPGA (And usually in CMOS ASIC, too) can only generate the values 1, 0, Z, WH, WL and not the four other values of STD_LOGIC. Furthermore, any of these states, including Z can not be distinguished from 1 or 0 by the hardware. Because of this, a case statetement is completely defined, as far as synthesis is concerned, if all combinations of 1 and 0 are coverd. By decoding these combinations the circuit can then generate the values 1, 0, Z, WH and WL. Netlist simulation will reflect this behaviour. A statement of the type when 'Z' => .count <= count +1; would result in a synthesis error anyway. Even more so, the synthesis results in the above example are not entirely correct: The suggested code when others => null; specifies, that the counter must not count if the value is Z, WH, WL, X, .. The synthesis tools can not comply with that rule. when others => count <= "----"; would be more exact with respect to that. Kolja Sulimma
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