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I've half done one. Just need to implement some fifo... Chaudhry wrote: > > Have anybody used FPGA device to control STN LCD panels either 16 bit or 24 > bit? > > What is the possibility to do it ? we have a lots of stock of 6" STN panels > so we want to make standalone monitor for Video or VGA interface or both. > All the controllers for STN LCD's are either ISA or PCI based which is not > suitable for our application. > > Any comments will be appreciated. > > Regards, > > -- > *********************** > Chaudhry > ICQ# 11502664 > Singapore > *********************** -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 31951
Ray Andraka wrote: > > The problem yo are having is a mismatch between what the place and route > needs and what the simulation needs. For simulation, you need to > specify the INIT generic, as you have done. Simulation uses that to > apply the LUT function to the LUT component. The synthesizer won't do > anything with the generic, and in fact will usually either complain or > generate a different black box for the primitive (depends on the > synthesis tool...SYnplicity will create a unique black box and issues a > warning that it doesn't know what to do with generics on black boxes). > > The synthesis just puts down a LUT if you instantiate one. It doesn't > create an init attribute unless it inferred the LUT. You need to add an Actually, if you instantiate a LUT4 with a INIT generic/parameter in Synplify it will work fine and produce a LUT in the output EDIF programed with your INIT generic. If you are using verilog, you will need to include .../synplify/lib/xilinx/virtex.v and for VHDL you need to use the stmts. library virtex; use virtex.components.all; LUTS have been special cased. > INIT= attribute to the LUT instantiation to get the contents into the > implemented design. If you do not, then the LUT gets loaded with a > default init value of X"0000". Unfortunately, as you have found, this > means another opportunity to have your implemented code behave > differently than the simulation. You can gt around that by either not > using LUTs (if using synplicity, you can put RTL code for the logic that > goes in a LUT in a separate component and use the synplicity xc_lut or > xc_fmap attributes to get the same effect as an FMAP), or by writing > your code so that it derives the init generic and init attribute values > from the same source. The formats for the two are also different: the > generic is a bit vector and the attribute is a hex string. THe snippet > below is for a design that preloads an SRL16, but the idea is the same > itoh is a home-spun function to convert an integer to a hex string and > int2bit_vec is one that converts an integer to a bit vector. The > translate on and off pragmas are necessary to hide the generics on the > primitive, which is a black box from the synthesizer. Note both values > are functions of the same integer in this code, so I only need to test > that the translations work correctly once, then I should always get > simulations that match the hardware. > > --INIT= attribute to pass to PAR through synplicity > attribute INIT of U1 : label is itoh(lut_init); > begin > U1: SRL16E > --synthesis translate_off > -- init generic is for simulation model, not seen by Synplicity or PAR > generic map ( > INIT => int2bit_vec(lut_init,16)) > --synthesis translate_on > port map ( > Q => y, > > Michael Dales wrote: > > > Hi there, > > > > I'm trying to implement an algorithm using the LUT4 on Virtex. I have > > numerous variations on the following: > > > > lut_0: LUT4 generic map (INIT => X"0E6E") > > port map (res(0), val(0), val(1), val(2), val(3)); > > > > This simulated fine using the Alliance libraries compiled for Cadence > > Leapfrog, but when I tried to run it through FPGA Express it barfs on > > my generic map, with the following error: > > > > "Bad formal part - port names in entity and component declarations do > > not match." > > > > I checked the unisim vcomponents file and the component declaration > > seems to be correct. > > > > Any suggestions? -- Ken McElvain, CTO Synplicity Inc. (408)215-6060Article: 31952
Andreas Schmidt wrote: > > Stephane <sjulhes@free.fr> wrote in message news:<3B20982D.5EC2C857@free.fr>... > > Hi, > > > > I'm studying the following architecture : > > > > I have an APEX200E with 1 embbeded NIOS microcontroller which runs his > > program from an external flash. > > The APEX's configuration file beeing contained in his 2 EPC2 > > configuration flash PROM. > > > > My main problem is NIOS and FPGA software update. > > > > I intend to use JTAG. > > > > The FPGA's EPC2 would be programmed by their JTAG pins. > > The flash memory has no JTAG pins. > > So I was wondering if I could program it by driving the FPGA's pins ( > > the address, data and control bus pins ) using the FPGA's JTAG > > capabilities. > > > > Does anyone has already done such a thing ? > > > > Does it works ? > > What is the consequence on the JTAG software on the host PC ? > > > > Thanks in advance. > > > > Stephane. > > Thales Microelectronics. > > Hi Stephane, > > I'm sorry that I can't help you right now but later... > > We at BlueIguana (http://www.blueiguana.com) > working hard to solve this problem to update an whole system > consisting of FPGA, microcontrollers, FLASH, EEPROM, etc. in a secure way... > > The JTAG port on the FPGA can be used to configure the FPGA and access > internal registers (readback). > > The TAP controller in the FPGA can be switched to a transparent mode, > therefore other devices in the JTAG chain can be configured.... > > To program the FLASH you have to implement a TAP controller > together with a statemachine to program the FLASH, > therefore developing a JTAG interface for the FLASH. > > You can implement such an interface in a part of the > FPGA you are already using or using a different part... > > This 'user JTAG port' you daisychain with the JTAG port of the FPGA.... > > Then you can configure/program both.... > > I don't know if there any other solutions available that you can use... > > I hope this clearified it a little... > > cul8r, AS (Andreas) I'd think you could just use the boundary scan already in the fpga "all" you'd need is a program that via jtag can wiggle the fpga pins connected to the flash and thus the pins on the flash in the rigth sequence, I'm not sure how fast you can run the boundry scan so it may be slow though -Lasse -- Lasse Langwadt Christensen, -- PHX,AZArticle: 31953
Hi all, is it possible within the Spartan-II devices to instantiate - Verilog - tristate busses, as it was possible in earlier Xilinx FPGA's. Actually we are near 100% of the largest Spartan-II device, and maybe we could get rid off the readback multiplexer for the internal registers using this appraoch ... Any hints help would be appreciated ... markus -- ******************************************************************** ** Meng Engineering Telefon 056 222 44 10 ** ** Markus Meng Natel 079 230 93 86 ** ** Bruggerstr. 21 Telefax 056 222 44 10 ** ** CH-5400 Baden Email meng.engineering@bluewin.ch ** ******************************************************************** ** Theory may inform, but Practice convinces. -- George Bain **Article: 31954
> I'd think you could just use the boundary scan already in the fpga > > "all" you'd need is a program that via jtag can wiggle the fpga pins > connected to the flash and thus the pins on the flash in the rigth > sequence, I'm not sure how fast you can run the boundry scan so it > may be slow though > > -Lasse > -- Lasse Langwadt Christensen, > -- PHX,AZ The last FLASH Datasheet that I saw said something about 9us programming time per byte. You should be able to match that with JTAG ;-) Kolja SulimmaArticle: 31955
Falk Brunner <Falk.Brunner@gmx.de> wrote: > Hmm, FPGA Express does the job right. Interesting. I was doing something like this with Synplify 6.2.3 the other day. I had coded a single tristate enable for 32 data bits. Synplify replicated the enable 32 times but then the Xilinx tools (Alliance 3.1i SP8) didn't put use the TFFs in the IOBs. :-( It did use the DATA FF1s though (Virtex-II). Synplify puts IOB=TRUE attributes on the data flip flops. I didn't check to see if it put them on the tristate flip flops. I was impressed that Synplify replicated the output enable signal automatically, because in the past we had a lot of trouble with it not preserving those when we coded that fanout manually. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 31956
fred <x@y.z> wrote: > With my toolset you also have top tell the synth tool _and_ the placement > tool to set "use IOB regs = true" or "push regs into IOBs" or whatever > equivalent to make this work. Isn't "-pr b" on MAP supposed to do this? BTW, Synplify always warns me that the option to pack FFs into IOBs hasn't been specified. I could never work out how to specify it though. I see to get IOB=TRUE on the relevant flip flops anyway. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 31957
Hi, I am looking for a FPGA guide or something like that where I can find - an overview of all FPGAs available - comparsion of the different FPGA types (how many gates, how many useable gates, available speed,...) Free internet access is preferred, but not necessary. Sorry if this question was aked before, I am new to this group. Regards, Sven -- Sven Heithecker IDA, Hans-Sommer-Str. 66 Technical University of Braunschweig 38106 Braunschweig Tel. +49-(0)531-391-3751(voice)/4587(fax) Germany http://www.ida.ing.tu-bs.de/~svenh heithecker@ida.ing.tu-bs.deArticle: 31959
In article <3B21B0C7.5506929D@iprimus.com.au>, rjshaw@iprimus.com.au (Russell Shaw) wrote: > Hi, > > I've been using a cypress async. fifo chip, and tried to do the same > thing in maxplus2. However, the lpm functions only have fifos that > require clocks. The fifo chip i was using didn't need *any* clocks. > Will i need to do my own? Yes. Reliable async design is very much the realm of the human expert, not the HDL compiler. Even then, most designers would try and stay synchronous to keep their lives as simple as possible. If you can, redesign your circuit to meet the LPM requirements. -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 31960
What's you definition of a clock? Any asynchronous FIFO obviously needs one signal that "clocks" data in, and another one that "clocks" data out, with the appropriate handshake interfaces. So the only question is: are these clocks free-running and use clock enable for control ( which makes the design easier) or is there just one edge per transfer ( makes the design more tricky). Peter Alfke, Xilinx Applications ================================= Russell Shaw wrote: > Hi, > > I've been using a cypress async. fifo chip, and tried to do the same > thing in maxplus2. However, the lpm functions only have fifos that > require clocks. The fifo chip i was using didn't need *any* clocks. > Will i need to do my own? > > -- > ___ ___ > / /\ / /\ > / /__\ / /\/\ > /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ > \ \ / Victoria, Australia, Down-Under \ \/\/ > \__\/ \__\/Article: 31961
I've used the internal tristates with my Verilog code but I ended up using the BUFE and BUFT primitives to tristate-mux my intenal signals. I don't recall if that was because I had troubles using the `z assignments in multiple equations. The internal tristates are nice in that they don't have serious contention issues: an undriven bus defaults to high, bus contention (high and low drivers) defaults to low. Life is easier without frying chips. If you read in the data sheet, you'll find the tristates are a logical equivalent rather than true tristates. Some tricks I've used with readback multiplexers: * Use the tristate enable concept to generate a select for each register. Use a readout register which either latches in the value to read (enabled) or clears (unselected) and logically OR all the redout registers. Rather than ending up with mux stage after mux stage after mux stage, you end up combinatorially with only a wide or-gate for each bit. If you have more registers available than LUTs, this is a nice way to go. * Use the individual selects to put the readback on a carry chain. With two readback bits in each LUT and no registers used, the design allows for fast, wide readbacks in designs that are short on registers. This is effectively a wide or-gate again, but with the resource usage skewed toward LUTs. Happy coding! Markus Meng wrote: > Hi all, > > is it possible within the Spartan-II devices to instantiate - Verilog - > tristate busses, as it was possible in earlier Xilinx FPGA's. Actually > we are near 100% of the largest Spartan-II device, and maybe we could > get rid off the readback multiplexer for the internal registers using this > appraoch ... > > Any hints help would be appreciated ... > > markus > > -- > ******************************************************************** > ** Meng Engineering Telefon 056 222 44 10 ** > ** Markus Meng Natel 079 230 93 86 ** > ** Bruggerstr. 21 Telefax 056 222 44 10 ** > ** CH-5400 Baden Email meng.engineering@bluewin.ch ** > ******************************************************************** > ** Theory may inform, but Practice convinces. -- George Bain **Article: 31962
On Sat, 9 Jun 2001 18:02:44 +0200, Sven Heithecker <heithecker@ida.ing.tu-bs.de> wrote: >Hi, > >I am looking for a FPGA guide or something like that where I can find >- an overview of all FPGAs available May I suggest www.optimagic.com >- comparsion of the different FPGA types (how many gates, how many useable >gates, available speed,...) Get data sheets from the various vendors. The number of available families of device, and devices within families is very large, and direct comparison can be difficult, as the marketting departments have warped reality too many times. You may also want to look at www.fpga-faq.com FAQ 0014 where the two main FPGA vendors products are discussed. >Free internet access is preferred, but not necessary. All above refs are free. >Sorry if this question was aked before, I am new to this group. Welcome >Regards, Sven Philip Freidin =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 31963
Hello, I search a asynchron SRAM device (datasheet) with a 32 Bit DataI/O. Which company can offer this ? I have a synchron 64k x 32 burst pipelined high-speed CMOS static RAM (WINBOND W25P022A). Can i use this device as a normal SRAM ? Which pins i must use ? Can i switch off the mode 2T/2T, 2T1T ? I would like one of this device connect with a Altera Flex10k( the FPGA is connect with a PCI9052 -PLX- to the PCI-Bus), the SRAM should be write bytewise and read with a 32 Bit access. I use a VHDL-design that this managed, who can help me ? Give it standard- or exampleprograms ? Tipps for a VHDL-Design to connect the PCI9052 (or PCI-Interface general) with the FPGA can i need too ! It's very quickly ! Thanks ! MarioArticle: 31964
OK, so I'm trying to synthesize some VHDL code that simulates fine. Nothing fancy, just some generates to create some registers.
The synthesizer complains: ERROR : (VHP__0163). Where's the list of errors? Hitting F1 is no help. OK, look at the message: "Unexpected symbol read: BEGIN."
Wait, this tool doesn't seem to understand the LRM. My generate statement looks like:
foo: for ff in 0 to 2 generate
begin
bar: process (clk, rst) is
begin
if rst = '1' then
b(ff) <= '0';
elsif rising_edge(clk) then
b(ff) <= c(ff);
end if;
end process bar;
end generate foo;
Hmmm..Ashenden sez this is OK; so does ModelSim. So, what's wrong? Does XST support generates?
Soooo... what's with the online help? Choosing Help->Online Documentation... brings up a web browser (IE only, can't change it) with the following error:
"WebPACK Online Help. Please invoke the online help system from the Help and Technical Support icon in the Xilinx WebPACK program group." That's annoying.
So, Choosing the "Help and Technical Support icon" in my WebPACK program group launches the HTML-based Help system. OK, hmmm..I'm doing a 9500XL design in VHDL, but I have no idea what XST supports and does not support. Where are the synthesis tool details?
Oh, here they are: not under CPLD WebPACK ISE, but rather under FPGA WebPACK ISE->Tools->Synthesis.
But wait -- there's only one simple page here. First line: "XST is a Xilinx tool that synthesizes HDL designs to create EDIF netlists. For detailed information about XST, refer to the XST User Guide." that's rather useless, so I click the "XST User Guide" hyperlink.
That apparently runs the web browser within the help browser, connects to the Xilinx web site's "software Manuals Online" section, where I am NOT brought right to the XST User Guide -- which is what any reasonable person would EXPECT -- but rather, the top level of the Xilinx docs. Which still say 3.1i, but aren't they up to 3.3i SP8 or something?
I click on the Design Entry icon. Wow -- looks like some outdated documentation.
Ah -- waaaay down on the bottom of the "Docscan" frame, there's an XST link. Ah-ha! There it is. And there's VHDL Support, too. Where's Generate?
Hmmm...it's under Combinatorial Circuits. Your guess is as good as mine as to why.
Ah, here's something: I have the keyword BEGIN right after my generate statement (foo : for ff in 0 to 2 generate begin) which is required in VHDL'93 if we include any declarations, but can be omitted if there are none. Emacs seems to put them there, and I like my ENDs balanced by BEGINs.
But the example in the docs does NOT have the BEGIN, and the synth is happy if I remove it from my code. But I'm not happy, since I have to modify my code to satisfy the quirks of a non-compliant tool.
OK, so the tools are FREE. What should I expect?
Well, I expect compliance with the language. Whom does Xilinx think they are, anyway? Synopsys?
I also expect the documentation to be correct, and it and the tool should be OBVIOUS. If a menu item says, "Online help..." it should bring me directly to online help, not to a static HTML page with no links that says, "find something somewhere else."
If a link says, "XST User's Guide," I expect it to take me DIRECTLY to the XST user's guide -- not to the top level of docs for everything.
Xilinx: are you listening?
--andy
Article: 31965Hi All, Sorry for posing here but I have not found anywhere else so your help is appreciated. I would like to know of a newsgroup that maybe able to help me with information regarding a PC design. I need to transfer 32bits of data from my PC to my application hardware and wonder what the best IO standard I should use. Thanks for any help you can provide. DaveArticle: 31966
"Austin Franklin" <austin@dar54kroom.com> writes: > > you're going to find that he or she > > has more expectations of a FIFO than simply the ordering. In particular, > > it is expected that a FIFO can contain a VARIABLE amount of data, from > > zero items up to the FIFO depth. Your two flops with no logic always > > contain a FIXED amount of data. > > No, that isn't true. That's YOUR limited understanding. > > This is REALLY a simple concept. I don't understand why you want to argue > about this, except for the sake of arguing. You really don't know that FIFO > simply means FIRST IN FIRST OUT, and anything that provides that function IS > a FIFO? No matter what the implementation is? Oh, you mean like a piece of wire? Put in an electrical signal in one end, and it will come out in the other, in the same roder. First in, first out. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 31967
Yury <yuryws@yahoo.com> writes: > Just curious, > The Coregen that is a part of Foundation Tools (non-ISE) generates cores based on a revision of unisim and/or simprim libraries that is different from those precompiled into Modelsim XE. Which means that during Modelsim XE compilation one would orinarily get an error indicating that an entity referenced in the configuration block was not found. What was your strategy in getting over the above obstacle? The best strategy would probably be to download the new MXE libraries from Xilinx website. http://www.support.xilinx.com/support/mxelibs/index.htm Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 31968
Kolja Sulimma <kolja@sulimma.de> writes: > > I'd think you could just use the boundary scan already in the fpga > > > > "all" you'd need is a program that via jtag can wiggle the fpga pins > > connected to the flash and thus the pins on the flash in the rigth > > sequence, I'm not sure how fast you can run the boundry scan so it > > may be slow though > > > > -Lasse > > -- Lasse Langwadt Christensen, > > -- PHX,AZ > > The last FLASH Datasheet that I saw said something about 9us programming time per > byte. > You should be able to match that with JTAG ;-) Flashes tend to be programmed in bulk mode, that is for instance 256 bytes at a time. You through 256 bytes to the FLASH as fast as you can, then start programming. Now, 9us, you say. If your JTAG is doing 10 MHz, that's only 90 clocks. Considering that the larger (Xilinx) FPGAs have three boundary scans per I/O, that can be a lot of clocks (say 700). If you are using the internal JTAG chain, you need to go throuhg all of them. Then, if you use byte-wide connection to the Flash, and need to strobe the WR-signal, it takes _at least_ 1400 clocks to write one byte to the Flash. With 10 MHz JTAG, that is about 140 us. Why, oh why, can't Intel make Flash with JTAG? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 31969
Yes. Look at the HDL design guide on the Xilinx Web site. > is it possible within the Spartan-II devices to instantiate - Verilog - > tristate busses, as it was possible in earlier Xilinx FPGA's. Actually > we are near 100% of the largest Spartan-II device, and maybe we could > get rid off the readback multiplexer for the internal registers using this > appraoch ... > > Any hints help would be appreciated ... >Article: 31970
FPGA 2002: Call for Papers
Tenth ACM* International Symposium on Field-Programmable Gate Arrays
Monterey, California
February 24-26, 2002
Submissions due: September 28, 2001
web site: http://www.ecs.umass.edu/ece/fpga2002
The annual ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays is the premier conference for presentation of advances
in all areas related to FPGA technology. For FPGA 2002, we are
soliciting submissions describing novel research and developments
in the following (and related) areas of interest:
* FPGA Architecture: Combined FPGA fabric with system blocks
(memory, processors, etc.), Logic block & routing architectures,
I/O structures and circuits, new commercial architectures,
Field-Programmable Interconnect Chips and Devices (FPIC/FPID),
Field-Programmable Analog Arrays (FPAA).
* CAD for FPGAs: Placement, routing, logic optimization,
technology mapping, system-level partitioning, logic generators,
testing and verification, CAD for FPGA-based accelerators.
Evaluation of sensitivity of tools used for architecture
evaluation (i.e. VPR).
* Applications: Innovative use of FPGAs, exploitation of FPGA
features, novel circuits, high-performance and
low-power/mission-critical applications, DSP techniques,
uses of reconfiguration, FPGA-based cores.
* FPGA-based and FPGA-like computing engines: Compiled
accelerators, reconfigurable computing, adaptive computing
devices, systems and software.
* Rapid-prototyping: Fast prototyping for system-level design,
Multi-Chip Modules (MCMs), logic emulation.
Authors are invited to submit English language PDF of their paper
(12 pages maximum) and panel proposals by September 28, 2001 by
E-mail to fpga2002@xilinx.com. Notification of acceptance will
be sent by November 21, 2001. The authors of accepted papers will
be required to submit the final camera-ready copy by December 5, 2001.
A proceedings of the accepted papers will be published by ACM, and
included in the Annual ACM/SIGDA CD-ROM Compendium publication.
Address questions to:
Steve Trimberger, Program Chair, FPGA 2002
Xilinx Corporation,
2100 Logic Drive,
San Jose, CA 95124
phone: 408-879-5061
fax: 408-559-7168
Email: fpga2002@xilinx.com
General Chair: Martine Schlag, UCSC
Program Chair: Steve Trimberger, Xilinx
Publicity Chair: Russell Tessier, U. Mass.-Amherst
Finance Chair: Scott Hauck, U. of Washington
Panel Chair: Herman Schmit, CMU
Program Committee
Ray Andraka, Andraka Consulting Tom Kean, Algotronix
Mike Bershteyn, Cognigine Arun Kundu, Actel
Vaughn Betz, Altera Miriam Leeser, Northeastern U.
Richard Cliff, Altera Wayne Luk, Imperial College
Jason Cong, UCLA Margaret Marek-Sadowska, UCSB
Andre DeHon, Caltech Martine Schlag, UCSC
Eugene Ding, Agere Systems Herman Schmit, CMU
J.M. "Marty" Emmert, UNC-Charlotte Russ Tessier, U. Mass.-Amherst
Scott Hauck, U. Washington Steve Trimberger, Xilinx
Rajeev Jayaraman, Xilinx Steve Wilton, U. British Columbia
Sinan Kaptanoglu, Adaptive Silicon Martin Wong, U. Texas
Sponsored by ACM SIGDA, with support from industry.*
Please visit the web site <http://www.ecs.umass.edu/ece/fpga2002> for more information.
*Pending approval
--
Article: 31971Magnus Homann wrote: > Yury <yuryws@yahoo.com> writes: > > > Just curious, > > The Coregen that is a part of Foundation Tools (non-ISE) generates cores based on a revision of unisim and/or simprim libraries that is different from those precompiled into Modelsim XE. Which means that during Modelsim XE compilation one would orinarily get an error indicating that an entity referenced in the configuration block was not found. What was your strategy in getting over the above obstacle? > > The best strategy would probably be to download the new MXE libraries > from Xilinx website. > > http://www.support.xilinx.com/support/mxelibs/index.htm > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se Why not just compile the source files that come with Foundation? That way Coregen & the libs will match up.Article: 31972
Magnus Homann wrote: > Why, oh why, can't Intel make Flash with JTAG? > > Homann > -- > Magnus Homann, M.Sc. CS & E > d0asta@dtek.chalmers.se Or anybody else for that matter. If you had a cheap slow JTAG Flash + an XC95K part you could create an FPGA ``serial'' PROM for an awful lot less than the price of an XC18VXX.Article: 31973
> > No. STD_LOGIC(_VECTOR) states also include 'U', 'X', 'H', 'L', 'W', > > '-', and 'Z'. All combinations using these are not covered in the > > example (they "never" are), hence the need for the "when others" > > clause in "all" case statements. > > > > ---- > > Keith > > > > ========================== > > That is true. In most cases, the when others => null; should be used. > When I ran it through, the synthesis tool I used understood that in > an FPGA or CPLD only '1' and '0' can be reached. Surely use an integer subrange to represent an integer. Then you don't have U, X, and the rest...Article: 31974
Hi,
>From the help system, the AHDL definition for a dual-clock fifo is:
FUNCTION lpm_fifo_dc (data[], rdreq, wrreq, rdclock, wrclock, aclr)
WITH (LPM_WIDTH, LPM_NUMWORDS,...)
RETURNS (q[], rdempty, rdfull, wrempty, wrfull,...);
INPUTS:
data[]: Input port LPM_WIDTH wide.
rdclock: Positive-edge-triggered Clock. Synchronous read of lpm_fifo_dc.
wrclock: Positive-edge-triggered Clock. Synchronous load of lpm_fifo_dc.
I assume only one edge of the clock is needed, rather than a series of
pulses that 'clock' implies?
wrreq: Write request control. The data[] port is written to the
lpm_fifo_dc. Writing is disabled if wrfull = 1.
rdreq: Read request control. The oldest data in the lpm_fifo_dc goes
to the q[] port. Reading is disabled if rdempty = 1.
oh, i just realized this fifo has only one input and one output port.
I guess wrreq and rdreq tell the fifo which end you want to access?
aclr: Asynchronous Clear input. Resets the lpm_fifo_dc to empty.
OUTPUTS:
q[]: Output port LPM_WIDTH wide.
rdempty: If asserted, indicates that the lpm_fifo_dc is empty and
disables the rdreq port. Synchronized with rdclock.
wrfull: If asserted, indicates that the lpm_fifo_dc is full and
disables the wrreq port. Synchronized with wrclock.
wrempty: Indicates that the lpm_fifo_dc is empty. Delayed version of
rdempty that is synchronized with wrclock.
rdfull: If asserted, indicates that the lpm_fifo_dc is full. Delayed
version of wrfull that is synchronized with rdclock.
Peter Alfke wrote:
>
> What's you definition of a clock?
> Any asynchronous FIFO obviously needs one signal that "clocks" data in,
> and another one that "clocks" data out, with the appropriate handshake
> interfaces.
> So the only question is:
> are these clocks free-running and use clock enable for control ( which
> makes the design easier)
> or is there just one edge per transfer ( makes the design more tricky).
>
> Peter Alfke, Xilinx Applications
> =================================
> Russell Shaw wrote:
>
> > Hi,
> >
> > I've been using a cypress async. fifo chip, and tried to do the same
> > thing in maxplus2. However, the lpm functions only have fifos that
> > require clocks. The fifo chip i was using didn't need *any* clocks.
> > Will i need to do my own?
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/__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\ \ / Victoria, Australia, Down-Under \ \/\/
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