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Hi, I am trying to implement a FIFO buffer with two different clocks for read and write. I am going to use Dual port memory core but I do not know how to handle the flags and how to track number of bytes in the buffer. moreover how can I avoid metastability on the flags Regards Jamil KhatibArticle: 31626
--------------9952985909B583C0A231EDA4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You'll find it here : Xilinx made a lot of App. notes about FIFO design. FIFOs Using Virtex-II Block RAM http://www.xilinx.com/xapp/xapp258.pdf FIFOs Using Virtex-II Shift Registers http://www.xilinx.com/xapp/xapp256.pdf High Speed FIFOs In Spartan-II FPGAs http://www.xilinx.com/xapp/xapp175.pdf 170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature v1.5 http://www.xilinx.com/xapp/xapp131.pdf Implementing FIFOs in XC4000 Series RAM http://www.xilinx.com/xapp/xapp053.pdf Synchronous and Asynchronous FIFO Designs http://www.xilinx.com/xapp/xapp051.pdf Megabit FIFO in Two Chips: One LCA Device and One DRAM http://www.xilinx.com/xapp/xapp030.pdf If you want more : http://www.xilinx.com/apps/xapp.htm Hope these help ... Eric. --------------------------------------------------------------------- Jamil Khatib wrote: > Hi, > I am trying to implement a FIFO buffer with two different clocks for > read and write. I am going to use Dual port memory core but I do not > know how to handle the flags and how to track number of bytes in the > buffer. > moreover how can I avoid metastability on the flags > > Regards > Jamil Khatib --------------9952985909B583C0A231EDA4 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <body text="#000000" bgcolor="#FFFFFF" link="#0000FF" vlink="#000080" alink="#FF0000"> You'll find it here : <p>Xilinx made a lot of App. notes about FIFO design. <p>FIFOs Using Virtex-II Block RAM <br><a href="http://www.xilinx.com/xapp/xapp258.pdf"> http://www.xilinx.com/xapp/xapp258.pdf</a> <br>FIFOs Using Virtex-II Shift Registers <br> <A HREF="http://www.xilinx.com/xapp/xapp256.pdf">http://www.xilinx.com/xapp/xapp256.pdf</A> <br>High Speed FIFOs In Spartan-II FPGAs <br> <A HREF="http://www.xilinx.com/xapp/xapp175.pdf">http://www.xilinx.com/xapp/xapp175.pdf</A> <br>170 MHz FIFOs Using the Virtex Block SelectRAM+ Feature v1.5 <br> <A HREF="http://www.xilinx.com/xapp/xapp131.pdf">http://www.xilinx.com/xapp/xapp131.pdf</A> <br>Implementing FIFOs in XC4000 Series RAM <br> <A HREF="http://www.xilinx.com/xapp/xapp053.pdf">http://www.xilinx.com/xapp/xapp053.pdf</A> <br>Synchronous and Asynchronous FIFO Designs <br> <A HREF="http://www.xilinx.com/xapp/xapp051.pdf">http://www.xilinx.com/xapp/xapp051.pdf</A> <br>Megabit FIFO in Two Chips: One LCA Device and One DRAM <br> <a href="http://www.xilinx.com/xapp/xapp030.pdf">http://www.xilinx.com/xapp/xapp030.pdf</a> <p>If you want more : <br><A HREF="http://www.xilinx.com/apps/xapp.htm">http://www.xilinx.com/apps/xapp.htm</A> <p>Hope these help ... <p>Eric. <br>--------------------------------------------------------------------- <br>Jamil Khatib wrote: <blockquote TYPE=CITE>Hi, <br>I am trying to implement a FIFO buffer with two different clocks for <br>read and write. I am going to use Dual port memory core but I do not <br>know how to handle the flags and how to track number of bytes in the <br>buffer. <br>moreover how can I avoid metastability on the flags <p>Regards <br>Jamil Khatib</blockquote> </body> </html> --------------9952985909B583C0A231EDA4--Article: 31627
Hi again, Simple question! My design simulates with modelsim and fits OK with webpack. My question is how do I re-import my design into modelsim to check it still works? Cheers DaveArticle: 31628
> > FLAME ON... > > > > Why is > > the global reset signal NOT hard routed using a LOW SKEW net? > > > > FLAME turned down...but still burning with a trigger finger.... > > > Maybe this will be fixed with the Linux s/w release ? Damn. Is Linux the answer to everything, even "bad" hardware design and implementation ;-)Article: 31629
Austin Franklin wrote: > > > FLAME ON... > > > > > > Why is > > > the global reset signal NOT hard routed using a LOW SKEW net? > > > > > > FLAME turned down...but still burning with a trigger finger.... > > > > > Maybe this will be fixed with the Linux s/w release ? > > Damn. Is Linux the answer to everything, even "bad" hardware design and > implementation ;-) Austin, Remember that Xilinx's attitude to Linux is basically ``There's no call for it''. ``Its a sort of a joke you see, never was very good at them'' - Slarty Bardfast, planet designer, in HGTTG.Article: 31630
Speedy Zero Two wrote: > Hi again, > > Simple question! > > My design simulates with modelsim and fits OK with webpack. > > My question is how do I re-import my design into modelsim to check it still > works? > > Cheers > Dave Assuming you mean how do you generate a Verilog/VHDL file that represents the fitted/routed design ? If so then check out the docs on the 2 utilities NGDANNO & NGD2VER/NGD2VHD. The first one generated a timing annotated .nga file & the second takes the .nga & produces both a Verilog simulation model and an SDF timing file. This applies to FPGAs, for CPLDs its slightly different since the TSIM utility is used to produce the .nga.Article: 31631
Since there are still V40 and V50 devices available, albeit with some difficulty, but at a small fraction of the cost of a major FPGA, it might be well to examine one of those processors for use of its built-in 8080 core. You can, if you like, use the 8086-compatible instruction set to execute what will probably have to be an original BIOS, yet use the internal 8080 to execute the CP/M code. Of course it's not Z-80 compatible, but who cares? Dick On Tue, 29 May 2001 13:06:57 GMT, "Mark Walter" <maw@nospam.com> wrote: >It appears that the tools for the SFL language support conversion to Verilog >or VHDL. Is it possible someone can convert this 8080 processor core into >Verilog or VHDL. Then it could be used with the Xilinx tools for creating a >8080 clone... > >Mark > >Article: 31632
> Hi again, > > Simple question! > > My design simulates with modelsim and fits OK with webpack. > > My question is how do I re-import my design into modelsim to check it still > works? > > Cheers > Dave Why would you want to do that? There should be no need for timed stand-alone simulations provided you used TIMESPECs, and your TIMESPECs are accurate.Article: 31633
Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.parmita.com/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Chip-Guru : http://www.chip-guru.com/ )Article: 31634
What is the vol / issue number of the issue that you mention here? Thanks, Dave Feustel "Roberto R. Osorio" <osorior@imec.be> wrote in message news:3B16319A.C50A2AEB@imec.be... > Thanks Tim and Kolja for the answers. > Yesterday I found that last issue of J. of VLSI Signal > Processing is dedicated to reconfigurable computing. > I will spend some time reading those interesting articles. > > Regards. > > > > > Tim wrote: > > > Look at SRC computers, the latest in the Cray lineage. > > > > A problem may be that they are pretty secretive over results. > > > > Also, check the archives for thsi group. > > > > Roberto R. Osorio wrote in message <3B14EAD0.1CBDF5E8@imec.be>... > > >This is just a question. > > > > > >Is anybody using FPGAs to execute scientific programs? > > >Is it possible to find small cores in the programs that can > > >be mapped onto a FPGA and obtain good speed-up? > > >Which is the main problem, computing or IO bandwidth? > > > > > >If you are doing that, which are the results? Which kind > > >of programs are you focused in: optimization, genetics, > > >matrix computation, simulation, weather forecast...? > > > >Article: 31635
Take a look at ATMEL, I think they are providing replacement alternatives (unfortunately same price or even a little bit more expensive). HTH, Carlhermann Schlehaus "Wade D. Peterson" <wadep@silicore.net> schrieb im Newsbeitrag news:QTxR6.499$oF3.81901@news7.onvoy.net... > Does anybody know of a second source for the Altera EPC1 or EPC2 configuration > PROMs? The company that makes my device programmer (Needhams) stopped > supporting Altera, and I need to program some serial PROMs. > > Thanks, > > -- > Wade D. Peterson > Silicore Corporation > >Article: 31636
Richard Erlacher wrote: > > On Tue, 29 May 2001 13:06:57 GMT, "Mark Walter" <maw@nospam.com> > wrote: > > >It appears that the tools for the SFL language support conversion to Verilog > >or VHDL. Is it possible someone can convert this 8080 processor core into > >Verilog or VHDL. Then it could be used with the Xilinx tools for creating a > >8080 clone... > > Since there are still V40 and V50 devices available, albeit with some > difficulty, but at a small fraction of the cost of a major FPGA, it > might be well to examine one of those processors for use of its > built-in 8080 core. You can, if you like, use the 8086-compatible > instruction set to execute what will probably have to be an original > BIOS, yet use the internal 8080 to execute the CP/M code. Of course > it's not Z-80 compatible, but who cares? That only makes sense if you want the 8086 instruction set also. Otherwise why not just use a Z180? All Z80's execute the 8080 instruction set, with the exception being some parity bit settings, and nobody in their right mind ever wrote code that ran into that after the first z80's came out. -- Chuck F (cbfalconer@my-deja.com) (cbfalconer@XXXXworldnet.att.net) http://www.qwikpages.com/backstreets/cbfalconer :=(down for now) (Remove "NOSPAM." from reply address. my-deja works unmodified) mailto:uce@ftc.gov (for spambots to harvest)Article: 31637
Hi,
I would recommend implementing a two stage FIFO. A shallow (e.g. eight
to sixteen words) asynchronous FIFO connected directly to a deeper
synchronous one. The deeper one would be dual-port RAM based, the
shallow one would be implemented as an array of flip-flops. We have an
example of the latter (the FIFODDGF) on our web-page
http://www.eda-services.de/SiSoCKit/index.html. =
Basically, the asynchronous FIFO has two extra flip-flops per fifo word,
one connected to each clock domain. If the flip-flops have a different
value the word contains unread data, if they are the same it is empty
(has been read). The read and write logic each only has to look at the
(synchronised) XORed/XNORed flag flip-flops from the current and next
two cells to determine whether full/last-in or empty/last-out. In other
words, even though signals from the other clock-domain are read, FIFO
behaviour will generally lead to the signals of interest not switching
during the observation window. =
Of course even this solution does not give you zero meta-stability but
IMHO it is significantly reduced. You do avoid having to compute the
distance between synchronised versions of the read and write pointers to
determine whether your FIFO is full or empty.
Another possible solution is to gray-code your pointers. To compute the
distance between the pointers you will need to convert to binary. An
example of a function for gray-to-binary is in the Synthesis Utilities
Package on our above mentioned site.
Hope this helps.
Best regards,
Mit freundlichen Gr=FC=DFen,
Charles Gardiner
-------------------------------------------------------------
Charles Gardiner, B.E.
Program Manager, Silicon IP
Siemens AG
Dept: I&S IT PS 8 Mch
Otto-Hahn-Ring 6
D-81730 Muenchen
Email: mailto:charles.gardiner@mchr2.siemens.de
Phone: Office +49 89/636 42969, Mobile (0)171/867 2732
Fax : Office +49 89/636 44595
Homepage : http://eda-services.atd.siemens.de/gardiner
(Siemens Intranet only)
I&S Homepage: http://www.atd.siemens.de/it-dl/eda
Siemens I&S - Munich's ARM approved Design Centre
Article: 31638"Austin Franklin" <austin@dar54kroom.com> wrote in message news:9f5mq8$bnc$1@slb0.atl.mindspring.net... > > to develop a W2K driver > > for the Spartan II PCI core. > > Why would you need a driver for the PCI core? > > Because I don't have one. Actually I need a driver to drive everything that's behind the PCI core. But before I can drive that I first have to access the PCI core itself and I don't have code for that. ClemensArticle: 31639
A very good question that I asking myself... Sorry, no response. "Meelis Kuris" <matiku@hot.ee> a écrit dans le message news: 3b0e6f9f$1@news.estpak.ee... > Hi, > > In Virtex-II, DCM has outputs clk180, clk2x180 and clkfx180. > Why should anybody need them if it's possible just to use falling > edge of clock? The same applies to clk270, I can > just use falling edge of clk90 instead of it. And this way only 1 clock > buffer is needed. > > Just curious, > > Meelis > >Article: 31640
Austin Franklin wrote: > > > Hi again, > > > > Simple question! > > > > My design simulates with modelsim and fits OK with webpack. > > > > My question is how do I re-import my design into modelsim to check it > still > > works? > > > > Cheers > > Dave > > Why would you want to do that? > > There should be no need for timed stand-alone simulations provided you used > TIMESPECs, and your TIMESPECs are accurate. ... and the tools don't have bugs. ... and the speed files accurately reflect the operation of the silicon. Bitten by both on my last project. Ouch. In the speed file case, a gate level simulation won't help, as the back annotated VHDL (or Verilog, etc.) will have the values from the speed files, not the values from the silicon. The only way to catch these is to try them in the lab, over temperature and voltage variations. The gate level simulation was useful for picking up some of the tool bugs. Others bugs were more amenable to inspections using FPGA Editor, or netlist browsing. Regards, Allan.Article: 31641
In article <3B16B040.9FD2C3F5@sinectis.com.ar>, gonzaloa@sinectis.com.ar
says...
> Hi,
>
> It's me again.
> How may I use the same clock signal in two components? (with Xilinx
> WebPack)
> If I define it (the clock signal) as a port of a component, I get the
> warning: "Gated clock is not a good design practice....".
> Thanks,
>
> Gonzalo Arana
>
Normally you have a top level entity, where the clock is on a
input port. Assume it's called CLKIN.
Then you feed this signal CLKIN to components where
the clock is a input port too.
sub1 : comp2
port map {
clk => CLKIN,
....
};
This will give you no error message.
If you are making some combinatorial manipulation of your
clock like
CLK2 <= CLKIN and Sig2;
and feed this to the subcomponents then you have indeed
a gated clock which may be not desirable.
Hope this helps.
--
Falser Klaus
R&D Electronics Department
Company : Durst Phototechnik AG
Vittorio Veneto Str. 59
I-39042 Brixen
Voice : +0472/810235
: +0472/810111
FAX : +0472/830980
Email : kfalser@IHATESPAMdurst.it
Article: 31642Hi, Actually, I have never heard of a Xilinx 6200 family! Do you mean the 5200 family? Otherwise please tell me what the 6200 family is. If you want to examine how the Place&Route tool have mapped the logic into the CLBs, then you could use the Xilinx tool FPGA Editor. In this tool you can examine each CLB in detail, the equations for the look-up tables, routing between CLBs, etc. The input file for this tool is the <design_name>.ncd Regards /Thomas "Kuan Zhou" <zhouk@rpi.edu> wrote in message news:Pine.SOL.3.96.1010530182531.15124A-100000@rcs-sun2.rcs.rpi.edu... > Hi, > I am a guy who is looking at the performance of > the Xilinx 6200 chips. > When I download the compiled bit streams into > Xilinx 6200 chip,Is there any tool or file for me to > easily tell how the circirts are mapped in the > Xilinx 6200 chip?I want to know the functions > of each CLB in the chip during the application. > Is there any data sheet describing that? > > > sincerely > ------------- > Kuan Zhou > > >Article: 31643
Well, after searching the web for I while I found out that the XC6200 family is designed escpecially for partial reconfiguration while running in a system. Why isn't there any information about it on the Xilinx website? Is the device obsolete? /Thomas "Thomas Karlsson" <thomas.karlsson@sys.sigma.se> wrote in message news:3b1748e9.0@d2o947.telia.com... > Hi, > > Actually, I have never heard of a Xilinx 6200 family! Do you mean the 5200 > family? > Otherwise please tell me what the 6200 family is. > > If you want to examine how the Place&Route tool have mapped the logic into > the CLBs, > then you could use the Xilinx tool FPGA Editor. In this tool you can examine > each CLB in detail, > the equations for the look-up tables, routing between CLBs, etc. > The input file for this tool is the <design_name>.ncd > > Regards > /Thomas > > "Kuan Zhou" <zhouk@rpi.edu> wrote in message > news:Pine.SOL.3.96.1010530182531.15124A-100000@rcs-sun2.rcs.rpi.edu... > > Hi, > > I am a guy who is looking at the performance of > > the Xilinx 6200 chips. > > When I download the compiled bit streams into > > Xilinx 6200 chip,Is there any tool or file for me to > > easily tell how the circirts are mapped in the > > Xilinx 6200 chip?I want to know the functions > > of each CLB in the chip during the application. > > Is there any data sheet describing that? > > > > > > sincerely > > ------------- > > Kuan Zhou > > > > > > > >Article: 31644
Thomas Karlsson schrieb: > > Why isn't there any information about it on the Xilinx website? > Is the device obsolete? Hi Thomas, academic users didnt order high volumes (bad news) and real (industrial) designers didnt love 6200 (very bad news). xilinx like high volumes, so 6200 is dead now. simple. very simple. michael strothjohannArticle: 31645
What about running an 8080 S/W simulator on an ARM core? With the AT91R40807, you have 136 kB of internal SRAM and can run the simulator AND the application on chip at pretty high speed! -- Best regards, ulf at atmel dot com The contents of this message is intended to be my private opinion and may or may not be shared by my employer Atmel Sweden "Richard Erlacher" <edick@hotmail.com> skrev i meddelandet news:3b16f0c0.5485681@mindmeld.idcomm.com... > Since there are still V40 and V50 devices available, albeit with some > difficulty, but at a small fraction of the cost of a major FPGA, it > might be well to examine one of those processors for use of its > built-in 8080 core. You can, if you like, use the 8086-compatible > instruction set to execute what will probably have to be an original > BIOS, yet use the internal 8080 to execute the CP/M code. Of course > it's not Z-80 compatible, but who cares? > > Dick > > > On Tue, 29 May 2001 13:06:57 GMT, "Mark Walter" <maw@nospam.com> > wrote: > > >It appears that the tools for the SFL language support conversion to Verilog > >or VHDL. Is it possible someone can convert this 8080 processor core into > >Verilog or VHDL. Then it could be used with the Xilinx tools for creating a > >8080 clone... > > > >Mark > > > > >Article: 31646
Hello Gurus,
I am an ASIC Designer with 3+ years of experience and am
about to make a next move. Here is where I need your suggestions. I
have 2 (atleast) competetive offers which differ in the work nature.
Option 1.> Has SoC design + verification (major part) for Ethernet
related communications chip.
Option 2.> Is in developing RTL (+synthesis, simulation etc.) USB 2.0
is something they said they are developing. Also some maintanance of
previous peripherals (USB) is going on. They are also developing
interface blocks to act as interface from their properitory bus
standards to AMBA bus. The design work would be roughly 30% they say.
I am OK with VHDL & Verilog.
Given the above situation I am slightly confused about which one to
take.
I would be thankful if you could share your views on this.
Regards,
ASIC Engineer
P.S. Sorry for this non-technical post, didn't know where else to ask
for.
Article: 31647Hi ASIC engineer ! You can try to post your message at Electronic Times: http://www.eetimes.com There is so called the mentoring board, where I've seen many similar posts. Regars, MartinArticle: 31648
Hello it's seem to be very interesting for me can you send me or give the adresse please ? "Nicolas Matringe" <nicolas.matringe@IPricot.com> a écrit dans le message news: 3B163E47.C7382361@IPricot.com... > Frederic Darre wrote: > > > > Thanks you for all you do. > > Fred > > > > "Kent Orthner" <korthner@hotmail.nospam.com> a écrit dans le message news: > [...] > > > > It sounds to me like you need to take a look at a VHDL book > > > or a tutorial. I'm afraid that I don't know where you would > > > find one in french. > > > Je suis desolee! > > I've got a nice .pdf file from the EPFL called "Modelisation > de Systemes Numeriques Integres - Introduction à VHDL" > It's a bit big (1.7M) though > > -- > Nicolas MATRINGE IPricot European Headquarters > Conception electronique 10-12 Avenue de Verdun > Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE > Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 31649
Anthony,
Unfortunately, Motorola and IBM apparently have decided to hand off the
modeling to Synopsis, which is going to cost you BIG bucks!
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
"Anthony Ellis" <xxxa.ellis@logicworks.co.za> wrote in message
news:3b15e140.0@news1.mweb.co.za...
> Anyone know where I can get a VHDL bus interface model (functional only)
> for a PowerPC 603E. I need such for use in a test bench.
> Thanks Anthony
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