Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
SAF wrote:
> What I want to know is:
>
> Given that the idea in my head now is to do with network switching as
> a an aim. What Xilinx chip family should I go for? My project might
> end up on a PCI card or as a stand alone solution. Should I go for
> Virtex or Spartan?
>
> Remember I am starting out, so I need to be able to start small on
> whatever it is. Should I just start out with the XC4k as on the XESS
> boards? I want to lear as uch as possible in the next 2 months.
>
> Or should I actually o for CPLDs perhaps Coolrunner specifically,
> since switching is speed critical?
Coolrunner is probably a little small for any significant
network switching function.
I would suggest that you defer picking a device or buying
a board until you have working RTL code and a simulation
testbench. The Modelsim version on WebPack is probably
adequate for this purpose.
Start with a more specific goal than "network switching".
For example, maybe start with just receiving, delineating
and validating an ethernet frame or ATM cell
out of a bitstream.
--Mike Treseler
Article: 33001What's the voltage (VCC) you're supplying to the cable ? Thanks "Russell Shaw" <rjshaw@iprimus.com.au> wrote in message news:3B5000C5.E2F99692@iprimus.com.au... > I just made a byteblasterMV for the acex 1k, and it works:) > > The resistors are 100ohms and 2.2k. > > The schematic doesn't show any VCC-GND capacitor across the 74HC244, > but i put a 100nF in there anyway. > > I assume the max3000 is jtag. Try connecting 1k pull-up resistors > just in case... > > Rodo wrote: > > > > Hi all... > > > > A friend and I are building this cable to experiment with the MAX3000 series > > chips. The datasheet for the cable shows several 100 ohms resistors in > > series and 2.2 ohms resistors as pull ups. These 2.2 ohms resistors are very > > low to be a pull ups so we called altera to make sure. The tech guy said the > > value was right. Not convinced my friend went to ask a professor who > > happened to have the evaluation board from altera. After looking at the > > schematic for the board the resistors are 2.2K ohms. So, we build the cable > > with the 2.2k values. > > > > The Max+Plus II software detected the cable but it cannot find any device > > attached. We have a EPM3032ALC44-10 connected and setup as the target > > device. We did supply a 3.3v to all 4 VCC pins in the device and the cable. > > We're gonna go back to ask the professor on Monday if we can take his cable > > apart and make sure the resistor values are right :-). Does anyone know the > > values for the resistors ? Is it 2.2 K or ohms ? > > > > BTW if we disconnect the cable and check if the device is blank we get a > > cable not found error. With the cable connected it says no device or socket > > empty. > > > > Any help/comments are welcome. > > -- > ___ ___ > / /\ / /\ > / /__\ / /\/\ > /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ > \ \ / Victoria, Australia, Down-Under \ \/\/ > \__\/ \__\/Article: 33002
Thanks, but... The reason for my question wasn't really to try and determine the architecture for my final project design, but more, which is likely to allow me to get closer to it. I need to buy a development/test board, as I want to get some experience on the physical front with RJ45 port interfacing and thus. So, is there a reason to go for one family over another? What I mean is which family, will allow me the most room for expansion in that direction? Should I just get one of the cheap XS40 boards (www.xess.com), or should I get a Spartan II or Virtex board? And if so, which come recommended? I am starting out, hence I will probably start with very simple designs, before moving onto the more serious stuff. Thanks for any help. Suhaib. Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3B509ABC.5A8FB5B@flukenetworks.com>... > SAF wrote: > > > What I want to know is: > > > > Given that the idea in my head now is to do with network switching as > > a an aim. What Xilinx chip family should I go for? My project might > > end up on a PCI card or as a stand alone solution. Should I go for > > Virtex or Spartan? > > > > Remember I am starting out, so I need to be able to start small on > > whatever it is. Should I just start out with the XC4k as on the XESS > > boards? I want to lear as uch as possible in the next 2 months. > > > > Or should I actually o for CPLDs perhaps Coolrunner specifically, > > since switching is speed critical? > > Coolrunner is probably a little small for any significant > network switching function. > > I would suggest that you defer picking a device or buying > a board until you have working RTL code and a simulation > testbench. The Modelsim version on WebPack is probably > adequate for this purpose. > > Start with a more specific goal than "network switching". > For example, maybe start with just receiving, delineating > and validating an ethernet frame or ATM cell > out of a bitstream. > > > --Mike TreselerArticle: 33003
I'm starting out, and was wondering whether I should spend money and get the Xilinx Foundation Student Edition, or just use WebPack. I understand the WebPack doesn't include schematic capture. But I do like the general heirarchy to be in schematic with implementation in HDL. Is it wirth though, going for Foundation, given that I can only get version 2.1? Thanks. Suhaib.Article: 33004
3.3V from the circuit being programmed. Rodo wrote: > > What's the voltage (VCC) you're supplying to the cable ? > > Thanks > > "Russell Shaw" <rjshaw@iprimus.com.au> wrote in message > news:3B5000C5.E2F99692@iprimus.com.au... > > I just made a byteblasterMV for the acex 1k, and it works:) > > > > The resistors are 100ohms and 2.2k. > > > > The schematic doesn't show any VCC-GND capacitor across the 74HC244, > > but i put a 100nF in there anyway. > > > > I assume the max3000 is jtag. Try connecting 1k pull-up resistors > > just in case... > > > > Rodo wrote: > > > > > > Hi all... > > > > > > A friend and I are building this cable to experiment with the MAX3000 > series > > > chips. The datasheet for the cable shows several 100 ohms resistors in > > > series and 2.2 ohms resistors as pull ups. These 2.2 ohms resistors are > very > > > low to be a pull ups so we called altera to make sure. The tech guy said > the > > > value was right. Not convinced my friend went to ask a professor who > > > happened to have the evaluation board from altera. After looking at the > > > schematic for the board the resistors are 2.2K ohms. So, we build the > cable > > > with the 2.2k values. > > > > > > The Max+Plus II software detected the cable but it cannot find any > device > > > attached. We have a EPM3032ALC44-10 connected and setup as the target > > > device. We did supply a 3.3v to all 4 VCC pins in the device and the > cable. > > > We're gonna go back to ask the professor on Monday if we can take his > cable > > > apart and make sure the resistor values are right :-). Does anyone know > the > > > values for the resistors ? Is it 2.2 K or ohms ? > > > > > > BTW if we disconnect the cable and check if the device is blank we get a > > > cable not found error. With the cable connected it says no device or > socket > > > empty. > > > > > > Any help/comments are welcome. > > -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33005
Suhaib, You may wish to consider the low cost SpartanII board from Burch Electronic Designs: http://www.burched.com.au/bedspartan2.html It has a 200K gate SpartanII device, configuration download pod and cable, a header programmable PLL oscillator (1-100MHz), and it works with the free Xilinx WebPACK design software. All for less than US$120 ! Best regards Tony Burch http://www.BurchED.com.au Lowest cost, easy-to-use FPGA prototyping kits! "SAF" <safahmy@hotmail.com> wrote in message news:66c23f42.0107141338.4e2c49c7@posting.google.com... > Thanks, but... > > The reason for my question wasn't really to try and determine the > architecture for my final project design, but more, which is likely to > allow me to get closer to it. I need to buy a development/test board, > as I want to get some experience on the physical front with RJ45 port > interfacing and thus. > > So, is there a reason to go for one family over another? What I mean > is which family, will allow me the most room for expansion in that > direction? Should I just get one of the cheap XS40 boards > (www.xess.com), or should I get a Spartan II or Virtex board? And if > so, which come recommended? > > I am starting out, hence I will probably start with very simple > designs, before moving onto the more serious stuff. > > Thanks for any help. > > Suhaib. > > > Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3B509ABC.5A8FB5B@flukenetworks.com>... > > SAF wrote: > > > > > What I want to know is: > > > > > > Given that the idea in my head now is to do with network switching as > > > a an aim. What Xilinx chip family should I go for? My project might > > > end up on a PCI card or as a stand alone solution. Should I go for > > > Virtex or Spartan? > > > > > > Remember I am starting out, so I need to be able to start small on > > > whatever it is. Should I just start out with the XC4k as on the XESS > > > boards? I want to lear as uch as possible in the next 2 months. > > > > > > Or should I actually o for CPLDs perhaps Coolrunner specifically, > > > since switching is speed critical? > > > > Coolrunner is probably a little small for any significant > > network switching function. > > > > I would suggest that you defer picking a device or buying > > a board until you have working RTL code and a simulation > > testbench. The Modelsim version on WebPack is probably > > adequate for this purpose. > > > > Start with a more specific goal than "network switching". > > For example, maybe start with just receiving, delineating > > and validating an ethernet frame or ATM cell > > out of a bitstream. > > > > > > --Mike TreselerArticle: 33006
Free MaxPlus2 has free schematic entry, AHDL, and VHDL. SAF wrote: > > I'm starting out, and was wondering whether I should spend money and > get the Xilinx Foundation Student Edition, or just use WebPack. I > understand the WebPack doesn't include schematic capture. But I do > like the general heirarchy to be in schematic with implementation in > HDL. Is it wirth though, going for Foundation, given that I can only > get version 2.1? > > Thanks. > > Suhaib.Article: 33007
On Sat, 14 Jul 2001 10:23:47 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: >Have you set the ``override write protect'' tick box when trying to erase the >device Yes but it seems to erase OK.. it's just that I can't seem to get the device to accept a file in program mode. >Article: 33008
Hi, "Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag news:3B50EBD5.48D24C6E@iprimus.com.au... > 3.3V from the circuit being programmed. > Well, this could be a problem, as there is a 74HCT244(?) Driver for the programming signals installed on the Byteblaster, which (AFAIK) needs 5V supply. Detection of the cable itself is done by simply monitoring the bridge between Pin7 and Pin10. Try to supply Your's Byteblaster with 5V. HTH, Carlhermann SchlehausArticle: 33009
"C.Schlehaus" wrote: > > Hi, > > "Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag > news:3B50EBD5.48D24C6E@iprimus.com.au... > > 3.3V from the circuit being programmed. > > > > Well, this could be a problem, as there is a 74HCT244(?) Driver for the > programming signals installed on the Byteblaster, which (AFAIK) needs > 5V supply. > Detection of the cable itself is done by simply monitoring the bridge > between Pin7 and Pin10. > > Try to supply Your's Byteblaster with 5V. > > HTH, Carlhermann Schlehaus The new byteblaster MV is probably different to the old byteblaster. The new one has a straight 74HC244 which can run from 2->6V. -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33010
I've seen your plug many times before! While it seems quite good, I don't like the fact that it's all on ribbon cables. Specifically, I worry that the download cable bit will break. Does it include JTAG connections? To everyone else: What is the difference between Spartan-II and Virtex-II, what different markets are they targeted at, and what are the different features? Why chose one over another? Thanks. "Tony Burch" <tony@BurchED.com.au> wrote in message news:<3b50f1d9@news1.idx.com.au>... > Suhaib, > > You may wish to consider the low cost > SpartanII board from Burch Electronic Designs: > http://www.burched.com.au/bedspartan2.html > > It has a 200K gate SpartanII device, configuration > download pod and cable, a header programmable > PLL oscillator (1-100MHz), and it works with > the free Xilinx WebPACK design software. > All for less than US$120 ! > > Best regards > Tony Burch > http://www.BurchED.com.au > Lowest cost, easy-to-use > FPGA prototyping kits!Article: 33011
I'm still trying to get this chip to erase. Every time I try to erase it, I get the following error message in the log file: (null):Release 3.3WP8.x - JTAG Boundary-Scan Download D Copyright:(null) JTAG Programmer Started 2001/07/15 21:49:39 ERROR:JTag - No instance of the name 'accelerometercounter(Device1)' was found in the instance database. Make certain that the complete boundary-scan chain was specified and that you are using the correct JEDEC, .BIT and BSDL files. ERROR:JTag - No instance of the name 'accelerometercounter(Device1)' was found in the instance database. Make certain that the complete boundary-scan chain was specified and that you are using the correct JEDEC, .BIT and BSDL files. ERROR:JTag - The boundary-scan based 'erase' operation is not supported by the download software on the instance 'accelerometercounter(Device1)'. These operations are currently supported only on Xilinx CPLD devices. 'accelerometercounter(Device1)': Erasure terminated due to errors. Can anyone tell me the precise meaning of what "No instance of the name 'accelerometercounter(Device1)' was found in the instance database" ? I've loaded the correct jedec file.Article: 33012
T.Dattuprasad schrieb: > > Dear friends, > I am beginner in using the FPGA tools. I have designed a small FIFO based design. When I Synthesise the Design using the Foundation Express 2.1i, I am getting the following error : "Global Set/Reset (GSR)net could be used in the design because there is not a unique net that sets or resets all the sequential cells. (FPGA-GSRMP-5)" > > I ahve used a common Rst pin for all the sequential elements also I am getting the same error. When Synthesize the same design in Virtex Hmm, sounds like there are some FFs missing the reset signal, otherwise the warnig would not appear. > devices the oproblem is not coming where in if i synthesize it in Spartan devices the problem is coming. This is no serious problem, in general you can ignore this. -- MFG FalkArticle: 33013
SAF schrieb: > > What I want to know is: > > Given that the idea in my head now is to do with network switching as > a an aim. What Xilinx chip family should I go for? My project might > end up on a PCI card or as a stand alone solution. Should I go for > Virtex or Spartan? Forget about Spartan and Virtex and especially about 4K. The devices for todays designs are Virtex-E, Spartan-II and Virtex-II. > > Remember I am starting out, so I need to be able to start small on > whatever it is. Should I just start out with the XC4k as on the XESS > boards? I want to lear as uch as possible in the next 2 months. Go for a Spartan-II or Virtex-E board, the later is AFAIK available as a PCI card. Saves a lot of trouble. > Or should I actually o for CPLDs perhaps Coolrunner specifically, > since switching is speed critical? No, today FPGAs are mostly faster than CPLDs (if its not pure pin2pin delay) > What download cable/development board should I use? A simple JTAG/Serial will do, a PCI card based prototype board will be very fine, but also a simple workbench demoboard will do. -- MFG FalkArticle: 33014
SAF schrieb: > > I've seen your plug many times before! While it seems quite good, I > don't like the fact that it's all on ribbon cables. Specifically, I > worry that the download cable bit will break. Does it include JTAG > connections? I dont think so. If you REALLY break the cable, you can build your own very easy (the schematics can be found on the Xilinx website) > What is the difference between Spartan-II and Virtex-II, what Spartan-II is the low cost version of Virtex. Its quite nice, powerfull and cheap, up to 5300 logic cells (I dont mention the 200k gates, as this number is useless) Virtex-II is the new flagship of Xilinx, much faster than Spartan-II (420 MHz instead of 200 MHz internal performance) with lots of improvements (digital terminates outputs, much improved clock management functions, dedicated multipliers, bigger block RAMS . . . ). >From the point of power I would say the order is Spartan(XL) Spartan-II Virtex-E Virtex-II I wouldnt use other families for new designs. -- MFG Falk P.S. Im not working for Xilinx marketing ;-)Article: 33015
SAF schrieb: > > I'm starting out, and was wondering whether I should spend money and > get the Xilinx Foundation Student Edition, or just use WebPack. I > understand the WebPack doesn't include schematic capture. But I do > like the general heirarchy to be in schematic with implementation in > HDL. Is it wirth though, going for Foundation, given that I can only > get version 2.1? Foundation 2.1 isnt that bad, but as Webpack is totally free, I would recommend Webpack. -- MFG FalkArticle: 33016
In article <Zl1QO96p8f60ip3LW3BxQrVcS=OD@4ax.com>, John Larkin <jjlarkin@highlandSNIPTHIStechnology.com> wrote: >On Thu, 5 Jul 2001 16:44:13 +0000 (UTC), subodh@best.com (Subodh >Nijsure) wrote: > > > >After you pull PROGRAM high, you need a *long* wait before you can >begin clocking data. The delay depends on the device... check the data >books. Thanks for all the help from everyone on the newsgroup, I am now able to download bitstream correcty. I had received bitstream compipled for Virtex and not Virtex_E, we compiled program with right option now, I guess. Also on my board I have 860P which I am using to download bitstream, and I had configured CPLD chip select for UPM instead of GPCM. Now the DONE pin goes high, and I my FPGA is seems to be doing its job. But what I have observed is, as soon as checksum command words are sent for the last block /INIT pin goes low, but if ignore that error, DONE pin is still going high and FPGA seems to be working okay. I haven't tried pulling /INIT high as was suggeseted earlier. Any hints on why /INIT goes low? /Subodh NijsureArticle: 33017
If you're just getting started and doing simpler designs, the Spartan-II (based on the original Virtex architecture rather than Virtex-E or Virtex-II) gives you excellent functionality and good speeds IF you can learn to design with the target architecture in mind. The Virtex devices have faster speed grades and higher densities available and the Virtex-II devices have increased functionality but it doesn't sound like this is the learning vehicle you need. If you end up with complex logic, often the CPLDs can't handle the sheer size of the designs so the speed doesn't gain you much. You can hit some darned nice system speeds with any of the Virtex family or Spartan-II devices even in the slowest speed grades. Spartan-IIs are a lower-cost alternative to the Virtex family that Xilinx came out with to win over the cost sensitive ASIC replacement market. The Virtex family is the flagship line of devices (without the sacrifices in profit margin) that address the high speed, high densitiy designs used in high end or low volume applications where cost sensitivity is less of an issue than functionality. If you need to deal with LVDS signals, Virtex-E and Virtex-II give you native functionality while the Virtex and Spartan-II receive fine but require resistor networks on the outputs to give you the correct LVDS levels; switching speeds aren't quite world-class LVDS speeds in those non-native devices. So... density, cost, speed. It's all a tradeoff. I've been happy with the Spartan-II devices for much of my own high volume, low cost, (reasonably) high speed complex design work. Good fortune in your pursuits, - John SAF wrote: > What is the difference between Spartan-II and Virtex-II, what > different markets are they targeted at, and what are the different > features? Why chose one over another?Article: 33018
Say, can we still buy TTL? DTL? RTL? Ben Franchuk wrote: > One advantage schematics may be ( with a good > macro library ) for the large amount of small TTL projects > that are around.Article: 33019
In my quick internet scan, I see the Booth Multiplier as an algorithm which might reduce the number of accumulator cycles but requires a variable shift to skip over unneeded cycles. If I understand the Modified Booth Multiplier as taking bit pairs, each stage of the multiplier requires more resources since there are too many inputs to fit onto one LUT: accumulator feedback, first multipler (unshifted), first multiplier (shifted), 2 bits of select for 0/+1/-1/-2(/+2?). You might attain better speeds with the external mux to get the right value - 0/+1/-1/-2(/+2?) - in with the accumulator in the older Xilinx 4000 series devices or the Altera arithmatic functions, but for the Xilinx Virtex devices, the complete shift/add/subtract accumulation can take place in a single level of LUTs. A booth approach might be more efficient from a cycle perspective, but for resources too? Steve Casselman wrote: > I have to disagree. A booth multiplier is more efficient than a regular > shift and add. In the 4000 I was able to fit a booth multiplier in the same > area as a normal shift and add (which does not use all the inputs in a 4 bit > LUT and the recoding just takes two three-LUTs and an inverter). As you know > one of our demos is the mandelbrot hardware. You can "unroll" the booth > multiplier and pipeline it to save 1/2 the area.Article: 33020
John_H wrote: > > Say, can we still buy TTL? DTL? RTL? > The DTL & RTL chips have gone the way of the Dodo. Real TTL chips can still be found mostly as surplus old stock. The TTL family of devices have moved to high speed cmos. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 33021
Thanks everyone for the advice. Now I just need to decide on a board. There's a few from Avnet (http://www.ads.avnet.com/avenue.html), a few from Insight Memec (http://www.insight-electronics.com/solutions/kits/xilinx/index.shtml), then there's BurchEd (http://www.burched.com.au), and Cleoxica (http://www.celoxica.com/products/boards/index.htm) - never heard of them. I'm probably going to go for an Avnet or Insight board, as they distribute Xilinx stuff anyway, and I trust their stuff's pretty good. Or should I go for a second-hand Virtex E board? (http://members-http-1.rwc1.sfba.home.net/ecoroy/xi/bg432_100.html or http://members-http-1.rwc1.sfba.home.net/ecoroy/xi/pq240_110.html) BTW, this guy's got a few more Xilinx things for sale. Oh, and lastly, how easy would it be to get hold of a single chip? say a Spartan-II 200? I'll be using WebPACK, and Ashenden's book to learn VHDL. Anyone know of a lab book or project outlines online? I again thank everyone for the advice, when I'm up to scratch, I'll try to help out newbies too! Suhaib, John_H <johnhandwork@mail.com> wrote in message news:<3B51E3A5.BD016B67@mail.com>... > If you're just getting started and doing simpler designs, the Spartan-II (based on the > original Virtex architecture rather than Virtex-E or Virtex-II) gives you excellent > functionality and good speeds IF you can learn to design with the target architecture in > mind. The Virtex devices have faster speed grades and higher densities available and the > Virtex-II devices have increased functionality but it doesn't sound like this is the > learning vehicle you need. > > If you end up with complex logic, often the CPLDs can't handle the sheer size of the > designs so the speed doesn't gain you much. You can hit some darned nice system speeds > with any of the Virtex family or Spartan-II devices even in the slowest speed grades. > > Spartan-IIs are a lower-cost alternative to the Virtex family that Xilinx came out with to > win over the cost sensitive ASIC replacement market. The Virtex family is the flagship > line of devices (without the sacrifices in profit margin) that address the high speed, high > densitiy designs used in high end or low volume applications where cost sensitivity is less > of an issue than functionality. > > If you need to deal with LVDS signals, Virtex-E and Virtex-II give you native functionality > while the Virtex and Spartan-II receive fine but require resistor networks on the outputs > to give you the correct LVDS levels; switching speeds aren't quite world-class LVDS speeds > in those non-native devices. > > So... density, cost, speed. It's all a tradeoff. I've been happy with the Spartan-II > devices for much of my own high volume, low cost, (reasonably) high speed complex design > work. > > Good fortune in your pursuits, > - John > > > SAF wrote: > > > What is the difference between Spartan-II and Virtex-II, what > > different markets are they targeted at, and what are the different > > features? Why chose one over another?Article: 33022
I forgot, I would be very interested about what exactly you mean by the below statement, and how I can get enough information about the target architecture. Is it also mainly a matter of experience or is there some way of learning techniques? Thanks again. Suhaib. John_H <johnhandwork@mail.com> wrote in message news:<3B51E3A5.BD016B67@mail.com>... > IF you can learn to design with the target architecture in mind.Article: 33023
Spartan II is the Virtex architecture, in fact the bitstreams of like size devices are the same for the two (ie an XCV50 bitstream will load in an XC2S50 and vise-versa). In that respect, your comment about skipping Virtex but including Spartan II doesn't make sense. For new designs, if you are not in the Spartan II, I would go with the Virtex E right now. The Virtex also lives on as the QPRO (military) device, so if you putting your whizbang design into space, you're stuck with Virtex. Personally, I'd forgo the 4K/Spartan (original) architecture for new designs, as the cost per gate and speeds are better for the later families, and the later families have a longer time horizon until they become obsolete. Falk Brunner wrote: > SAF schrieb: > > > > What I want to know is: > > > > Given that the idea in my head now is to do with network switching as > > a an aim. What Xilinx chip family should I go for? My project might > > end up on a PCI card or as a stand alone solution. Should I go for > > Virtex or Spartan? > > Forget about Spartan and Virtex and especially about 4K. > The devices for todays designs are Virtex-E, Spartan-II and Virtex-II. > > > > > Remember I am starting out, so I need to be able to start small on > > whatever it is. Should I just start out with the XC4k as on the XESS > > boards? I want to lear as uch as possible in the next 2 months. > > Go for a Spartan-II or Virtex-E board, the later is AFAIK available as a > PCI card. > Saves a lot of trouble. > > > Or should I actually o for CPLDs perhaps Coolrunner specifically, > > since switching is speed critical? > > No, today FPGAs are mostly faster than CPLDs (if its not pure pin2pin > delay) > > > What download cable/development board should I use? > > A simple JTAG/Serial will do, a PCI card based prototype board will be > very fine, but also a simple workbench demoboard will do. > > -- > MFG > Falk -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33024
Steve, I think we are talking apples and oranges here. The orignal post on this thread was asking specifically about scaling accumulator multipliers, which do the shift-add on a cycle by cycle basis. The multiplier exists as an accumulator with one input gated (to initialize on first cycle) and the other XOR'ed with the MSB control. The area occupied is the same as an adder of the same width, if you get the tools to make it right. The accumulator feedback is a fixed (wired shift). In order to do a booth mulitplier with this structure, you need to modify the serial input to replace strings of 1's with a shortened 1 and -1 input. That requires dropping bit times and dynamically changing the shift in the accumulator feedback. There is a serial booth multiplier which is a different architecture. That one uses a series of serial adders, as described in my FIR filter paper from 1992 PLDCOn. This one can be run faster than the scaling accumulator because it doesn't use the carry chain, but it also requires about twice the number of LUTs, since the carry chain gives you half the logic for free. On reading your posts, I am pretty sure you are describing a parallel by parallel multiplier, in which case the Booth recoding does reduce the size of the adder tree needed to sum the partial products. Steve Casselman wrote: > I have to disagree. A booth multiplier is more efficient than a regular > shift and add. In the 4000 I was able to fit a booth multiplier in the same > area as a normal shift and add (which does not use all the inputs in a 4 bit > LUT and the recoding just takes two three-LUTs and an inverter). As you know > one of our demos is the mandelbrot hardware. You can "unroll" the booth > multiplier and pipeline it to save 1/2 the area. > > Steve > > "Ray Andraka" <ray@andraka.com> wrote in message > news:3B4E8927.BF2AB802@andraka.com... > > Booth recoding won't help much in this case. A scaling accumulator > > multiplier is a single accumulator with the feedback shifted. It is a > > serial by parallel multiplier, that uses a conventional adder. Booth > > recoding seeks to reduce the number of partial products by recoding > > strings of '1' bits into an equivalent 1, -1 and zeros. The result is > > that you can reduce the number of partial products to be combined in an > > adder tree, which in turn reduces the size of the tree. Since the > > scaling accumulator multiplier is shifting once and adding for N cycles, > > you essentially are doing all the partial products regardless of whether > > or not they are zero. You could conceivably use Booth recoding in this > > case to reduce the number of cycles, but in a practical sense, the added > > complexity to the circuit would outweigh the benefit (one could use two > > scaling accumulator multipliers, or go to a 2 bits/clock version to get > > on average a better speedup for less area and complexity). All he has > > to do is subtract the partial product corresponding to the MSB of the > > serial input and sign extend the parallel input to handle signed > > muliplicands. > > > > Rob Finch wrote: > > > > > Try using Booth recoding. > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z