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Bob Perlman wrote: > OIf Celoxica and similar companies convince managers that their > software people can use a C-like language to design FPGAs, that's > tantamount to declaring a guaranteed employment act for FPGA > consultants; we'll be cleaning up the mess for years. > > Bob Perlman It might help if the company promoting Handel-C didn't sound like an unpleasant disease picked up on holiday.Article: 30451
Worry? No way... I spent about 10 years doing semi-conductor design. Recently, I started to feel more comfortable than ever before since fresh graduates have no idea of what they are doing with HDL. :-) Thanks to synthesis tools, they believe they are doing right job by clicking. If I am a bit cynical, sorry for that. But, that is true. ;-) cyber_spook <pjc@cyberspook.freeserve.co.uk>ÀÌ(°¡) <3AD0DE23.F06C20C7@cyberspook.freeserve.co.uk> ±â»ç¿¡¼ ÀÛ¼ºÇß½À´Ï´Ù... > > At the end of the day if you are good at what you do - why worry - its the > hardware chaps that have been blagging there boss for years that are in > danger!Article: 30452
Have you looked at the "webpack" software suite? It's ostensibly the same basic software as the Foundation suite has, including the schematic editor, allowing interchange of schematic and HDL files. Dick On Sun, 8 Apr 2001 21:02:10 +0100, "[Pedro Silva]" <pedro_silva@oninet.pt> wrote: > > Is there an alternative to Xilink Foundation schematic editor? > I am using a 4000E board with the Xilink Software in my university, but >I need to do some things in home. Can't I use another editor to build my >circuits and then use them with Xilink Software? > > Thank you. > >Article: 30453
I'd love to see some useful tools at least for testbenching, and the like evolve from 'C'-language tools. That's about as far as they've gone so far. However, if they ever figure out how to make a language operate in parallel rather than serial fashion, it may evolve into something useful for this task. Dick On Sat, 7 Apr 2001 18:46:03 -0700, "Compilit" <compilehr@yahoo.com> wrote: >Does anyone what the future will be like for Verilog and VHDL ? > >Wil it be replaced by C/C++ platform ? > >It looks like Handel C is taking oof. > >What I am wondering is will DK-1 suite be able to convert the test benches >into a supported >language as well ? For ASIC conversion, that is.. > >http://www.infoconomy.com/pages/search/group18585.adp > >http://isdmag.com/story/OEG20010301S0056 > >http://www.celoxica.com/news/in_the_news.htm > >Article: 30454
Any suggestions for an FPGA or CPLD that can do the following? Core Logic: only the equivalent of 60 or so CPLD 'macrocells' ..... just edge detectors & 4-to-16 decoders. No arithmetic needed. slow I/O: 10 Mhz TTL/LVTTL inputs (4), clock (1), and outputs(18). fast I/O: 200 Mhz PECL clock (1) producing 100 Mhz output (1). [I want plenty of margin on this, not just squeeking by at 200 Mhz.] Power Supply: 3.3v/Gnd. I know Dynachip could have done this, but they went out of business. Basically, a small PLD that can do fast PECL as well as traditional slower TTL. Any ideas? -- ============================== William Lenihan lenihan3weNOSPAM@earthlink.net .... remove "NOSPAM" when replying ==============================Article: 30455
Rick Filipkiewicz wrote: > Oh dear it looks like the memory leak, fixed in 5.4, has come > back. I never noticed it had been fixed (or was it worse on earlier versions?). I've always had this problem with 5.4 > If you are running under NT use task manager to see what the > vsim memory useage is. What used to happen is that on every > restart you could see 10-15MBytes being added. I'll check -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 30456
Does anyone know if the phase relationship between the clk2x and clk0 output of a spartan-II DLL known? The DCM in Virtex-II states clk2x and clk0 is in phase, but I can't seem to find anywhere in xilinx's docs mentioning the phase relationship of the two in a Spartan-II CLKDLL. I can do some measurement myself, but it will be nice if they are by design in-phase. I'll need both clock in my design. Thanks. Hayden (email me by removing the nospam part of the email address)Article: 30457
William Lenihan wrote: > Any suggestions for an FPGA or CPLD that can do the following? > > slow I/O: 10 Mhz TTL/LVTTL inputs (4), clock (1), and outputs(18). > fast I/O: 200 Mhz PECL clock (1) producing 100 Mhz output (1). [I want > plenty of margin on this, not just squeeking by at 200 Mhz.] > > Basically, a small PLD that can do fast PECL as well as traditional > slower TTL. > > Any ideas? Do you also need PECL output? I am experimenting with PECL input to Spartan-II FPGA by configuring the input as GTL and using a higher VREF. I have no results yet, but it should work. There are also affordable CMOS level clock synthesizers available at 200 MHz. Kolja SulimmaArticle: 30458
How to synthesize project which uses falling edge clocking using Xilinx Foundation 3.x? DamirArticle: 30459
Just out of interest. I bought low voltage flash from Avnet. Nobody else wanted to help me but Avnet delivered it (via UPS) to my door in a couple of days. It was one of the effortless component procurement exercises ever, so I agree that you should try Avnet's WEB site. "Dave Vanden Bout" <devb@xess.com> wrote in message news:3AD06029.A7A1D1C2@xess.com... > Richard Martineau wrote: > > > hello everybody > > > > does anyone have a spare minute to tell me where I can get a price list for > > Xilinx Spartan 2 range? > > > > Richard > > Go to http://www.em.avnet.com and do a search for parts starting with "XC2S". > You will get prices for all Spartan2 speed grades and packages. You don't get > any large-volume pricing and the small quantity pricing is a few bucks more > than what you will get from your distributor, but it will give you an idead of > what you will have to pay and the relative prices of various options. > > > -- > || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || > || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || > || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || > >Article: 30460
"Xilinx Announces MicroBlaze: World's Fastest FPGA Soft Processor": http://www.xilinx.com/prs_rls/0133microblaze.htm. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 30461
Is that your design, Jan? Jan Gray wrote: > > "Xilinx Announces MicroBlaze: World's Fastest FPGA Soft Processor": > http://www.xilinx.com/prs_rls/0133microblaze.htm. > > Jan Gray, Gray Research LLC > FPGA CPU News: www.fpgacpu.org -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30462
They are aligned. It's described in the Virtex data sheet under DLL timing parameters: Phase offset between clock outputs = max 140 ps. It may also be descibed better elsewhere, but trust me, they are aligned. Peter Alfke, Xilinx Applications Hayden So wrote: > Does anyone know if the phase relationship between the clk2x and clk0 output of a spartan-II DLL known? The DCM in Virtex-II states clk2x and clk0 is in phase, but I can't seem to find anywhere in xilinx's docs mentioning the phase relationship of the two in a Spartan-II CLKDLL. I can do some measurement myself, but it will be nice if they are by design in-phase. I'll need both clock in my design. > > Thanks. > > Hayden > (email me by removing the nospam part of the email address)Article: 30463
"Ray Andraka" <ray@andraka.com> asked > Is that your design, Jan? No, it's not. Jan Gray, Gray Research LLCArticle: 30464
Hi there. I am a total FPGA newbie, so i have a few questions. What would be the best fpga to start with ? I just wanna play with simple things in the beginning like counters, small controllers and stuff like that. It should be cheap and also easy to connect to a PC to program it. Does there exist some free VHDL software ? Hopefully with simulator. Please help me. -- With many Thanks Soren ' Disky ' Reinke ICQ #1413069 Remove IHSYD from email address when replying by emailArticle: 30465
"Peter Alfke" <peter.alfke@xilinx.com> wrote in message
news:3ACDFFEC.BEFA4706@xilinx.com...
> Yes, yes: The phase can be programmed by configuration, but the phase can
also
> be adjusted during normal operation by pulsing the increment/decrement
input of
> the DCM. See the description on pages 171...175 of the Virtex-II Handbook.
I think to be accurate, this should be a qualified "yes". The engineering
samples of the XC2V40 and XC2V1000 do not support this feature. According
to the errata we received with some XC2V1000-4FG256CES parts, last week:
"DCM Fine Phase shift operation - the "variable" shift mode of the DCM
Fine Phase Shift feature is not available in these devices. "Fixed" shift
mode is available for use."
If you need the feature, you will probably have to wait for the next die
revision. Admittedly, I have not yet checked for a possible workaround, as
we weren't planning on playing with this feature for at least a couple of
weeks.
Regards,
Erik Widding.
--
Birger Engineering, Inc. -------------------------------- 781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com
Article: 30466Nicolas Matringe wrote: > Rick Filipkiewicz wrote: > > > Oh dear it looks like the memory leak, fixed in 5.4, has come > > back. > > I never noticed it had been fixed (or was it worse on earlier > versions?). I've always had this problem with 5.4 > > > If you are running under NT use task manager to see what the > > vsim memory useage is. What used to happen is that on every > > restart you could see 10-15MBytes being added. > > I'll check > It was fixed in 5.4c. Have a look in the release notes under the section: General Defects Repaired in Release 5.4c second item. AFAIK it had been there for a long time.Article: 30467
Currently I work as a IT suport Eng. (Yuk!) but I'm watching Handle-C make a differance were I work - The hardware department look a little worried as one of the softy's is going grate guns with his evaluation copy of Handle-C. It will be intresting to see how adapts to it better, the Embeded C programmer or the Expert VHDL Engineer who thinks he knows nothing about software ( he needs to look at some C code to see the simularits! ). I would love to have a change ( being a hardware engineer at hart with many years of C also under my belt). Currenly I have to fullfill my needs as a hardwear Eng. at home programming MAX7000's and FLEX10K's but also doing some assembler on a 68hc811. I remmber using EPROMS as logic when I was a kid! still better than spending hours wiring up 7400's chips - although I did plently of that two 8o) Oh well - one day I get back in full time as a hardware Eng! Once I'v mastered VHDL and Handle-C I guess? Cyber_Spook niki wrote: > Worry? No way... > > I spent about 10 years doing semi-conductor design. Recently, I started to > feel more comfortable than ever before since fresh graduates have no idea > of what they are doing with HDL. :-) Thanks to synthesis tools, they > believe they are doing right job by clicking. > > If I am a bit cynical, sorry for that. But, that is true. ;-) > > cyber_spook <pjc@cyberspook.freeserve.co.uk>ÀÌ(°¡) > <3AD0DE23.F06C20C7@cyberspook.freeserve.co.uk> ±â»ç¿¡¼ ÀÛ¼ºÇß½À´Ï´Ù... > > > > At the end of the day if you are good at what you do - why worry - its > the > > hardware chaps that have been blagging there boss for years that are in > > danger!Article: 30468
I beleve that there are some commands that tell the complier what to process in parellel!? cyber_spook Richard Erlacher wrote: > I'd love to see some useful tools at least for testbenching, and the > like evolve from 'C'-language tools. That's about as far as they've > gone so far. However, if they ever figure out how to make a language > operate in parallel rather than serial fashion, it may evolve into > something useful for this task. > > Dick > > On Sat, 7 Apr 2001 18:46:03 -0700, "Compilit" <compilehr@yahoo.com> > wrote: > > >Does anyone what the future will be like for Verilog and VHDL ? > > > >Wil it be replaced by C/C++ platform ? > > > >It looks like Handel C is taking oof. > > > >What I am wondering is will DK-1 suite be able to convert the test benches > >into a supported > >language as well ? For ASIC conversion, that is.. > > > >http://www.infoconomy.com/pages/search/group18585.adp > > > >http://isdmag.com/story/OEG20010301S0056 > > > >http://www.celoxica.com/news/in_the_news.htm > > > >Article: 30469
Robert Carney wrote: > > some lines below deleted, sorry if I mis-snipped.... > > Rick Filipkiewicz <rick@algor.co.uk> wrote...... > > > "S. Ramirez" wrote: > > > I personally think that HDLs will evolve to C eventually, > > Saying HDLs will evolve to C is like saying humans will evolve to monkeys. > > >> but the real problem is that HDL is only a part of FPGA design> > >> They are mostly trying to talk to managers and saying: > > ``Hey guys here are some tools that will allow you to throw away all those > > expensive, rare h/w types & replace them with off-the-shelf el-cheapo s/w > > grunts'' > > > > The sad thing is my experience of most management types says they will buy > it - > > its what MBA training is all about. Remember these are the same people for > who > > marketing target with their whizzo GUIs [what other purpose do all those > screen > > shots on the Web serve ?]. > > > > What I actually don't understand is why the C-based tools are needed ? > Verilog > > is so easy to write that at the pure coding level any reasonably competent > C/C++ > > programmer could pick it up in a couple of days. Then with a couple of years > > practice they might, if they have the right mentality (*), get to produce > h/w > > that's not an embarrasment to their company. > > > > (*) This is not just to do with timing, metastability, etc. My fear here is > that > > s/w types do not have the deep, ingrained, awareness that from day 1, hour > 1, > > minute 1 of design start any mistake they make could be fatal. s/w bug = fix > it > > & put a patch file on the Web, h/w bug = a $250K+ ASIC respin. > > > > I think that if C alone were enough for hardware design, it would have > been used instead of Verilog or VHDL. As it turns out, the programmer's > model is quite different for one case compared to the other. For C, as > with other system programming languages, the focus is on algorithms and > data structures used in the one-instruction at a time sequential flow. > To support hardware modeling, it was necessary to extend C to allow > the programmer to model the passage of time and the execution of > statements in concurrent processes. Actually Handel-C is thinly disguised occam which does have all those features. -- A E LawrenceArticle: 30470
Rick Filipkiewicz wrote: > snip > > What I actually don't understand is why the C-based tools are needed ? Verilog > is so easy to write that at the pure coding level any reasonably competent C/C++ > programmer could pick it up in a couple of days. Then with a couple of years > practice they might, if they have the right mentality (*), get to produce h/w > that's not an embarrasment to their company. yep, figuring out how to describe the HW in what ever language you choose shouldn't be a big issue, figuring out what HW to describe is the hard part > > (*) This is not just to do with timing, metastability, etc. My fear here is that > s/w types do not have the deep, ingrained, awareness that from day 1, hour 1, > minute 1 of design start any mistake they make could be fatal. s/w bug = fix it > & put a patch file on the Web, h/w bug = a $250K+ ASIC respin. you could start them up slowly by having them write code to be put in ROM :) -Lasse -- DK-9000Article: 30471
> > "S. Ramirez" wrote:
> > > I personally think that HDLs will evolve to C eventually,
> "Robert Carney" wrote:
> Saying HDLs will evolve to C is like saying humans will evolve to monkeys.
Looks like we're there already!
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL 32765
Article: 30472Duties: Design board-level logic and PCB for next generation product. Also responsible for bringing up system and for diagnostics, and for interfacing with manufacturer/vendor. Required Skills and Experience: 1. 3 years logic and CPLD/FPGA design experience 2. 3 years hands-on experience doing PCB layout 3. Expert use of Cadence Allegro. 4. Expert use of schematic capture tool 5. Experience doing high speed digital design (>100MHz) Additional Skills and Experience Desired: 1. Expert use of lab equipment such as Logic Analyzers and high-speed scopes. 2. CPLD/FPGA design, SPICE simulation tools, System Thermal and Power Analysis 3. C/C++, Verilog, Altera MAX+ 4. Knowledge of ATE systems, experience with analog or RF design 5. Knowledge of FCC issues 6. Experience developing a product that was released to the market. Education: BSEE or MSEE -- Send Resumes to: Michael Morell Terran Systems michaelm@terransys.com 408-727-9000Article: 30473
Richard Erlacher <edick@hotmail.com> wrote in message news:3ad142ec.42595873@mindmeld.idcomm.com... > I'd love to see some useful tools at least for testbenching, and the > like evolve from 'C'-language tools. That's about as far as they've > gone so far. However, if they ever figure out how to make a language > operate in parallel rather than serial fashion, it may evolve into > something useful for this task. > Lots of research goes on in the area of parallel compilers. Most of the comments on this thread assume a more or less static environment with little innovation. Over time, we will see the advent of pure C/C++ that can be targeted to HW or a processor (now that FPGAs have powerful CPUs on them). Will the HW be as good as hand-crafted designs? Probably not, but as the FPGA vendors make corresponding improvements to their tools, true co-design tools will become available. Its inevitable.Article: 30474
Hi Soren, I would recommend an Altera FPGA, preferrably a MAX. They are easily programmed trough a cable, which you can make yourself, and the development software is free and easy to use. I don't think the free version supports VHDL though. Best of luck, Kristian Rye Vennesland -- ----------------------------------- Kristian Rye Vennesland E-mail : Kristirv@stud.iet.hist.no Cell.phone : +47 97 03 14 94 Mail Address: Kristian Rye Vennesland Nonnegata 2B 7014 Trondheim N-7014 NORWAY -----------------------------------
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