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Hello,
we have a problem at power on/reset. If we rely on the reset from GSR at
power on our fpga design does not start up correctly. If we generate a reset
from an external pin everything works fine.
Any ideas?
Neil Badenoch
Article: 30401Oh, that was a bit stupid I guess. Who said I need clk90 output to get 90 degrees shifted clock, I can just use one additional DCM to get 90degrees shifted clock, phase shift is possible in high frequency mode as well, right? Mexx. "Meelis Kuris" <matiku@hot.ee> wrote in message news :3acda8b0@news.estpak.ee... > I have a similar problem, I need 4 phases of 270MHz clock. > But in Virtex-II, in low frequency mode I get only 210MHz from DCM, > in high frequency mode clk90 output is not available. > Will it work if I first create two 135MHz clocks with 45 degrees phase shift > in low freq mode and then multiply both by 2 in high freq mode? > The phase shift doesn't have to be very precise, -/+10 degrees would be ok > I think. > > Mexx. > > "Peter Alfke" <palfke@earthlink.net> wrote in message > news:3ACD5062.7425E890@earthlink.net... > .. > > Virtex-II goes further than that, it allows you to define the phase > > delay of any clock in increments of 1/256 of the clock period, > > implemented with stable delays of 50 ps increment. And there are 16 > > low-skew clock networks... > > > > So, Virtex-E gets you halfway to your goal, and Virtex-II easily meets > > all your requirements, even if it were *NOT* an even division of the > > clock period. And you get hundreds or thousands of flip-flops and LUTs > > plus a bunch of BlockRAMs and multipliers as a bonus. Should be hard to > > resist :-) > > > > Peter Alfke, Xilinx Applications > > > > >Article: 30402
Peter Alfke ha scritto nel messaggio <3ACD5062.7425E890@earthlink.net>... > >Virtex-II goes further than that, it allows you to define the phase >delay of any clock in increments of 1/256 of the clock period, >implemented with stable delays of 50 ps increment. And there are 16 >low-skew clock networks... Peter, does it's possible these delays to be programmed in configuration only or it can be used also to obtain a variable delay during the nornal FPGA working? LuigiArticle: 30403
Vitaliy, Thank you for your quick response.... I'm a little surprised because I can't find any passive serial documentation that says this. The only info I can find on TRST relates to JTAG and is (supposedly) optional. It even says to pull it up if it's unused. I don't question your feedback, I just need to confirm 100% that this is my problem. Can you refer me to any relevant Altera docs or resources. In the meantime, I'll check the artwork to see if I can fix this or if I need to throw away all my boards and get them reprinted :(( Thanks again for the info, it is VERY helpful. Andrew "Vitaliy Tkachenko" <vit@telus.net> wrote in message news:zbez6.4006$Tj4.812404@news0.telusplanet.net... > If the 20ke's are set up for passive serial configuration, TRST pins should > be tied to GND. To be able to configure the devices via the JTAG chain you > need to connect the pins to I/O Vcc. > > Vitaliy > > >Article: 30404
Green Mountain Computing Systems, Inc. is currently offering free licenses to version 2.0 beta of VHDL Studio for beta testing. VHDL Studio is a design suite including VHDL Simulator, graphical State Machine Editor, graphical Testbench Editor, and IDE. For details, see http://www.gmvhdl.com/betatest.htmlArticle: 30405
Hi, I've been doing since fall among schematics designing and PIC/HC908/CV5410 coding + some FPGA and CPLD designs, like cleaning old designs and creating new to the CPLDs. I first disliked the idea of doing anything with these black logics but must admit that I am a bit in love to them now. I love the parallel nature of carrying things out and the large number of I/Os. :) However, the thing is that these little beasts waste LOTS of power whereas I am involved in innovative (small entrepreneur) projects where the power source is battery, i.e., I cannot put the experience and knowledge gained from CPLD/FPGA circuit design into interesting (to me) applications. A bit frustrating feeling. So, could someone point to a document where it is explained the physics, or why these programmable logics draw so much current? And better, is there bound to be any change to this? New design perhaps? From anyone? I heard rumour that Lattice would introduce this summer a new CPLD circuit that wastes only few hundred microamps supply current. That is what I can stand and have a few targets for such circuits. So can anyone verify this rumour? Greetings, Matti RuusunenArticle: 30406
Yes, yes: The phase can be programmed by configuration, but the phase can also be adjusted during normal operation by pulsing the increment/decrement input of the DCM. See the description on pages 171...175 of the Virtex-II Handbook. This is a neat feature for adaptive pin-to-pin set-up/hold time control. You get 50 ps resolution. :-) Peter Alfke ============================== luigi funes wrote: > Peter, > does it's possible these delays to be programmed in configuration only or it > can be used also to obtain a variable delay during the nornal FPGA working? > > LuigiArticle: 30407
--------------3F98610ACBB048FDA48D81CD Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit Look at XAPP090. It shows you the start-up options that allow you to control GSR early or late. http://www.xilinx.com/xapp/xapp090.pdf Peter Alfke, Xilinx Applications ( who wrote that app note in 1997 ) ================================== Neil Badenoch wrote: > Hello, > > we have a problem at power on/reset. If we rely on the reset from GSR at > power on our fpga design does not start up correctly. If we generate a reset > from an external pin everything works fine. > > Any ideas? > > Neil Badenoch --------------3F98610ACBB048FDA48D81CD Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> Look at XAPP090. It shows you the start-up options that allow you to control GSR early or late. <p><u><A HREF="http://www.xilinx.com/xapp/xapp090.pdf">http://www.xilinx.com/xapp/xapp090.pdf</A></u> <p>Peter Alfke, Xilinx Applications <br>( who wrote that app note in 1997 ) <br>================================== <br>Neil Badenoch wrote: <blockquote TYPE=CITE>Hello, <p> we have a problem at power on/reset. If we rely on the reset from GSR at <br>power on our fpga design does not start up correctly. If we generate a reset <br>from an external pin everything works fine. <p> Any ideas? <p> Neil Badenoch</blockquote> </html> --------------3F98610ACBB048FDA48D81CD--Article: 30408
I just got the latest version of AN116 and I noticed that Figure 12., PS Multi-Device Configuration with a Microprocessor, now has a note next to the CONF_DONE pull up. It needs to be a 10k, not a 1k....hmmmm.... I'm not too happy about that, but I wouldn't expect that to cause initial failure. Especially since nStatus has the same note and that signal works fine. Any thoughts? Thanks, AndrewArticle: 30409
Nicolas Matringe wrote: > "W.Turk" wrote: > > > > Hi Gang: > > Now ,i use Modelsim5.5.When i load or run a large design,it > > will always close automatic. > > Why? > > I have the same problem and I think, as Utku suggested, that it is RAM > related. > It usually happens when I restart the simulation. It works fine after > freeing some RAM. > > - Oh dear it looks like the memory leak, fixed in 5.4, has come back. If you are running under NT use task manager to see what the vsim memory useage is. What used to happen is that on every restart you could see 10-15MBytes being added.Article: 30410
Hi Matti,
I am looking at the Xilinx Coolrunner CPLDs. Their development board
with a CPLD and LCD screen consume only 60 microamps. They power if from
grapefruits! Check out their web site: www.xilinx.com
Ryan
"Matti Ruusunen" <matti.ruusunen@removeme.soredex.com> wrote in message
news:%2mz6.240$qw5.10624@read2.inet.fi...
> Hi,
>
> I've been doing since fall among schematics designing and PIC/HC908/CV5410
> coding + some FPGA and CPLD designs, like cleaning old designs and
creating
> new to the CPLDs. I first disliked the idea of doing anything with these
> black logics but must admit that I am a bit in love to them now. I love
the
> parallel nature of carrying things out and the large number of I/Os. :)
>
> However, the thing is that these little beasts waste LOTS of power whereas
I
> am involved in innovative (small entrepreneur) projects where the power
> source is battery, i.e., I cannot put the experience and knowledge gained
> from CPLD/FPGA circuit design into interesting (to me) applications. A bit
> frustrating feeling.
>
> So, could someone point to a document where it is explained the physics,
or
> why these programmable logics draw so much current? And better, is there
> bound to be any change to this? New design perhaps? From anyone?
>
> I heard rumour that Lattice would introduce this summer a new CPLD circuit
> that wastes only few hundred microamps supply current. That is what I can
> stand and have a few targets for such circuits. So can anyone verify this
> rumour?
>
>
> Greetings,
> Matti Ruusunen
>
>
>
Article: 30411<snip> > "Matti Ruusunen" <matti.ruusunen@removeme.soredex.com> wrote > > I've been doing since fall among schematics designing and PIC/HC908/CV5410 > > coding + some FPGA and CPLD designs, like cleaning old designs and > creating > > new to the CPLDs. I first disliked the idea of doing anything with these > > black logics but must admit that I am a bit in love to them now. I love > the > > parallel nature of carrying things out and the large number of I/Os. :) > > > > However, the thing is that these little beasts waste LOTS of power whereas > I > > am involved in innovative (small entrepreneur) projects where the power > > source is battery, i.e., I cannot put the experience and knowledge gained > > from CPLD/FPGA circuit design into interesting (to me) applications. A bit > > frustrating feeling. > > > > So, could someone point to a document where it is explained the physics, > or > > why these programmable logics draw so much current? And better, is there > > bound to be any change to this? New design perhaps? From anyone? > > > > I heard rumour that Lattice would introduce this summer a new CPLD circuit > > that wastes only few hundred microamps supply current. That is what I can > > stand and have a few targets for such circuits. So can anyone verify this > > rumour? It depends a lot on your frequency, and on the technology. All devices have a DC current, and a mA/MHz slope. As the clock frequency increases, all logic will draw more current. We are studying CPLD for LCD drivers, and sub 10uA (typ) is looking feasible, in ATF1504ASVL series - at low freqs these draw less than coolrunner, So, if you are using these as IO, and not at tens of MHz, look at the ATF15xx family. Also, given CMOS process nature, VERY low Idd will be easier at 3V than 5V. - jg -- ======= 80x51 Tools & PLD IP Specialists ========= = http://www.DesignTools.co.nzArticle: 30412
Does any one know of any issues using Win95 and programming Xilinx's XL95288 BGA?Article: 30413
Hi All,
I am using Xilinx Virtex-E XCV400E FG676-6. I am in need of experienced
people's to help solve my DLL locking problem.
I have two DLLs in my FPGA.
The first one locks onto a 61 Mhz PAD input clock to output a 1X and a 2X
(122Mhz) clock for internal FPGA use. The 1X output is used as the feed
back clock.
The second locks onto the same PAD input 61MHz clock to output a 2X clock.
This 2X clock is used to drive some off-chip on-board RAMs. The external 2X
clock is used as the feedback clock (for on-board clock de-skew/mirror
purpose).
I have a reset signal for both DLLs.
Now my problems/questions:
1a) After the system clock and everything else is up and running, I assert
and de-assert the reset signal of the DLLs. However, I do not get clock
outputs all the time. In fact, usually I have to try up to about 8 times
before the DLLs achieve lock. Sometimes, the output clock appears and
disappers in a flash.
1b) Quite often, even if lock is achieved, my DLL loses lock after some time
(it is especially prone to losing lock when I am adjusting some DIP switches
on the board). But then, it has also run for hours without losing lock.
1c) Some times, after the output clock is lost, the LOCK signal remains
asserted.
I have read the comp.arch.fpga newsgroup's past threads like "Virtex II DLL
at 311MHz on XCV300e-8ES", "PLL vs DLL" and "DLL
unlocking". I gather that
a lousy (jittery, low amplitude, reflections) input clock may be the cause
of difficulty in locking. Is there any other possible cause beside this?
2) For the second DLL, up till now, I have NEVER seen the LOCK signal goes
up, even though there is a 2X clock running at the output. This means the
output is not locked to the feedback clock, right? Why is it not locking?
Is there a problem with using a 2X clock output as the feed back clock?
Would I be better off using the 2x output of the first DLL as input to the
second DLL (and using the 1X output)?
3) Xilinx DLL has a period tolerance (about 1ns) and jitter tolerance (about
150ps). What is the difference between these two parameters? Does the same
requirement apply to the feedback clock?
4) Why doesn’t a DLL try to regain lock?
A million thanks in advance.
TA TA
kahhean
----------------------------------------------------------------------------
------------
--vhdl code below
----------------------------------------------------------------------------
----------
entity ClockGen is
port(
CLK1X_I: in std_logic; --Incoming clock
CLK2X_EXT_FB_I: in std_logic; --Feedback signal for the external clock
PDN_I: in std_logic;
DLL_INT_LOCKED_O: out std_logic;
DLL_ZBT_LOCKED_O: out std_logic;
CLK1X_INT_O: out std_logic; --2X clk available inside the fpga
CLK2X_INT_O: out std_logic; --2X clk available inside the fpga
CLK2X_EXT_O: out std_logic); --2X clk going out of the fpga
end ClockGen;
architecture RTL of ClockGen is
signal logic0,logic1: std_logic;
signal clk1x,clk1x_prebuf,clk2x,clk2x_prebuf: std_logic;
component CLKDLL
port(clkin : in std_logic;
clkfb : in std_logic;
rst : in std_logic;
locked: out std_logic;
clk0 : out std_logic;
clk2x : out std_logic);
end component;
component BUFG
port(I : in std_logic;
O : out std_logic);
end component;
begin
logic0 <= '0';
logic1 <= '1';
I_dll_int : CLKDLL
port map (clkin => CLK1X_I,
clkfb => clk1x,
locked => DLL_INT_LOCKED_O,
rst => PDN_I,
clk2x => clk2x_prebuf,
clk0 => clk1x_prebuf);
I_bufg_clk1x_int : BUFG
port map (I => clk1x_prebuf,
O => clk1x);
I_bufg_clk2x_int : BUFG
port map (I => clk2x_prebuf,
O => clk2x);
CLK1X_INT_O <= clk1x;
CLK2X_INT_O <= clk2x;
--clock 2x external
I_dll_zbt : CLKDLL
port map (clkin => CLK1X_I,
clkfb => CLK2X_EXT_FB_I,
locked => DLL_ZBT_LOCKED_O,
rst => PDN_I,
clk2x => CLK2X_EXT_O);
end RTL;
------------------------------------------------
-- Top level
------------------------------------------------
U_SYSCLK : IBUFG
Port Map ( I => SYSCLK_IN, O => SYSCLK);
U_ZBTCLK : OBUF_F_24
Port Map ( I => ZBT_CLK, O => ZBT_CLK_OUT );
U_ZBTCLKFB: IBUF
Port Map ( I => ZBT_CLKFB_IN, O => ZBT_CLKFB);
U_ClockGen : ClockGen
Port Map
CLK1X_I => SYSCLK,
CLK2X_EXT_FB_I => ZBT_CLKFB,
PDN_I => pdn_dll,
DLL_INT_LOCKED_O => dll_int_locked,
DLL_ZBT_LOCKED_O => dll_zbt_locked,
CLK2X_EXT_O => ZBT_CLK,
CLK1X_INT_O => CLK61,
CLK2X_INT_O => CLK122);
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Article: 30414On popular demand, these package files will be on the external Xilinx website soon..... -Vikram Xilinx Applications Rick Filipkiewicz wrote: > Vikram Pasham wrote: > > > The package file format did not show up properly in my earlier mail. > > > > Physical Row/Col-RAM Package VCCO IO Output LVDS > > Name Location Name Bank Type Asynchronous > > > > -Vikram > > > > Vikram Pasham wrote: > > If you have them why don't you just put them on the Web ?Article: 30415
Hi Andrew, For passive serial cofiguration with a EPC2 device you need the following pull-ups: nSTATUS 10k to VCC, CONFIG_DONE 10k to VCC, nCONFIG 1k to VCCINT !!! If you found an errata note to AN116, you might see that nCONFIG should be pulled up to VCCINT. Though they mentioned that this is only to guarantee normal functioning with all possible power sequencing situations. Possibly it is not so critical, because the Altera's NIOS development board has a 7032 device, which configures a 20ke200 device (parallel configuration scheme), and there they use only two pull-ups for nSTATUS and for CONFIG_DONE - both 1k to VCC (on Figure 12 AN116 there is an example of serial confuguration using same pull-ups). And to enable JTAG configuration they tied TRST to VCC. In AN116, p55, Figure 29 Note11 you can see how to connect TRST. There is an error on the drawing. TRST belongs to the FPGA device, not EPC2. Vitaliy. "Andrew Hosmer" <ahosmer@scoundrelz.com> wrote in message news:tapz6.3871$Nb.1764048@typhoon2.ba-dsg.net... > I just got the latest version of AN116 and I noticed that Figure 12., PS > Multi-Device Configuration with a Microprocessor, now has a note next to the > CONF_DONE pull up. It needs to be a 10k, not a 1k....hmmmm.... I'm not too > happy about that, but I wouldn't expect that to cause initial failure. > Especially since nStatus has the same note and that signal works fine. Any > thoughts? > > Thanks, > Andrew > > > >Article: 30416
Hi can anybody suggest something on how to configure FPGA in a PC based design? Regards SBArticle: 30417
> Hi > can anybody suggest something on how to configure FPGA in a PC based design? > Regards > SB If your FPGA is the PCI Interface, you have no choice than configuring the FPGA without PC CPU interaction, for example from a FLASHROM that is controled by a CPLD or small embedded CPU or from one of these expensive configuration PROMs. If you have a standalone PCI interface (from PLX, Galileo, or others) you can use this to load data in the FPGA. If you want to do ISA, you can build your ISA interface with a FlashCPLD an use that to load the FPGA. USB controllers are kind of neat for configuring FPGAs. In the category "best abuse of the rules": It should be quite simple to configure an FPGA from an AC97 serial port, that is on most mainboards today. KoljaArticle: 30418
Good Morning! Part of the difference is that I'm not using a 'configuration device', such as the EPC2. Figure 12 describes my method (multi-device using microprocessor). The EPM7160s is only for host interface logic. That being said, it is still worthy of note that Fig. 29 specifically mentions grounding TRST when not using JTAG. I agree it should be done to be thorough, but if it is truly required I think it should be in every configuration section of the AN (Altera are you listening?). I'm encouraged that Altera's NIOS board only uses 1k pull-ups for the 20ke. Thanks for making me feel better :) Regards, and thanks again, Andrew "Vitaliy Tkachenko" <vit@telus.net> wrote in message news:m1zz6.351$%B2.94040@news1.telusplanet.net... > Hi Andrew, > For passive serial cofiguration with a EPC2 device you need the following > pull-ups: > nSTATUS 10k to VCC, > CONFIG_DONE 10k to VCC, > nCONFIG 1k to VCCINT !!! > If you found an errata note to AN116, you might see that nCONFIG should be > pulled up to VCCINT. Though they mentioned that this is only to guarantee > normal functioning with all possible power sequencing situations. > Possibly it is not so critical, because the Altera's NIOS development board > has a 7032 device, which configures a 20ke200 device (parallel configuration > scheme), and there they use only two pull-ups for nSTATUS and for > CONFIG_DONE - both 1k to VCC (on Figure 12 AN116 there is an example of > serial confuguration using same pull-ups). > And to enable JTAG configuration they tied TRST to VCC. > In AN116, p55, Figure 29 Note11 you can see how to connect TRST. There is an > error on the drawing. TRST belongs to the FPGA device, not EPC2. > Vitaliy. > > "Andrew Hosmer" <ahosmer@scoundrelz.com> wrote in message > news:tapz6.3871$Nb.1764048@typhoon2.ba-dsg.net... > > I just got the latest version of AN116 and I noticed that Figure 12., PS > > Multi-Device Configuration with a Microprocessor, now has a note next to > the > > CONF_DONE pull up. It needs to be a 10k, not a 1k....hmmmm.... I'm not > too > > happy about that, but I wouldn't expect that to cause initial failure. > > Especially since nStatus has the same note and that signal works fine. > Any > > thoughts? > > > > Thanks, > > Andrew > > > > > > > > > >Article: 30419
I have never read a paper on this, but my bet would be that a combination of LFSRs is no better than a single LFSR of length equal to the sum of the lengths of the short LFSRs being combined. I am sure that the length of the combined sequence would be equal to the product of the individual lengths and this would be less than or equal to the length of the single long LFSR sequence. I would be willing to bet that there is a simple way to discover the three LFSRs in this examnple or to discover an equivalent single LFSR polynomial given a sufficiently long output sequence. Ray Andraka wrote: > > Actually, as long as you take one bit at a time, the randomness of an LFSR is > quite good, but the sequencer feedback polynomial as well as the current state > can be discovered by looking at the most recent bits, which makes it lousy for a > cryptographic application where knowing the sequence allows one to decipher the > encypted data. Using 3 LFSRs in combination obfuscates the sequence enough to > make discovery of the generating function much harder. If it is an encryption > you are after, then true enough a single LFSR is not sufficient. But the problem > stems from the ability to infer the polynomial and current state, not from the > apparent randomness of the bits. > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 30420
Vikram Pasham wrote: > > On popular demand, these package files will be on the external Xilinx > website soon..... Thank you. -- Phil HaysArticle: 30421
I have a design with an FPGA (XCS40XL) and 4 demodulated (at 500kHz) analog channels : 4x (AC amplifier + mixer (500 kHz LO)+ filter + 15dB amp + 24bit AD) + 2 fast AD channels (12Bits 100MHz each) I was wandering if I could replace the mixers+filters+15dB Amps+24bits ADs by the 12 bit 100MHz + FGPA and do the demodulation in the FPGA. It's rather easy to do but I would like to know what kind of performance I can get. Using the analog channels I get an equivalent input noise of 1.6pA/rtHz. How can I have an idea of what I would get using the FPGA demodulation. If it could work I will try this with 14 bit 65MHz AD + Virtex 300E (The XCS40XL is too small) Thanks Marc BattyaniArticle: 30422
hello everybody does anyone have a spare minute to tell me where I can get a price list for Xilinx Spartan 2 range? RichardArticle: 30423
the one I'm using has 8Mbytes divided across 4 ram banks i.e. 2Mbytes for each bank which each start at 0x0 address using the RC1000PP functions assuming you are using the prototyping board. however, when the host is addressing the fpga ram it sees it as a continuous block of memory so you have to use offsets to the start of each ram bank Richard <sam> wrote in message news:ee70229.-1@WebX.sUN8CHnE... > does anyone have an idea about the exact amount of onchip ram in a xilinx virtex XCV1000BG560. > > samArticle: 30424
Richard,
The best place to get that kind of information is your local Xilinx
manufacturer's rep. Call him/her to get pricing.
As an alternative, you can call Insight, Avnet or Nu-Horizons
distributors. They will have to go to the rep anyway to get pricing, so
this is one reason I suggest that you contact the rep first.
Here is another reason. If you are new to this and haven't contacted
the disties before, be prepared for a barrage of questions, phone calls,
hiya doings, questions, phone calls, what are you working on, phone calls,
questions, how many do you need, questions, phone calls, etc. Until they
establish clearly what you are working on, what product you need, how many
of each product you will order and when, and get a design registration in
place, you will be hounded by these people.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA
"Richard Martineau" <richard.martineau@btinternet.com> wrote in message
news:9angmf$s1k$1@neptunium.btinternet.com...
> hello everybody
>
> does anyone have a spare minute to tell me where I can get a price list
for
> Xilinx Spartan 2 range?
>
> Richard
>
>
>
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