Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
You can also generate a similar package pinout table using "partgen" command from Xilinx software. For example, to generate a pinout table for V1000E-FG900 use % partgen -v v1000efg900 This generates a package file "v1000efg900.pkg" and this file has pad, pin, bank and other info. Refer software manuals for more info on this package file format. http://toolbox.xilinx.com/docsan/3_1i/data/common/dev/chap03/dev03003.htm -Vikram Xilinx Applications Rick Filipkiewicz wrote: > Vikram Pasham wrote: > > > The package file format did not show up properly in my earlier mail. > > > > Physical Row/Col-RAM Package VCCO IO Output LVDS > > Name Location Name Bank Type Asynchronous > > > > -Vikram > > > > Vikram Pasham wrote: > > If you have them why don't you just put them on the Web ?Article: 30226
I have some EE books for trade. I am in the San Francisco Area. These all are all in brand new, unnused condition. Some have CD-ROM's included that are not yet opened. I bought them for a project now currently on hold. Please search www.abebooks.com or www.powells.com or www.Amazon.com for good deals on these, and get back to me. Please help me to get the books I need. The following list are what I currently have extra to be given away: 1/ Designer's Guide to VHDL by Peter Ashenden http://www.amazon.com/exec/obidos/ASIN/1558602704/qid=985827963/sr=1-3/ref=s c_b_4/002-1116465-7214451 2/ VHDL Analysis and Modeling of Digital systems 2ed by Navabi 3/ Computer Architechiture, and Quantitative Approach. 4/ Verilog Digital Computer Design. Algorithms into Hardware by Arnold 5/ Real World FPGA Design with Verilog by Ken Coffman 6/ VHDL Representation and Synthesis by Armstrong and Gary 7/ VHDL made easy by Tellering and Taylor 8/ Verilog HDL by Palnitkar 9/ Verilog Designer's Library by Zeidman 10/ Timing Verification (ASIC) by Farzd Nekoogar http://www.amazon.com/exec/obidos/ASIN/0137943482/ref=sim_books/002-1116465- 7214451 11/ VHDL by Douglas Perry 12/ VHDL for programmable logic by Kevin Skahill 13/ Real Time Signal Processing John G. Ackenhusen http://www.amazon.com/exec/obidos/ASIN/0136317715/qid=985827868/sr=1-2/ref=s c_b_3/002-1116465-7214451 14/ Object Oriented Perl by Conway 15/ Programming and Customizing PIC controller Predro 16/ PCI-X System Architecture Mindshare INC 17/ Application-Specific Integrated Circuits. By Smith 18/ VHDL for Logic Synthesis by Andrew Rushton http://www.amazon.com/exec/obidos/search-handle-form/002-1116465-7214451 ===================================================================== The following are what I am in desparate need for, I don't mind them in used conditions: 1/ http://www.amazon.com/exec/obidos/ASIN/0792377664/ref=ase_janickbergershom/0 02-1116465-7214451 Writing Testbenches - Functional Verification of HDL Models by Janick Bergeron 2/ System-on-a-Chip Verification - Methodology and Techniques http://www.amazon.com/exec/obidos/ASIN/0792372794/qid=985827145/sr=1-4/ref=s c_b_5/002-1116465-7214451 3/ Rajsuman, Rochit SYSTEM ON A CHIP DESIGN AND TEST http://dogbert.abebooks.com/abe/BookDetails?bi=75782617 4/Keating, Michael and Pierre Bricaud Reuse Methodology Manual For System-On-A-Chip Designs http://dogbert.abebooks.com/abe/BookDetails?bi=53348445 5/HDL chip design :a practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog http://www.powells.com/cgi-bin/biblio?inkey=2-0965193438-0 6/PRINCIPLES OF VERILOG PLI by Swapnajit Mittra http://www.powells.com/cgi-bin/biblio?inkey=4-0792384776-0 7/VHDL Coding and Logic Synthesis with Synopsys by Weng Fook Lee http://www.amazon.com/exec/obidos/ASIN/0124406513/qid=985827963/sr=1-6/ref=s c_b_7/002-1116465-7214451 8/Vhdl Coding Styles and Methodologies by Ben Cohen must be 2nd edition http://dogbert.abebooks.com/abe/BookDetails?bi=52919198 9/Cohen, Ben VHDL ANSWERS TO FREQUENTLY ASKED QUESTION 2nd edition http://dogbert.abebooks.com/abe/BookDetails?bi=55220448 10/Component Design by Example : a Step-by-Step Process Using VHDL with UART as Vehicle by Ben Cohen Thank you, Peace. Please click reply to email me.Article: 30227
Vikram Pasham wrote: > Call the hotline to get these package pinout in text format or let me know the > exact device /package and I will email it to you. The local Xilinx FAE mailed me the whole package. Nice. But let me ask the question that others are asking. Why isn't this on the Xilinx web site? It's handy. Also, I just tried the partgen tool. Much better than starting with cutting out of the .pdf, not quite as nice as the files the FAE mailed to me. -- Phil HaysArticle: 30228
> When I synthetize it with Fpga Express I got a warning saying > that no net is attached to port autosync. I dont understand > why and if I modify the code the following way ( I believe that > the functionnality is the same ): > > process(rxready, autosync) > begin > if rxready='0' and autosync='1' then > datamode <= '0'; > syncerr <= '1'; > else > syncerr <= not rxready; > datamode <= '1'; > end if; > end process; > > Then, the synthetizer doesn't report the warning anymore. I forgot to add that it doesn't report any warning but it DOES remove the port (I've seen that when I tried to resimulate my design). datamode and syncerr are really used and connected to some ports. The behavior of this in simulation is like if autosync was always tied to '0'. Now, I'm totally confused ;-( -- _______________________________________ | | | Jean-Marie Bussat | | Lawrence Berkeley National Laboratory | | 1 Cyclotron Road - MS 50A-6134 | | BERKELEY, CA 94720 - USA | | Email: JMBussat@lbl.gov | | Phone: (510)-486-5687 | | Fax: (510)-486-5977 | |_______________________________________|Article: 30229
Hello, <br> <br> I am trying to source an EXTERNAL 25 MHz oscillator that can feed into a Spartan 2 device. This will pass trough 2 DLLs to obtain an output frequency of 100 MHz. <br> <br> XAPP174 (page 8) states than any 100PPM quartz crystall oscilator can be used but the catch is the cycle to cycle jitter of 300 ps. <br> <br> Can any body recommend a 25MHz Oscillator that meets the cycle to cycle jitter spec in the SPARTAN 2 datasheet. <br> <br> Both the Spartan2 Datasheet and XAPP174 do not have any recommendation for oscillator brands or part numbers that meet these specs <br> <br> ( http://www.support.xilinx.com/xapp/xapp174.pdf ) <br> <br> Will Xilinx in the future provide any recommendations for external oscillators on their datasheets or app notes. This would save a lot of time and confusion. <br> <br> ThankyouArticle: 30230
Hi, I've problems with determining which NIC to use for Quartus licensing, as I get one NIC by ipconfig /all in DOS box, but three (!) NICs with HostIDs tab in FlexLM License manager. I have a Win2K Professional system with only one Ethernet card installed, thus I thought I should have only one NIC. Unfortunately Quartus seems to use the first NIC FlexLM offers, thus it's not the ipconfig'd NIC. More than this, the first two NICs are changing when the PC is restarted, thus I didn't have any chance to switch the license. Does anyone got similar problems fixed? TIA, Carlhermann SchlehausArticle: 30231
Hi, Jean-Marie.
I tried the following on Fuoundateioin Express v.1 (The synthesizer
is FPGA Express v3.4), so the setup is a little different than what
you have. But there were no problems. And looking at your code, I
can't see why you would get that warning. Maybe it's something in the
part of your code that you didn't include in your message? Maybe post
the entire entity/architecture.
Hope this helps,
-Kent
entity test is
port (
rxready, autosync : in bit;
syncerr, datamode : out bit
);
end entity test;
architecture test_a of test is
begin
process(rxready, autosync)
begin
if rxready = '0' then
syncerr <= '1';
if autosync = '1' then
datamode <= '0';
else
datamode <= '1';
end if;
else
syncerr <= '0';
datamode <= '1';
end if;
end process;
end architecture test_a;
Jean-Marie Bussat <JMBussat@lbl.gov> writes:
> I have a piece of code but the synthetizer doesn't react as I would
> expect at first glance. I have to following simple code (rxready and
> autosync are two input ports and datamode and syncerr are output
> ports):
>
> process(rxready, autosync)
> begin
> if rxready='0' then
> syncerr <= '1';
> if autosync='1' then
> datamode <= '0';
> else
> datamode <= '1';
> end if;
> else
> syncerr <= '0';
> datamode <= '1';
> end if;
> end process;
>
> When I synthetize it with Fpga Express I got a warning saying
> that no net is attached to port autosync. I dont understand
> why and if I modify the code the following way ( I believe that
> the functionnality is the same ):
Article: 30232Jean-Marie Bussat <JMBussat@lbl.gov> writes: > > When I synthetize it with Fpga Express I got a warning saying > > that no net is attached to port autosync. I dont understand > > why and if I modify the code the following way ( I believe that > > the functionnality is the same ): > > > > process(rxready, autosync) > > begin > > if rxready='0' and autosync='1' then > > datamode <= '0'; > > syncerr <= '1'; > > else > > syncerr <= not rxready; > > datamode <= '1'; > > end if; > > end process; > > > > Then, the synthetizer doesn't report the warning anymore. > > I forgot to add that it doesn't report any warning but it DOES > remove the port (I've seen that when I tried to resimulate my > design). > datamode and syncerr are really used and connected to some > ports. > The behavior of this in simulation is like if autosync was > always tied to '0'. > > Now, I'm totally confused ;-( So it ends up removing the 'autosync' port in both cases? I suggest posting the entire code. One possibility is that the IO pad for austosync isn't being inserted (It's a synthesis option.), so nothing is driving the net, so the logic is being removed. But I don't see why 'rxready' would be okay. -KentArticle: 30233
Mark Raviola wrote: > > Hello, > I am trying to source an EXTERNAL 25 MHz oscillator that can feed into a Spartan 2 device. This will pass trough 2 DLLs to obtain an output frequency of 100 MHz. > XAPP174 (page 8) states than any 100PPM quartz crystall oscilator can be used but the catch is the cycle to cycle jitter of 300 ps. Mark, Did you try one and have it fail, or does the 300ps sound daunting ? You can get a feel for jitter, and power supply tolerance, with some maths, on the XTAL sine wave, before it is squared up. 25Mhz is 20nS/half period, and if we take a 3V peak, thats a slew of ~3000mV/20ns or 150mV/nS. Put another way, a 45mV change on the sine threshold, is 300pS, so that's the order of uncertainty you need to be under. Std CMOS inverter gates commonly found in Oscillators have stable thresholds ( < 1mV cycle-cycle), but very poor Power supply rejection, so you need to ensure your OSC supply is clean ( << 45mV of peak noise ) So a separate regulator (or good filter) for the OSC is sounding like a good idea, but any Osc module should do. -jgArticle: 30234
Wow, by the time you get through all those VHDL books, you could have been on your 3rd or 4th design learning by doing and became an expert. Your first VHDL design, and probably the second will be best used as liners for the kitty litter pan no matter how much reading you do. You learn what really works in practice by making the mistakes. Of course it helps if you have someone else's code to look at too, but make sure you are not looking at someone else's cat box when you do. For the amount you spend on the books you probably could have picked up the Aldec tools (which have the best on-line references and tutorials I've ever seen) and played with the real thing. ANyway, you've got a pretty impressive library ammassed there. I'm not sure I'd trade away the Ashenden for any of your "must haves" though. Compilit wrote: > > I have some EE books for trade. I am in the San Francisco Area. > > These all are all in brand new, unnused condition. Some have CD-ROM's > included that are not yet opened. > I bought them for a project now currently on hold. > > Please search www.abebooks.com or www.powells.com or www.Amazon.com for good > deals on these, and get back to me. Please help me to get the books I need. > > The following list are what I currently have extra to be given away: > > 1/ Designer's Guide to VHDL by Peter Ashenden > http://www.amazon.com/exec/obidos/ASIN/1558602704/qid=985827963/sr=1-3/ref=s > c_b_4/002-1116465-7214451 > 2/ VHDL Analysis and Modeling of Digital systems 2ed by Navabi > > 3/ Computer Architechiture, and Quantitative Approach. > > 4/ Verilog Digital Computer Design. Algorithms into Hardware by Arnold > > 5/ Real World FPGA Design with Verilog by Ken Coffman > > 6/ VHDL Representation and Synthesis by Armstrong and Gary > > 7/ VHDL made easy by Tellering and Taylor > > 8/ Verilog HDL by Palnitkar > > 9/ Verilog Designer's Library by Zeidman > > 10/ Timing Verification (ASIC) by Farzd Nekoogar > http://www.amazon.com/exec/obidos/ASIN/0137943482/ref=sim_books/002-1116465- > 7214451 > > 11/ VHDL by Douglas Perry > > 12/ VHDL for programmable logic by Kevin Skahill > > 13/ Real Time Signal Processing John G. Ackenhusen > http://www.amazon.com/exec/obidos/ASIN/0136317715/qid=985827868/sr=1-2/ref=s > c_b_3/002-1116465-7214451 > > 14/ Object Oriented Perl by Conway > > 15/ Programming and Customizing PIC controller Predro > > 16/ PCI-X System Architecture Mindshare INC > > 17/ Application-Specific Integrated Circuits. By Smith > > 18/ VHDL for Logic Synthesis by Andrew Rushton > http://www.amazon.com/exec/obidos/search-handle-form/002-1116465-7214451 > > ===================================================================== > > The following are what I am in desparate need for, I don't mind them in used > conditions: > > 1/ > http://www.amazon.com/exec/obidos/ASIN/0792377664/ref=ase_janickbergershom/0 > 02-1116465-7214451 > Writing Testbenches - Functional Verification of HDL Models > by Janick Bergeron > > 2/ System-on-a-Chip Verification - Methodology and Techniques > http://www.amazon.com/exec/obidos/ASIN/0792372794/qid=985827145/sr=1-4/ref=s > c_b_5/002-1116465-7214451 > > 3/ Rajsuman, Rochit SYSTEM ON A CHIP DESIGN AND TEST > http://dogbert.abebooks.com/abe/BookDetails?bi=75782617 > > 4/Keating, Michael and Pierre Bricaud Reuse Methodology Manual For > System-On-A-Chip Designs > http://dogbert.abebooks.com/abe/BookDetails?bi=53348445 > > 5/HDL chip design :a practical guide for designing, synthesizing, and > simulating ASICs and FPGAs using VHDL or Verilog > > http://www.powells.com/cgi-bin/biblio?inkey=2-0965193438-0 > > 6/PRINCIPLES OF VERILOG PLI > by Swapnajit Mittra > http://www.powells.com/cgi-bin/biblio?inkey=4-0792384776-0 > > 7/VHDL Coding and Logic Synthesis with Synopsys by Weng Fook Lee > http://www.amazon.com/exec/obidos/ASIN/0124406513/qid=985827963/sr=1-6/ref=s > c_b_7/002-1116465-7214451 > > 8/Vhdl Coding Styles and Methodologies by Ben Cohen must be 2nd edition > http://dogbert.abebooks.com/abe/BookDetails?bi=52919198 > > 9/Cohen, Ben VHDL ANSWERS TO FREQUENTLY ASKED QUESTION 2nd edition > http://dogbert.abebooks.com/abe/BookDetails?bi=55220448 > > 10/Component Design by Example : a Step-by-Step Process Using VHDL with UART > as Vehicle > by Ben Cohen > > Thank you, > Peace. > > Please click reply to email me. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30235
> Could someone enlighten me ? Is PCI-X just a clock speed uprated 66MHz PCI > or are there any fundamental differences ? As far as I can see the only > significant change is to allow split cycles. It's basically registered. More clock cycles for control, but given it can support much higher clock rates, it's faster.Article: 30236
Yes, with a filtered power supply you should be well within 300ps jitter for an oscilator.
I always found oscillators quite expensive in small quantities.
You should have a look at oscillator replacement parts like the ICS525-01R.
www.icst.com
www.nuhorizons.com
For $2.50 it will give you a programmable clock up to 160 MHz and you have you dlls available as
zero delay buffers.
(Don't worry about the SMT package: Just solder it to the board :-)
CU,
Kolja
Jim Granville wrote:
> Mark Raviola wrote:
> >
> > Hello,
> > I am trying to source an EXTERNAL 25 MHz oscillator that can feed into a Spartan 2 device. This will pass trough 2 DLLs to obtain an output frequency of 100 MHz.
> > XAPP174 (page 8) states than any 100PPM quartz crystall oscilator can be used but the catch is the cycle to cycle jitter of 300 ps.
>
> Mark,
> Did you try one and have it fail, or does the 300ps sound daunting ?
>
> You can get a feel for jitter, and power supply tolerance, with some
> maths, on
> the XTAL sine wave, before it is squared up.
>
> 25Mhz is 20nS/half period, and if we take a 3V peak, thats a slew of
> ~3000mV/20ns
> or 150mV/nS.
> Put another way, a 45mV change on the sine threshold, is 300pS, so
> that's
> the order of uncertainty you need to be under.
>
> Std CMOS inverter gates commonly found in Oscillators have stable
> thresholds ( < 1mV cycle-cycle), but very poor Power supply rejection,
> so you need to ensure your OSC supply is clean ( << 45mV of peak noise
> )
>
> So a separate regulator (or good filter) for the OSC is sounding like
> a good idea, but any Osc module should do.
>
> -jg
Article: 30237Yes, I am working hard writing codes. I bought those books for a bunch of other people But right now that project is on hold. I still want to get my hands on the other books. :-) Please help. I have two copies of the one I listed. Aldec tutorial is cool isn't it ? :-) "Ray Andraka" <ray@andraka.com> wrote in message news:3AC2B5E3.EC7EB03A@andraka.com... > Wow, by the time you get through all those VHDL books, you could have been on > your 3rd or 4th design learning by doing and became an expert. Your first VHDL > design, and probably the second will be best used as liners for the kitty litter > pan no matter how much reading you do. You learn what really works in practice > by making the mistakes. Of course it helps if you have someone else's code to > look at too, but make sure you are not looking at someone else's cat box when > you do. For the amount you spend on the books you probably could have picked up > the Aldec tools (which have the best on-line references and tutorials I've ever > seen) and played with the real thing. ANyway, you've got a pretty impressive > library ammassed there. I'm not sure I'd trade away the Ashenden for any of > your "must haves" though. > > Compilit wrote: > > > > I have some EE books for trade. I am in the San Francisco Area. > > > > These all are all in brand new, unnused condition. Some have CD-ROM's > > included that are not yet opened. > > I bought them for a project now currently on hold. > > > > Please search www.abebooks.com or www.powells.com or www.Amazon.com for good > > deals on these, and get back to me. Please help me to get the books I need. > > > > The following list are what I currently have extra to be given away: > > > > 1/ Designer's Guide to VHDL by Peter Ashenden > > http://www.amazon.com/exec/obidos/ASIN/1558602704/qid=985827963/sr=1-3/ref=s > > c_b_4/002-1116465-7214451 > > 2/ VHDL Analysis and Modeling of Digital systems 2ed by Navabi > > > > 3/ Computer Architechiture, and Quantitative Approach. > > > > 4/ Verilog Digital Computer Design. Algorithms into Hardware by Arnold > > > > 5/ Real World FPGA Design with Verilog by Ken Coffman > > > > 6/ VHDL Representation and Synthesis by Armstrong and Gary > > > > 7/ VHDL made easy by Tellering and Taylor > > > > 8/ Verilog HDL by Palnitkar > > > > 9/ Verilog Designer's Library by Zeidman > > > > 10/ Timing Verification (ASIC) by Farzd Nekoogar > > http://www.amazon.com/exec/obidos/ASIN/0137943482/ref=sim_books/002-1116465- > > 7214451 > > > > 11/ VHDL by Douglas Perry > > > > 12/ VHDL for programmable logic by Kevin Skahill > > > > 13/ Real Time Signal Processing John G. Ackenhusen > > http://www.amazon.com/exec/obidos/ASIN/0136317715/qid=985827868/sr=1-2/ref=s > > c_b_3/002-1116465-7214451 > > > > 14/ Object Oriented Perl by Conway > > > > 15/ Programming and Customizing PIC controller Predro > > > > 16/ PCI-X System Architecture Mindshare INC > > > > 17/ Application-Specific Integrated Circuits. By Smith > > > > 18/ VHDL for Logic Synthesis by Andrew Rushton > > http://www.amazon.com/exec/obidos/search-handle-form/002-1116465-7214451 > > > > ===================================================================== > > > > The following are what I am in desparate need for, I don't mind them in used > > conditions: > > > > 1/ > > http://www.amazon.com/exec/obidos/ASIN/0792377664/ref=ase_janickbergershom/0 > > 02-1116465-7214451 > > Writing Testbenches - Functional Verification of HDL Models > > by Janick Bergeron > > > > 2/ System-on-a-Chip Verification - Methodology and Techniques > > http://www.amazon.com/exec/obidos/ASIN/0792372794/qid=985827145/sr=1-4/ref=s > > c_b_5/002-1116465-7214451 > > > > 3/ Rajsuman, Rochit SYSTEM ON A CHIP DESIGN AND TEST > > http://dogbert.abebooks.com/abe/BookDetails?bi=75782617 > > > > 4/Keating, Michael and Pierre Bricaud Reuse Methodology Manual For > > System-On-A-Chip Designs > > http://dogbert.abebooks.com/abe/BookDetails?bi=53348445 > > > > 5/HDL chip design :a practical guide for designing, synthesizing, and > > simulating ASICs and FPGAs using VHDL or Verilog > > > > http://www.powells.com/cgi-bin/biblio?inkey=2-0965193438-0 > > > > 6/PRINCIPLES OF VERILOG PLI > > by Swapnajit Mittra > > http://www.powells.com/cgi-bin/biblio?inkey=4-0792384776-0 > > > > 7/VHDL Coding and Logic Synthesis with Synopsys by Weng Fook Lee > > http://www.amazon.com/exec/obidos/ASIN/0124406513/qid=985827963/sr=1-6/ref=s > > c_b_7/002-1116465-7214451 > > > > 8/Vhdl Coding Styles and Methodologies by Ben Cohen must be 2nd edition > > http://dogbert.abebooks.com/abe/BookDetails?bi=52919198 > > > > 9/Cohen, Ben VHDL ANSWERS TO FREQUENTLY ASKED QUESTION 2nd edition > > http://dogbert.abebooks.com/abe/BookDetails?bi=55220448 > > > > 10/Component Design by Example : a Step-by-Step Process Using VHDL with UART > > as Vehicle > > by Ben Cohen > > > > Thank you, > > Peace. > > > > Please click reply to email me. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 30238
I don't use Quartus, but I have products that use FlexLM. I'm not sure this information will help, but it might.... ipconfig /all gives addresses for both NICs and modems. Ignore the modem entries. Modem entries will carry a description of "PPP Adapter." My NIC is a 3Com card and this is displayed in its description field. The address you want is the physical address. It will be shown as a series of six 2-digit numbers separated by dashes. When using FlexLM, remove the dashes. For example: 00-01-45-44-84-32 becomes 000145448432. Your NICs physical address should never change - it is hard coded in your NIC. Good luck! On Thu, 29 Mar 2001 05:13:12 +0200, "C.Schlehaus" <carlhermann.schlehaus@t-online.de> wrote: >Hi, >I've problems with determining which NIC to use for Quartus licensing, >as I get one NIC by ipconfig /all in DOS box, but three (!) NICs with >HostIDs tab in FlexLM License manager. I have a Win2K Professional >system with only one Ethernet card installed, thus I thought I should >have only one NIC. >Unfortunately Quartus seems to use the first NIC FlexLM offers, thus >it's not the ipconfig'd NIC. >More than this, the first two NICs are changing when the PC is restarted, >thus I didn't have any chance to switch the license. > >Does anyone got similar problems fixed? > >TIA, Carlhermann Schlehaus > mchampion@Xbigfoot.com (remove the X to send me email)Article: 30239
Dies ist eine mehrteilige Nachricht im MIME-Format. --------------AB1A9BF9271D271236B40AFF Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Hi Gurus, I'm looking for possibilities to encrypt my fpga bitstream. Exist there any fpga architectures, which support this feature? I've read the thread "Encryption is supported in new Virtex II but....." starting 24.01.01 I did not completely understand the topic they discussed. Can anybody tell me more about loading encrypted designs into fpga's. thanks Ralf Oberländer --------------AB1A9BF9271D271236B40AFF Content-Type: text/x-vcard; charset=us-ascii; name="ralf.oberlaender.vcf" Content-Transfer-Encoding: 7bit Content-Description: Visitenkarte für Ralf Oberländer Content-Disposition: attachment; filename="ralf.oberlaender.vcf" begin:vcard n:Oberländer;Ralf tel;fax:++49 3677 6682-59 tel;work:++49 3677 6682-57 x-mozilla-html:FALSE org:Emsys GmbH adr:;;Ehrenberg Str. 11;Ilmenau;;98693;Germany version:2.1 email;internet:ralf.oberlaender@emsys.de title:Dipl. Ing. fn:Ralf Oberländer end:vcard --------------AB1A9BF9271D271236B40AFF--Article: 30240
Programmable Logic can be used to control the "timing sequence" of either internally or externally connected devices. I've created a web page at: http://www.Twyman.org.uk/PL-Sequencer that explains a simple method using "Intellectual Property Level Design", where you only specify the functionality not actually how it's implemented. ---------- Harvey Twyman About Me: http://www.Twyman.org.uk/CV ---------- __________________________________________________ Do You Yahoo!? Get email at your own domain with Yahoo! Mail. http://personal.mail.yahoo.com/?.refer=text -- Posted from web3505.mail.yahoo.com [204.71.203.72] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 30241
Hello. I believe that the Xilinx Foundation 3.1i timing simulation sofware shows me the maximum (worst-case) delay, but is there an easy way to determine the *minimum*, and if possible the *typical* room-temperature propagation delay of: * GCK to I/O (/4 clock divider using IBUF, Q1 of a CB4 and OBUF) (shows 10.3 ns max) * I/O to I/O (data path thru IBUF, M16_1E mux and OBUFT) (shows 15.5 ns max) For a fitted design almost filling an XC95144XL-10TQ100I CPLD? It would be good for the software to show the min,typ,max time delays in some way in the waveform viewer!!! TIA, Paul. p a u l t @ t r x - technology_._com (remove all spaces and underscores!)Article: 30242
> I've created a web page at: > > http://www.Twyman.org.uk/PL-Sequencer Did anyone else go read this and come away a little 'miffed'? I don't quite get what it is supposed to be saying... It starts out somewhat claiming these are new techniques, but it describes techniques that have been used for at least the past 25 years...and goes on to talk about timing problems and pipelining and Harvard Architectures...and timing specifications...but completely incorrectly. I don't really want to chew it up and spit it out...but it seems like it's got a ton of misinformation and misunderstanding in it, and this is how this kind of misinformation gets propagated... I think this guy's a teacher...Article: 30243
Ralf Oberländer ha scritto nel messaggio <3AC304DC.A5D2DC64@emsys.de>... >Hi Gurus, > >I'm looking for possibilities to encrypt my fpga bitstream. Exist there >any fpga architectures, which support this feature? >I've read the thread "Encryption is supported in new Virtex II but....." >starting 24.01.01 >I did not completely understand the topic they discussed. Can anybody >tell me more about loading encrypted designs into fpga's. >From the Virtex II handbook: "Virtex-II devices have an on-chip decryptor that can be enabled to make the configuration bitstream (and thus the whole logic design) secure.The user can encrypt the bitstream in the Xilinx software,and the Virtex-II chip then perform the reverse operation,decrypting the incoming bitstream, and internally recreating the intended configuration. This method provides a very high degree of design security.Without knowledge of the encryption/decryption key or keys,potential pirates cannot use the externally intercepted bitstream to analyze,or even to clone the design.System manufacturer can be sure that their Virtex-II implemented design cannot be copied and reverse engineered.Also, IP Virtex-II chips that contain the correct decryption key. The Virtex-II devices store the internal decryption keys in a few hundred bits of dedicated RAM,backed up by a small externally connected battery. At <100 nA load,the endurance of the battery is only limited by its shelf life." IMHO, this method is secure, but I belive the presence of a battery lowers the overall system reliability. It would be better to use a public key cryptosystem, with the keys stored on a ROM inside the FPGA chip. LuigiArticle: 30244
Not all newsgroup users are experts. I didn't check the details but I like the passionate design of the site. MichaelArticle: 30245
Mark, The specification of 300 ps is for cycle to cylce jitter, not total peak to peak period jitter. That is, the edge to next edge variation must be less than the 300 ps (in LF mode). I have found this to be extremely robust, and practically all crystal oscillators meet this specification. If this was a period specification, it would be much more difficult (smallest period to largest period). We just buy oscillators out of the DigiKey catalog! Of course, if you want to have a low jitter clock for some other reason (like the application needs it), you must start with a higher quality oscillator. Most oscillators only specify the RMS jitter, so it is hard to convert these numbers. RMS measures of typical packaged oscillators runs less than 10 ps, with the peak to peak period jitter being about 35 to 65 ps, and the cycle to cycle jitter being about 20 to 40 ps. A really cheap packaged oscillator might have 100 ps P-P period, and ~50 ps P-P cycle jitter, and ~15 ps RMS jitter. Count on adding another 100 ps to the jitter when everything else on the board (in the real world) starts running. Of more concern is if you have done the correct signal integrity engineering to get the clock into the device without reflections or ground bounce (both add jitter). A small 22 ohm resistor at the oscillator effectively series terminates most small packaged 3.3 Vdc oscillators. Decoupling the oscillator itself with a ferrite bead and a capacitor is also good practive if the resulting clock also is desired to have low jitter for other reasons. Although all of the above measurements are not done this way. We have often found test bench pulse generators to gave > 300 ps cycle to cycle jitter, and to cause the DLL to loose lock. This may be because some pulse generators are more focused on providing variable pulse heights, widths, and delays, and providing a good clock signal is secondary to their purpose. Austin Mark Raviola wrote: > Hello, <br> > <br> > I am trying to source an EXTERNAL 25 MHz oscillator that can feed into a Spartan 2 device. This will pass trough 2 DLLs to obtain an output frequency of 100 MHz. <br> > <br> > XAPP174 (page 8) states than any 100PPM quartz crystall oscilator can be used but the catch is the cycle to cycle jitter of 300 ps. <br> > <br> > Can any body recommend a 25MHz Oscillator that meets the cycle to cycle jitter spec in the SPARTAN 2 datasheet. <br> > <br> > Both the Spartan2 Datasheet and XAPP174 do not have any recommendation for oscillator brands or part numbers that meet these specs <br> <br> > ( http://www.support.xilinx.com/xapp/xapp174.pdf ) <br> > <br> > Will Xilinx in the future provide any recommendations for external oscillators on their datasheets or app notes. This would save a lot of time and confusion. <br> > <br> > ThankyouArticle: 30246
luigi funes wrote: > The Virtex-II devices store the internal decryption keys in a few hundred > bits of dedicated RAM,backed up by a small externally connected battery. > At <100 nA load,the endurance of the battery is only limited by its shelf > life." > > IMHO, this method is secure, but I belive the presence of a battery > lowers the overall system reliability. It would be better to use a public > key cryptosystem, with the keys stored on a ROM inside the FPGA > chip. > Thank you, Luigi, for the explanation (quote ). The external battery is a necessity, since the CMOS logic process used for all FPGAs ( except antifuse ones ) is volatile, i.e. it loses all variable data when power is removed. We saw no other possibility to store the key but an internal RAM, backed up by a battery. Battery capacity is not an issue, but shelf-life is. Use a good Lithium battery, and it should be ok for 10 to 15 years. And yes, you can replace the battery without any complications, while as Vcc is present. There was a recent thread on his ng about battery reliability. Peter Alfke, Xilinx ApplicationsArticle: 30247
Here is the deal with test vector generation: it's not as hard as you may think but
it takes a bit of work.
First, make the distinction between formal test vectors and HDL generated test
vector modules/entities. If you are using a HDL such as Verilog or VHDL you can
create other modules (Verilog) or entities (VHDL) which provide a stimulus to your
design. For example, in Verilog this would be a file with an "always" statement
describing a clock.
module clock_gen(clock);
output clock;
reg clock;
always @(posedge clock) #20 clock <= ~clock;
endmodule
The above creates a clock with a period of 40 "units". This does not explicitly
call out a series of ones and zeros sequenced to act a a clock reference but that
is the result.
On the other hand, a formal test vector file is vertically oriented and is
expressed as a series of ones and zeros:
s s
c i i
l g g
k 1 2
----------
0 x x
1 1 0
0 1 0
1 0 0
0 0 1
1 1 1
Etc.
Take some scripting language, like Tcl or Perl or Python etc, which uses "regular
expressions", and create your own test vector file in whichever format you choose.
Some simulators work with .VEC files (VHDL format) and others work with .VER files
(Verilog format) while still other have their own format. The formats are easy to
generate once you have learned how to use a scripting language. Of course, you
could use C or C++ but neither of these systems programming languages have regular
expression libraries, and regular expressions are very useful when
extracting/formatting data or text.
A common trick is to use a mathematical language like Matlab or C/C++ to generate
data points (of any kind). Then use the scripting language (of your choice) to read
the Matlab data file and translate the output to whichever format you require.
Hope this helps.
Tom Cipollone
tomcip@concentric.net
tom_systek@msn.com wrote:
> Does anyone know of test vector generation free- or shareware?
>
> Thanks.
>
> ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web -----
> http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups
> NewsOne.Net prohibits users from posting spam. If this or other posts
> made through NewsOne.Net violate posting guidelines, email abuse@newsone.net
tom_systek@msn.com wrote:
> Does anyone know of test vector generation free- or shareware?
>
> Thanks.
>
> ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web -----
> http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups
> NewsOne.Net prohibits users from posting spam. If this or other posts
> made through NewsOne.Net violate posting guidelines, email abuse@newsone.net
Article: 30248More importantly: PCI-X has no reads (which are sloooowww), but only writes: therefore all PCI-X devices must be able to become bus master. To get information, you "write" to the "slave" give me some data and the slave then "writes" to the "master" "here is your data" No retries anymore.... Mark Austin Franklin wrote: > > > Could someone enlighten me ? Is PCI-X just a clock speed uprated 66MHz PCI > > or are there any fundamental differences ? As far as I can see the only > > significant change is to allow split cycles. > > It's basically registered. More clock cycles for control, but given it can > support much higher clock rates, it's faster.Article: 30249
I am an expert board designer/FPGA engineer but I only take on contract work since I can not live in the Silicon Valley. If you are interested I will send a resume. Tom Cipollone tomcip@concentric.net Cynthia Victor wrote: > Hi, > I want to know if there are any expert Board Designers/FPGA Engineers out > there, looking for a job? > If you are out there , please email me at cvictor@cachevision.com. > Cynthia > > -- > Posted from un.cachevision.com [63.150.36.35] > via Mailgate.ORG Server - http://www.Mailgate.ORG
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z