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Don't work so hard! Less than 50 ps of RMS jitter is an enormous budget! There are very few oscillators that are that bad! Any LVCMOS packaged oscillator will have typically 50 ps peak to peak jitter, and around 6 to 10 ps RMS jitter. It is OK to leave any unused IO pin unconnected. Kolja Sulimma wrote: > Hello all, > > I have two questions regarding Xilinx Spartan-II I/O. > > 1. Abuse of VRef as differential input. > > I need one high quality low jitter input clock. (<50ps RMS Jitter) > I found a couple of Clock Synthesizers with PECL outputs that have a RMS > jitter down to 2.6ps. > Now I am wondering how to interface PECL to a Spartan-II. > Of course I could buy a PECL to CMOS converter. I could also use > Virtex-II or Virtex-E but engineering > is the art of building what you need with what you have, therefore I > woul like to know: > > - could I set the VRef to 2.8V and use one of the PECL signals as single > ended clock input? (2.3V to 3.3V signal) > - could I connect VRef of one bank to the inverted CLK signal and GCLK > to the positive CLK signal an get a > differential input as aresult? (If have a lot of unused I/O and can > spare a bank) > > 2. Unused VCCO > > I am using a PQ208 Package where the VCCO of all banks are internaly > tied together. > However I am only using the outputs of two of the I/O banks. Is it > sufficient to externaly connect VCCO of these two banks and leave the > unused banks externaly unconnected to simplify the layout? > > Thanks in advance, > > KoljaArticle: 29951
Kolja Sulimma wrote: > > Chris Dunlap wrote: > > > You can always look in FPGA editor. Nothing can be left out there. If its > > routed or routable, its there. > > Sure it can be. > Or can you used the mysterious undocumented IRDY/TRDY pins special features of > Spartan-II in FPGA editor? That's in there. In fact, going through the FPGA editor is the only way you can get at the IRDY/TRDY feature. Look on the right and left edges about half way down (in the FPGA editor). You'll see the IRDY/TRDY boxes there. And, yes, you can use the FPGA editor to connect those up. -- Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 29952
Use timing constraints. Unless the rest of the design is dense, you'll probably make 100 Mhz without doing anything more. If not, then you can try floorplanning it or looking a little closer at your implementation. I think the way you've described the circuit is going to generate 4 layers of logic not counting the carry chain. The decode of that one read address is probably going to be done in two levels of combinatorial logic. If you can change your counter to a downcount that gets loaded with one of two values, you'll get a tighter implementation (that way you can use the carry out of the counter's carry chain to trigger a reload, and if you register that carry out you can get 150+ MHz even in the virtex -4. Bottom line is look at the virtex structure to tailor your circuit to work with the architecture if you want the highest performance. MANJUNATHAN wrote: > > Hello everybody !!! > > I need to know how to place and route the design given below. > > the code shown below has to work in 100 mz.but when i synthesized this with xilinx foundation series 2.1 it showed me 32 mz. when i synthesized the same code again it showed me 40 mz working fenquency. > why this difference ? is it possible it to make 100 mz. > > is it possible to place and route the design in virtex device such that its working frequency is > 100 mz. > > the code is > > LIBRARY IEEE ; > USE IEEE.STD_LOGIC_1164.ALL; > USE IEEE.STD_LOGIC_UNSIGNED.ALL ; > > ENTITY ADDRESS_GENERATOR is > > port ( > > sfp : in std_logic ; > clk : in std_logic ; > reset : in std_logic ; > > READ_address : out std_logic_vector(10 downto 0) > ); > END ADDRESS_GENERATOR ; > > > ARCHITECTURE BEHAV OF ADDRESS_GENERATOR IS > > signal read_address_s : std_logic_vector(10 downto 0); > > begin > > > process(clk,reset) > > begin > > > if reset='1' then > read_address_s <= (others => '0' ) ; > > elsif clk='1' and clk'event then > > > > if sfp='1' then > > read_address_s <= "00000011000" ; > > elsif read_address_s ="10000110111" then > read_address_s <= (others => '0') ; > > else > read_address_s <= read_address_s + 1 ; > > end if ; > > > > > end if ; > > > > end process ; > read_address <= read_address_s ; > end behav ; > > > configuration cfg_address_generator_behav of address_generator is > for behav > > end for ; > > > > > end cfg_address_generator_behav; > > is there any material or web sites how to place and route the design in to the virtex device such that its working frency is very high. > > thanx in advance > > regards > Manjunathan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 29953
This is a multi-part message in MIME format.
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Hello David,
Sounds like a homework assignment but I will help out, just in case
it is not. The sysclk/2 is easy enough in a DLL or DCM if you are
targeting a Virtex-derivative or Spartan-II. Switching between two
outputs is a simple MUX function. The only thing here of slight
complication is the 2's compliment function and you are in luck as I have
some VHDL code lying around if you are targeting the above devices. I
created some structural code a while back implementing a 2's compliment
function in the carry chain the Virtex architecture. It is fairly fast
and area efficient so it should work for most situations. It has been a
while since I have played with it but should work properly however I
would definitely test it to be sure it suits your needs as it does not
come with any guarantees or warranties. Right now it is setup for a
ten-bit operator but that can easily be modified by changing the
"data_width" generic in the code. This should be a good starting place
for you.
The code is attached. Enjoy.
-- Brian
David Nyarko wrote:
> Hi,
> Any leads on VHDL code to implement the following system:
>
> Inputs
> Inputseq: A sequence of standard logic vector elements each of the
> same width representing 2's complement inputs typically 16-bits wide.
>
> clock: sysclk
>
> Each input sequence element is clocked in on the rising edge of
> sysclk.
>
> Outputs:
> outputA: same size and type as input
> outputB: same size and type as input
> outclock: sysclk/2
>
> Assuming the input sequence elements are represented as:
>
> x0,x1,x2,x3,x4,x5,x6,x7...
>
> The desired output elements should be:
>
> outputA: x0,-x2,x4,-x6,x8,...
> outputB: x1,-x3,x5,-x7,x9,.
>
> The outputs are at half the input rate and should
> appear at the same time (i.e x0 and x1 , -x2 and -x3 etc...)
> The output clock (outclock) will be used the clock
> the next processing stage whose inputs will
> be outputA and outputB.
>
> David
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Article: 29954Frode, Maybe you have a look at www.mpeg.org mpeg is video compression and is used a lot. Only MPEG2 is available in hardcore?? meaning can be put in FPFA/ASIC .you have to wait a while if yoy want mpeg4 and 7 in FPGA. regards ron proveniers Frode Vatvedt Fjeld <frodef@acm.org> schreef in berichtnieuws 2helvugmaa.fsf@dslab7.cs.uit.no... > Does anyone know of any texts concerning implementing digital video > coding (compression, DCT etc.) on FPGAs? > > Thanks, > -- > Frode Vatvedt FjeldArticle: 29955
I am using Xlinix Foundation 2.1li I met this problem FPGA Express 2.x, 3.x - Cannot Export netlist from Synopsys - For unknown reasons the operation could not be completed. I searched at website and got answer Solution 1: Check to see if you have identical assignment statements in your code. Comment out or delete one of these statements, and you will be able to export the netlist. This error has also been seen to be a result of a lack of memory. Solution 2: Check the license file. Is it for STD or BAS? Make sure that the user is licensed for Synopsys. Solution 1 could not solve my problem I have no idea how to do with solution 2, do you have some good ideas? Thanks a lot!Article: 29956
Does anyone know of any texts or references concerning implementing TOA (time of arrival) measurement of the radar signal on FPGA or DSP chips? Thanks, MichalArticle: 29957
Peter Alfke schrieb: > > termination ) Every feature of the larger parts, even the 16 global clocks > with glitch-free input muxes, is available in the tiny XC2V40. Stop me, I > just came back from a seminar tour... ;-))))) -- MFG FalkArticle: 29958
Hi, I'm developing a embedded system, which uses a FPGA. Currently I'm writing VHDL code for it. When I've written a part of the code, I simulate it in ModelSim. Now is my question: how reliable is ModelSim when you use a Xilinx FPGA? I'm asking this because my simulation results are OK, but when I implement (using Synplify an the Xilinx Design Manager) my design (DONE signal becomes high after programming), it doesn't work the way I simulated it. How is this possible? For example, I implemented a simple clock divider to see if my FPGA is working correctly. When I only implement this clock divider (by 4 from a 33MHz. clock) it works, but when I a add some other features (an adresdecoder and a 16 bit register) it doesn't work anymore (the output of the clock divider stays low!). I really don't know what's wrong. I also took a look at the technology view within Synplify and it seems to me that it is OK. Could my FPGA be broken (we soldered the FPGA on the PCB our selves)? The FPGA also doesn't support reprogramming (after INIT has been pulled low for several u-seconds DONE should become high, but it doesn't!). I'm using a Xilinx SpartanXL XCS30 PQ208 package FPGA. Regards, JurjenArticle: 29959
Wow, it really is there. You do not happen to know its functionality? I assumed it would have something to do with pulling up the outputs at the end of the access within the time spec (I found that hard to implement) but it connects to the output clock enables. One could create a hard macro and instantiate it in VHDL, right? Kolja Sulimma Ray Andraka wrote: > Kolja Sulimma wrote: > > Chris Dunlap wrote: > > > You can always look in FPGA editor. Nothing can be left out there. If its > > > routed or routable, its there. > > > > Sure it can be. > > Or can you used the mysterious undocumented IRDY/TRDY pins special features of > > Spartan-II in FPGA editor? > > That's in there. In fact, going through the FPGA editor is the only way you can > get at the IRDY/TRDY feature. Look on the right and left edges about half way > down (in the FPGA editor). You'll see the IRDY/TRDY boxes there. And, yes, you > can use the FPGA editor to connect those up. > > -- > Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 29960
Can you describe the rwquirements in more detail?
Is it just delay measurement with high resolution?
What resolution do you need? And how many channels?
CU,
Kolja Sulimma
Michal Kvasnicka wrote:
> Does anyone know of any texts or references concerning implementing TOA
> (time of arrival) measurement of the radar signal on FPGA or DSP chips?
>
> Thanks,
>
> Michal
Article: 29961Does anyone know of any work to implement unsupervised ANNs in FPGAs available on the web? Thanks ChrisArticle: 29962
Austin Lesea wrote: > Don't work so hard! People keep telling me that ;-) > Less than 50 ps of RMS jitter is an enormous budget! There are very few > oscillators that are that bad! Any LVCMOS packaged oscillator will have > typically 50 ps peak to peak jitter, and around 6 to 10 ps RMS jitter. Sorry, I did not provide all the information: I need something around 200Mhz. I did not find oscillators for that frequency range. If you have a source for 200MHz oscillators, please tell me. That would save me a couple of hours. But there are a couple of clock synthesizers. Most of them - like ICS525 - have something like 200ps to 300ps peak to peak jitter. The Spartan DLL for example adds 60ps jitter to the input jitter. I only found PECL synthesizers meeting the spec. > It is OK to leave any unused IO pin unconnected. How about the VCCO of unused I/O banks? Thanks, Kolja > > I need one high quality low jitter input clock. (<50ps RMS Jitter) > > I found a couple of Clock Synthesizers with PECL outputs that have a RMS > > jitter down to 2.6ps. > > - could I set the VRef to 2.8V and use one of the PECL signals as single > > ended clock input? (2.3V to 3.3V signal) > > - could I connect VRef of one bank to the inverted CLK signal and GCLK > > to the positive CLK signal an get a > > differential input as aresult? (If have a lot of unused I/O and can > > spare a bank) > > > > 2. Unused VCCO > > > > I am using a PQ208 Package where the VCCO of all banks are internaly > > tied together. > > However I am only using the outputs of two of the I/O banks. Is it > > sufficient to externaly connect VCCO of these two banks and leave the > > unused banks externaly unconnected to simplify the layout?Article: 29963
Rick Collins wrote: > So if the XC2V40 and XC2V1000 parts were available > now and I had some reason to believe that I could get them at reasonable > prices by the point of production (like a quote) I would love to design > them in. Consider them available, and - in your time frame- the XC2V3000 also. > But one thing I forgot was that I need to interface to a 5 > volt PC/104 bus. The 5 volt IO would make the design much more > complex. > I would have to add another power rail for an XC2S part or add many > buffer parts. Neither one is very workable. Well, people are doing it. It's the "price of progress"... > > > I seem to remember that one of the V parts was 5 volt TTL compatible if > you added series resistors to limit the current. But that would mean > some 90+ extra resistors on the board! But it might work. Will the XC2V > work this way? That's true of XC2V as well as XCV-E. There is a diode to Vccio on each pin ( as ESD protection). That diode clamps at 0.7 V above Vccio, i.e. at 4.0V, assuming 3.3 V Vccio. If you have to drive 5-V stuff, you only go to Vccio, which, worst case, could be as low as 3.0V. If you receive something from 5-V logic, ( I call that "grandfather logic" ) it depends on the driving structure. You should be ok if the driver is a totem-pole ( n-channel pull-up and pull-down), but you need a current-limiting resistor if the 5-V driver is complementary, rail-to-rail. BTW, word is that the start-up current on Spartan-II is being improved, and the current is now kind-of proportional to size (i.e. part number). So the small 15 and 30 spartan-II devices have a low start-up current. > > > BTW, how can the part be PCI compliant without being 5 volt tolerant? Is > it only 3 volt PCI compliant? Yes. Peter Alfke, Xilinx ApplicationsArticle: 29964
I get the following error message when trying to configure a 10K10: 'SRAM load unsuccessful'. I'm using version 8.1 of MAX+PlusII and a BitBlaster download cable. It seems to pause right at the end of the config process. Any ideas?Article: 29965
"Tricia Dolkas, aka Technoyenta" wrote: > Boy, I sure hope that I don't upset anyone by asking if there is interest in > my job posting! I am looking for a HW engineer for one of my favorite > clients in Silicaon Valley. Just where, exactly, is the "Silicaon" Valley? ;-) . Sounds like some far away island where the "livin" is easy. I sure hope that you don't mean the "Silicon Valley" in California, where a salary of $120k would not allow you to live in a garage attached to a dog house in beautiful Milpitas. Yes, please tell me where the Silicaon Valley is and I will apply for the job. (I apologize for bring a pain in the you-know-what but someone has to do it). Regards Tom > Take a look at the description!! > > If you are interested, shoot me an email so that I can call you and we can > discuss the position. Please only contact me if you are a citizen or perm > resident of the USA and you have experience in most of what they are asking > for. > > (Salary is in the range of $100 - $120k. Great benefits and a great working > environment. People who get a chance to work at this company LOVE it and > never want to leave!) > > JOB REQUIREMENTS: 5 years of experience that includes 1)Lots of Embedded > System Design (FPGA, ASIC and Micro controller firmware); 2) EMI issue > resolution (including analog design skills with A/D and D/A); 3)High-volume > product development experience that covers the complete life cycle; 4) > Understanding of mechanical packaging design; 5) Power issues including > low-cost power supplies, International power standards and connecting to an > AC main.) > > Tricia Dolkas > (650)964-6644 x126 > tricia@lrc.comArticle: 29966
Ray Andraka <ray@andraka.com> writes:
> Jan Gray wrote:
> >
> > But for V-II there seems to be no practical alternative but to a) use
> > (waste) LUTs and their interconnect to build these horizontal muxes, and/or
> > b) recode your design to help your technology mappers merge some of the
> > muxes into other logic.
>
> I haven't looked at it closely, but it seems to me that you might be able to use
> the horizontal OR chains for this. Have you investigated it?
I went quickly to the data sheet. If I get it correctly, there is only
one ORCY per slice (after the G MUXCY). So if you are using 4bits per
CLB row (given by carry logic) and want one horizontal mux per bit,
you have only 1/2 the needed ORCYs.
Dammit. Using LUTs as (F1-in&F2-enable)|(F3-in&F4-enable) and then
ORCYing them would have solved the problem. And LUTs with 3 inputs
for logic and one enable and ORCY would be ideal.
Xilinx: more ORCYs in Virtex-III, please.
> > Regarding (b), using the Virtex-style carry logic (including MULT_AND), it
> > seems possible to build these "free mux" structures:
> > 1) o[i] = addsub ? (a[i] + b[i]) : (a[i] - b[i])
> > 2) o[i] = add ? (a[i] + b[i]) : c[i]
> > 3) o[i] = addb ? (a[i] + b[i]) : (a[i] + c[i])
> > 4) o[i] = addsub ? (addand ? a[i]+b[i] : a[i]-b[i]) : (addand ? a[i]&b[i]
> > : a[i]^b[i])
Sorry, I do not speak Verilog. Here is my MUXCY based layout:
2input 4input 8input
7 67 4567 each digit is one LUT (F1&F2)|(F3&F4) + MUXCY OR
6 67 4567 digits number data path bit that is processed
5 45 4567 2x2 digits is a Virtex CLB
4 45 4567
3 23 0123
2 23 0123
1 01 0123
0 01 0123
Java/JBits code 4-enables type 4:1 Mux:
for (int Col = MuxCol; Col < MuxCol+2; Col++) {
for (int Row = MuxRow; Row < MuxRow+MuxBits/2; Row++) {
/* LUT AND OR AND, 1&2|3&4, 8888|F000 = F888 */
int Mux2i[] = Util.IntToIntArray(0xF888, 16);
Fpga.set(Row, Col, LUT.SLICE0_F, Util.InvertIntArray(Mux2i));
Fpga.set(Row, Col, LUT.SLICE0_G, Util.InvertIntArray(Mux2i));
/* wide OR with LUT=0 -> !BX (=0) and LUT=1 -> 1 */
Fpga.set(Row, Col, S0Control.XCarrySelect.XCarrySelect,
S0Control.XCarrySelect.LUT_CONTROL);
Fpga.set(Row, Col, S0Control.YCarrySelect.YCarrySelect,
S0Control.YCarrySelect.LUT_CONTROL);
Fpga.set(Row, Col, S0Control.AndMux.AndMux, S0Control.AndMux.ONE);
Fpga.set(Row, Col, S0Control.Cin.Cin, S0Control.Cin.BX);
Fpga.set(Row, Col, S0Control.BxInvert, S0Control.ON); } }
> > See http://www.fpgacpu.org/log/nov00.html#001112 for details.
I have already employed the jump/increment program counter trick with
the carry logic increment controlled by MUL-AND. Actually read about it
in November, forgot it, reinvented it, and now re-recognized it.
> > This add/mux inference digression aside, abundant TBUFs were useful and will
> > be missed. But I suppose that any FPGA feature that HDL synthesis users and
> > tools do not take good advantage of, is not long for this world.
So I suppose the line "Consequently, the Virtex routing archi-tecture
and its place-and-route software were defined in a single optimization
process" can be translated as: we the chip designers do not support
Assembler^WJBits fossils^Wprogrammers. :-(
--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/FH/BSc, Sysadmin, Roleplayer, LARPer
Article: 29967OK... From my point of view delay measurement needs two delayed signal which are compared in the TDE (time delay estimation) algorithm, but TOA measurement work only with one precisely sampled signal and any available additional apriory knowledge (pulse shape, noise model, etc.). Radar pulse can be approximated by trapezoidal (symmetric or asymmetric) pulse wit the following parameters: pulse width = 0.5 - 500us (50% amplitude level) rise time = 20-100ns fall time = 20-200ns sample interval = 1 - 10ns Pulse repetition interval = 1 - 5000us These pulses (pulse train) is contaminated by noise of the general form (colored nongaussian, spread spectrum, etc.) with low S/N ration (in many cases). Finally is represented by 1-channel data stream sampled by 1-10ns and with precise time stamping. Time sampling is realized by Rubidium normal (short term stability about 10^-12 ) connected with GPS time receiver for long term stability about 10^-13 - 10^-15. Required TOA accuracy is about 1-10ns. So, I need effective and robust TOA algorithm which can be realized on DSP or FPGA chip sufficiently fast (see PRI value ~ 1-5000us). Regards, Michal "Kolja Sulimma" <kolja@bnl.gov> píse v diskusním príspevku news:3AB65BBE.2055F00D@bnl.gov... > Can you describe the rwquirements in more detail? > Is it just delay measurement with high resolution? > What resolution do you need? And how many channels? > > CU, > Kolja Sulimma > > Michal Kvasnicka wrote: > > > Does anyone know of any texts or references concerning implementing TOA > > (time of arrival) measurement of the radar signal on FPGA or DSP chips? > > > > Thanks, > > > > Michal >Article: 29968
Hi, "Shareef Jalloq" <sjalloq@hotmail.com> schrieb im Newsbeitrag news:995p83$g4u$1@news8.svr.pol.co.uk... > I get the following error message when trying to configure a 10K10: 'SRAM > load unsuccessful'. I'm using version 8.1 of MAX+PlusII and a BitBlaster > download cable. It seems to pause right at the end of the config process. > Any ideas? That a sign, that the Conf_Done Signal (which is controlled by the 10K) isn't released (You need to have an external pull-Up as shown in the AN). The only question is, why the Conf_Done does not change to high state. You should check, that the Pull is connected an the suggested value. Then, You should check for the signal integrity of DCLK and DATA, as the 10K needs spike-free signals. HTH, CarlhermannArticle: 29969
If I interpret that correctly the main problem is that the noise on the
relativly slow rise time requires more sophisticated
processing of the data then just computing the center of the pulse or doing
something similar.
I guess in that case I can not help you designing an algorithm, but when you
find one, we can talk about the FPGA implementation.
In general for DSP on small fixed point data FPGA is a good choice.
CU,
Kolja
Michal Kvasnicka wrote:
> OK...
> From my point of view delay measurement needs two delayed signal which are
> compared in the TDE (time delay estimation) algorithm, but TOA measurement
> work only with one precisely sampled signal and any available additional
> apriory knowledge (pulse shape, noise model, etc.).
>
> Radar pulse can be approximated by trapezoidal (symmetric or asymmetric)
> pulse wit the following parameters:
> pulse width = 0.5 - 500us (50% amplitude level)
> rise time = 20-100ns
> fall time = 20-200ns
> sample interval = 1 - 10ns
> Pulse repetition interval = 1 - 5000us
>
> These pulses (pulse train) is contaminated by noise of the general form
> (colored nongaussian, spread spectrum, etc.) with low S/N ration (in many
> cases). Finally is represented by 1-channel data stream sampled by 1-10ns
> and with precise time stamping.
>
> Time sampling is realized by Rubidium normal (short term stability about
> 10^-12 ) connected with GPS time receiver for long term stability about
> 10^-13 - 10^-15.
>
> Required TOA accuracy is about 1-10ns.
>
> So, I need effective and robust TOA algorithm which can be realized on DSP
> or FPGA chip sufficiently fast (see PRI value ~ 1-5000us).
>
> Regards,
>
> Michal
>
> "Kolja Sulimma" <kolja@bnl.gov> píse v diskusním príspevku
> news:3AB65BBE.2055F00D@bnl.gov...
> > Can you describe the rwquirements in more detail?
> > Is it just delay measurement with high resolution?
> > What resolution do you need? And how many channels?
> >
> > CU,
> > Kolja Sulimma
> >
> > Michal Kvasnicka wrote:
> >
> > > Does anyone know of any texts or references concerning implementing TOA
> > > (time of arrival) measurement of the radar signal on FPGA or DSP chips?
> > >
> > > Thanks,
> > >
> > > Michal
> >
Article: 29970I agree, Oscillators above 100 MHz are hard to find because their IO has to be so much faster, and hence lvpecl seems to be the only kind available. I wish they made lvds oscillators. HSTL or SSTL compatible oscillators would also work, but I don't know if anyone makes them. All unused Vcco's should get tied to a Vcco supply. You could tie them to the Vccint supply (as 1.8 Volts is a valid Vcco for some IO families). I prefer wiring it to a 3.3 V supply in case I need to use an input or an output to troubleshoot my design. Austin Kolja Sulimma wrote: > Austin Lesea wrote: > > > Don't work so hard! > > People keep telling me that ;-) > > > Less than 50 ps of RMS jitter is an enormous budget! There are very few > > oscillators that are that bad! Any LVCMOS packaged oscillator will have > > typically 50 ps peak to peak jitter, and around 6 to 10 ps RMS jitter. > > Sorry, I did not provide all the information: I need something around 200Mhz. > I did not find > oscillators for that frequency range. If you have a source for 200MHz > oscillators, please tell me. > That would save me a couple of hours. > But there are a couple of clock synthesizers. Most of them - like ICS525 - > have something like > 200ps to 300ps peak to peak jitter. The Spartan DLL for example adds 60ps > jitter to the input jitter. > I only found PECL synthesizers meeting the spec. > > > It is OK to leave any unused IO pin unconnected. > > How about the VCCO of unused I/O banks? > > Thanks, > > Kolja > > > > I need one high quality low jitter input clock. (<50ps RMS Jitter) > > > I found a couple of Clock Synthesizers with PECL outputs that have a RMS > > > jitter down to 2.6ps. > > > - could I set the VRef to 2.8V and use one of the PECL signals as single > > > ended clock input? (2.3V to 3.3V signal) > > > - could I connect VRef of one bank to the inverted CLK signal and GCLK > > > to the positive CLK signal an get a > > > differential input as aresult? (If have a lot of unused I/O and can > > > spare a bank) > > > > > > 2. Unused VCCO > > > > > > I am using a PQ208 Package where the VCCO of all banks are internaly > > > tied together. > > > However I am only using the outputs of two of the I/O banks. Is it > > > sufficient to externaly connect VCCO of these two banks and leave the > > > unused banks externaly unconnected to simplify the layout?Article: 29971
Normally we have a reference to indicate the timing of the transmit pulse. Depending on the radr design, the reference may the leakage from the transmit pulse into the receiver, or it may be a digital signal from the transmitter that triggers a receive cycle. In a simplistic radar, the transmit sync pulse starts the capture of the echo (perhaps after a fixed delay). The position of the echo relative to the start trigger or the coupled in transmit pulse gives you your range information. You'll probably need some signal processing to clean up the pulse. Using a simple pulse is going to require a fairly high peak power, which in turn is going to limit your range. The power under your pulse is going to determine the range, and the width of your pulse is going to set your range resolution. You can get fancier if you can shape your transmit waveform for pulse compression. I'd suggest a good study of a radar text such as Brookner, Rader or Skolnik. The FPGA can handle 5-10 ns range gates fairly easily. Getting much shorter than that will require more specialized tricks or some high speed external logic. Michal Kvasnicka wrote: > > OK... > From my point of view delay measurement needs two delayed signal which are > compared in the TDE (time delay estimation) algorithm, but TOA measurement > work only with one precisely sampled signal and any available additional > apriory knowledge (pulse shape, noise model, etc.). > > Radar pulse can be approximated by trapezoidal (symmetric or asymmetric) > pulse wit the following parameters: > pulse width = 0.5 - 500us (50% amplitude level) > rise time = 20-100ns > fall time = 20-200ns > sample interval = 1 - 10ns > Pulse repetition interval = 1 - 5000us > > These pulses (pulse train) is contaminated by noise of the general form > (colored nongaussian, spread spectrum, etc.) with low S/N ration (in many > cases). Finally is represented by 1-channel data stream sampled by 1-10ns > and with precise time stamping. > > Time sampling is realized by Rubidium normal (short term stability about > 10^-12 ) connected with GPS time receiver for long term stability about > 10^-13 - 10^-15. > > Required TOA accuracy is about 1-10ns. > > So, I need effective and robust TOA algorithm which can be realized on DSP > or FPGA chip sufficiently fast (see PRI value ~ 1-5000us). > > Regards, > > Michal > > "Kolja Sulimma" <kolja@bnl.gov> píse v diskusním príspevku > news:3AB65BBE.2055F00D@bnl.gov... > > Can you describe the rwquirements in more detail? > > Is it just delay measurement with high resolution? > > What resolution do you need? And how many channels? > > > > CU, > > Kolja Sulimma > > > > Michal Kvasnicka wrote: > > > > > Does anyone know of any texts or references concerning implementing TOA > > > (time of arrival) measurement of the radar signal on FPGA or DSP chips? > > > > > > Thanks, > > > > > > Michal > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 29972
I've got the pull-up in place but I'm not sure about how clean the DCLK signal is. This is a Uni project and I've put the device on a piece of veroboard. How would I go about cleaning DCLK and DATA0? Thanks. "C.Schlehaus" <carlhermann.schlehaus@t-online.de> wrote in message news:9960b1$811$03$1@news.t-online.com... > Hi, > > "Shareef Jalloq" <sjalloq@hotmail.com> schrieb im Newsbeitrag > news:995p83$g4u$1@news8.svr.pol.co.uk... > > I get the following error message when trying to configure a 10K10: 'SRAM > > load unsuccessful'. I'm using version 8.1 of MAX+PlusII and a BitBlaster > > download cable. It seems to pause right at the end of the config process. > > Any ideas? > > That a sign, that the Conf_Done Signal (which is controlled by the 10K) > isn't released (You need to have an external pull-Up as shown in the > AN). > The only question is, why the Conf_Done does not change to high > state. You should check, that the Pull is connected an the suggested > value. > Then, You should check for the signal integrity of DCLK and DATA, > as the 10K needs spike-free signals. > > HTH, Carlhermann > >Article: 29973
I wrote: > WebPACK does NOT support the Virtex parts. The only FPGAs > WebPACK supports are the Spartan II and a single Virtex-E part, > the XCV300E. Nicolas Matringe <nicolas.matringe@IPricot.com> writes: > I was only talking about the Floorplanner: > > Floorplanner Guide > > Chapter 1: Introduction > > Supported Architectures > The Floorplanner supports all Xilinx architectures in the Spartan/-II™, > Virtex/-E/-II™, and XC4000™ device families. > > (quoted from the WebPACK help) Yes, and Floorplanner *does* support those devices --- IF you're running it from the full-blown Foundation software. But WebPACK doesn't, so they don't supply the necessary data files.Article: 29974
it is a 5 input ROM (combinatorial, not configurable). I had the contents about a year ago, but alas, I've misplaced the information. Fortunately you can easily discover the function with a trivial test circuit which you can wire using the FPGA editor. Kolja Sulimma wrote: > > Wow, it really is there. > You do not happen to know its functionality? > > I assumed it would have something to do with pulling up the outputs at the end of > the access within the time > spec (I found that hard to implement) but it connects to the output clock enables. > > One could create a hard macro and instantiate it in VHDL, right? > > Kolja Sulimma > > Ray Andraka wrote: > > > Kolja Sulimma wrote: > > > Chris Dunlap wrote: > > > > You can always look in FPGA editor. Nothing can be left out there. If its > > > > routed or routable, its there. > > > > > > Sure it can be. > > > Or can you used the mysterious undocumented IRDY/TRDY pins special features of > > > Spartan-II in FPGA editor? > > > > That's in there. In fact, going through the FPGA editor is the only way you can > > get at the IRDY/TRDY feature. Look on the right and left edges about half way > > down (in the FPGA editor). You'll see the IRDY/TRDY boxes there. And, yes, you > > can use the FPGA editor to connect those up. > > > > -- > > Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com
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