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Rick Filipkiewicz wrote: > Mark wrote: > > > Hi, > > > > Does anybody have any information on the expected availability of the Virtex > > II family, especially the 6000 part? > > Probably depends on who you work for. Let me explain something: For Xilinx engineering, it is very easy to create the subsequent mask sets for the different family members, it's fundamentally step-and-repeat. We can do that in a few weeks. But the fab still has to get the new process fine-tuned, and achieve the low defect density necessary for volume manufacturing the larger chips. You are asking us to push technolgy close to its limits, and that's what we and the fabs are doing. Tough jobs are done fast, miracles sometimes take a little longer... My guess for Virtex-II availability is '40, '1000, '3000, in that order, with the in-between sizes appearing very fast after, and the larger devices after that. For those of us who have been around awhile, it's "deja vu all over again". For detailed information ask the distributors. But some designers consider the DigiKey catalog the ultimate authority. :-) Peter AlfkeArticle: 29551
Andrew I have seen the occasional thread about Handel-C, how well did the Rijndael algorithm port to hardware using Handel-C? I'm a software engineer working on methods of increasing performance of web servers, the general bottleneck is when the server starts any secure transactions (OpenSSL blah blah..) I have seen products out there that are hardware encryption acceleration boards, these tend to be expensive and costly to maintain (e.g. when a new encryption algorithm is released) What would be really great would be for me to write my own implementation using a generic low cost platform. Will Handel-C enable me to do this?? Regards John (no spam please) "ajd" <ajadu76@hotmail.com> wrote in message news:3a9a3744$1@news.star.co.uk... > > I'm afraid I don't know much about DSP's. I implemeted Rijndael on a VirtexE > FPGA using the Handel-C language (I think its produced by Celoxica... > www.celoxica.com). It took me about a week to get it working, and another 2 > or three to optimise. Throughput was close to 3 Gbits/sec. > > Andrew > > <satish_me@my-deja.com> wrote: > > Hi, > > I seen your response for Rijndel implementation in FPGA. I want to just > know the statistical result on FPGA versus DSP of this algorithm. I need to > know How many blocks it occupied, whether key storage is on memory cells, > how much speed it can execute, memory consumption(cycles used).etc.. > > I am planning to run the same on TI -DSP > > If you have a data on these things please share with me > > Thanks in advance > > SATISH KUMAR > > Subject: Re: Rijndael > From: ajadu76@hotmail.com (ajadu76@hotmail.com) > > > I did it in a month. What FPGA part are you trying to put it on and what > memory do you have available? > > Andrew > > <tchoh@my-deja.com> wrote in message news:95m5li$j87$1@nnrp1.deja.com... > > > > > > Hi. > > > > I wondered if anyone out there had attempted to implement the new AES > > in an FPGA. > > > > If so, being new to the world of crytography, I wonder if you have any > > general tips/advice? > > > > Thanks. > > > > > >Article: 29552
In article <3A9939F4.DA703B2B@earthlink.net>, palfke@earthlink.net (Peter Alfke) wrote: > > > Steve Rencontre wrote: > > > We've been round this loop a number of times in the ng, without > > coming to > > any universal solution. The new Xilinx devices with built-in > > encryption > > seem very interesting from this POV, but they still aren't perfect for > > everybody. > > Perhaps "nothing is ever perfect for everybody", but if you know of a > specific issue that we should improve, or a feature we should add, > please let > me know. > Perfection is still our goal... Well, if you could add the "instant-on" non-volatility of antifuse or flash technologies, partial reconfiguration, add some tiny versions for when you just need a 22V10 kind of thing, give them away free... Oh, and the software should never have bugs, and it should compile a few million gates a second on an old '386, and it should solve world hunger and AIDS and war and... When you've done that, come back and ask what's next on the wishlist :-))) -- Steve Rencontre http://www.rsn-tech.co.uk //#include <disclaimer.h>Article: 29553
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3A9A9B54.AFDA5D52@xilinx.com... > Call it what you will. > > It is intended to aid those that have less than the 500 mA available. > > Initially, we thought, "anyone using this IC will probably run it at a clock speed, > and with enough IO's that 500 mA will be required for its normal operation." > Obviously, there is a smaller contingent of users that do not use the fast clock > rates, or the large drive strengths, and need to get by with 200 or so mA. For instance, USB 'bus-powered' applications.Article: 29554
Hi
I always have something wrong with my
case when I check syntax in xilinx
foundation
here is my brief program
the xilinx foundation says
" Expression must be the name of
an object whose subtype is locally
static, or it must be a qualified
expression or type conversion whose
type mark denote a locally static
subtype"
--LIBRARY ieee;
ENTITY PWM IS
generic( DATAWIDTH: INTEGER :=23;
ADDRWIDTH:...
PORT(
CLK: in STD_LOGIC;
RESET: in STD_LOGIC;
DATA: IN
STD_LOGIC_VECTOR(DATAWIDTH DOWNTO 0);
ADDR: IN
STD_LOGIC_VECTOR(ADDRWIDTH DOWNTO 0);
WAVE1: out STD_LOGIC;
WAVE2: out STD_LOGIC
);
END PWM;
ARCHITECTURE ver1 OF PWM IS
signal SWITCHING_F:
STD_LOGIC_VECTOR(DATAWIDTH downto 0);
BEGIN
REG: PROCESS(ADDR,DATA,CLK,RESET)
BEGIN
IF RESET='1' THEN
SWITCHING_F<=DATAZERO;
ELSIF CLK'EVENT AND CLK='1' THEN
CASE ADDR IS
WHEN "0000" => SWITCHING_F<=DATA;
END CASE;
END IF;
END PROCESS;
END ver1;
Article: 29555Hi, I think You cannot compare a vector whose bitwidth is configured by an generic but not static with a static bitwidth value. Just think, how You would get Problems to resolve if a 5 Bit vector (Generic Bitwidth set to 5) is "0000"... If You just want to resolve if ADDR is all zero, You could write IF ADDR = CONV_STD_LOGIC_VECTOR(0,Datawidth) THEN... OR CASE ADDR(3 DOWNTO 0) IS .... (You have to ensure, that Bitwidth > 4 for this expression) CU, CarlhermannArticle: 29556
Hi,
Here is C source for a Xilinx FPGA programmer for Linux 2.4+, using
the nice new ppdev parallel port driver.
- Reinoud
(Spam goes to wanabe, mail to wanadoo.)
/*--------------------------------------------------------------------
lxp.c: Linux Xilinx Programmer - version 0
Programs Xilinx FPGAs in slave serial mode through a parallel port,
using a Xilinx Parallel Cable III compatible interface by default.
Input bitstream files must be in RBT (ASCII) format. The parallel
port is used only in 'compatible' mode, so any old hardware will
do. Requires a Linux kernel with ppdev/parport drivers, i.e. 2.4+
or 2.2.17 with the ppdev patch; for more information see
http://people.redhat.com/twaugh/parport/.
You must have r/w permissions for the parport device you want to
use. Typical use:
$ lxp bitstream.rbt /dev/parport0
or:
$ gunzip < bitstream.rbt.gz | lxp - /dev/parport0
At the moment of this writing, I have tested lxp with a 2.2.17
kernel+patch, and with Spartan-II and XC4000XL devices. Please let
me know of your results with other setups.
- Reinoud <reinoud@remove.et.tudelft.nl>
--------------------------------------------------------------------
(c) 2001 Reinoud Lamberts
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
USA
--------------------------------------------------------------------
Development funded in part by NWO and Delft University, the
Netherlands.
Many thanks to the Linux parport developers.
Any trademarks are the property of their respective owners.
--------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include <fcntl.h>
#include <unistd.h>
#include <sys/ioctl.h>
#include <linux/ppdev.h>
#include <linux/parport.h>
/*--- interface configuration ---*/
/* Configure the interface/cable with the defines below. Xilinx
parallel cable compatible is the default. If your interface
doesn't use a signal, simply make the corresponding mask all zero.
Note that the mask defines below are named after FPGA signals they
control, and not after names used in the Xilinx parallel cable
schematic. This is because the Xilinx cable is not the only
target, and the names it uses are confusing. */
/* select data or control output lines: PPWDATA or PPWCONTROL */
#define O_WRITECMD PPWDATA
/* output signal masks */
#define O_DIN 0x01
#define O_CCLK 0x02
#define O_PROG 0x04
#define O_ENABLE 0x08 /* enable outputs */
#define O_DONE 0x10
/* Default state, determines 'inactive' levels for output signals.
Make DONE asserted, others deasserted (at the FPGA). For CCLK, be
sure to use the level before the active edge (low). */
#define O_DEFAULT (O_PROG | O_ENABLE | O_DONE)
/* input signal masks; for *_OK give masked expected OK value */
#define I_SENSE PARPORT_STATUS_ERROR
#define I_SENSE_OK I_SENSE
#define I_DONE PARPORT_STATUS_SELECT
#define I_DONE_OK I_DONE
/* usec to wait after PROGRAM release */
#define PROG_DELAY 50000
/*--- print error and clean up if needed ---*/
void err (int d, char *s)
{
unsigned char o;
perror(s);
if (d != -1)
{
o = O_DEFAULT;
ioctl(d, O_WRITECMD, &o);
ioctl(d, PPRELEASE);
}
exit(1);
}
int main(int argc, char *argv[])
{
char *rbname; /* rbt file name */
char *ppname; /* parport device file name */
FILE *f; /* rbt file ptr */
int c; /* char from f */
int d; /* descriptor for parport device */
unsigned char o; /* output data for parport */
unsigned char stat; /* status (input) data from parport */
long bitcount; /* bits transferred */
/*--- get arguments ---*/
if (argc != 3)
{
fprintf(stderr, "usage: %s <RBT file, or - for stdin> <parport device>\n",
argv[0]);
exit(2);
}
rbname = argv[1];
ppname = argv[2];
/*--- get input file ---*/
if (strcmp(rbname, "-"))
f = fopen(rbname, "r");
else
f = stdin;
if (f == NULL)
err(-1, "open bitstream file");
/*--- find data start ('0' or '1' at beginning of a line) ---*/
/* note: no file format sanity checks implemented, header format
not defined by Xilinx */
while ( ((c = getc(f)) != EOF) && (c != '0') && (c != '1') )
while ( (c != '\n') && ((c = getc(f)) != EOF) );
if (c == EOF)
{
if (ferror(f))
err(-1, "read bitstream file");
else
err(-1, "find EOF in bitstream header");
}
/*--- get parport ---*/
d = open(ppname, O_RDWR);
if (d == -1)
err(-1, "open parport");
if (ioctl(d, PPCLAIM))
err(-1, "claim parport");
/*--- check power ---*/
/* note: makes no sense for broken Xilinx parallel cable hardware */
if (ioctl(d, PPRSTATUS, &stat))
err(d, "read status parport");
if ((stat & I_SENSE) != I_SENSE_OK)
fprintf(stderr, "-- warning: no power on interface\n");
/*--- init FPGA ---*/
o = O_DEFAULT ^ O_ENABLE ^ O_PROG;
if (ioctl(d, O_WRITECMD, &o))
err(d, "write parport");
usleep(10);
o = O_DEFAULT ^ O_ENABLE;
ioctl(d, O_WRITECMD, &o);
usleep(PROG_DELAY);
/*--- download bitstream ---*/
/* note: no checks, no timing control (assumes parport hardware is
slow enough, which is reasonable if only because every parport
acces goes through some high-latency bus in practice) */
fprintf(stderr, "programming");
bitcount = 0;
while (c != EOF)
{
o = (c == '0') ? O_DEFAULT ^ O_ENABLE :
O_DEFAULT ^ O_ENABLE ^ O_DIN;
ioctl(d, O_WRITECMD, &o); /* set up data */
o ^= O_CCLK;
ioctl(d, O_WRITECMD, &o); /* toggle clock */
if (!(bitcount++ & 0x1FFFF)) /* another dot every 128k bits */
putc('.', stderr);
while ( ((c = getc(f)) != EOF) && (c != '0') && (c != '1') ); /* next c */
}
fprintf(stderr, "\ntransferred %li bits\n", bitcount);
if (ferror(f))
err(d, "read bitstream file");
/*--- check DONE ---*/
if (ioctl(d, PPRSTATUS, &stat))
err(d, "read status parport");
if ((stat & I_DONE) != I_DONE_OK)
fprintf(stderr, "-- warning: not DONE\n");
/*--- clean up ---*/
o = O_DEFAULT;
if (ioctl(d, O_WRITECMD, &o))
err(d, "write parport");
if (ioctl(d, PPRELEASE))
err(-1, "release parport");
return 0;
}
Article: 29557FPGA Express can be really weird when you are trying to use INPUTS or OUTPUTS within logical functions. Create a signal, assign that ADDR line to that new signal and use the signal for your case statement and all should be well. Chris weMPEC wrote: > Hi > > I always have something wrong with my > case when I check syntax in xilinx > foundation > here is my brief program > > the xilinx foundation says > " Expression must be the name of > an object whose subtype is locally > static, or it must be a qualified > expression or type conversion whose > type mark denote a locally static > subtype" > --LIBRARY ieee; > > ENTITY PWM IS > generic( DATAWIDTH: INTEGER :=23; > ADDRWIDTH:... > PORT( > CLK: in STD_LOGIC; > RESET: in STD_LOGIC; > DATA: IN > STD_LOGIC_VECTOR(DATAWIDTH DOWNTO 0); > ADDR: IN > STD_LOGIC_VECTOR(ADDRWIDTH DOWNTO 0); > WAVE1: out STD_LOGIC; > WAVE2: out STD_LOGIC > ); > END PWM; > > ARCHITECTURE ver1 OF PWM IS > > signal SWITCHING_F: > STD_LOGIC_VECTOR(DATAWIDTH downto 0); > > BEGIN > REG: PROCESS(ADDR,DATA,CLK,RESET) > BEGIN > IF RESET='1' THEN > SWITCHING_F<=DATAZERO; > ELSIF CLK'EVENT AND CLK='1' THEN > CASE ADDR IS > WHEN "0000" => SWITCHING_F<=DATA; > END CASE; > END IF; > END PROCESS; > > END ver1;Article: 29558
Xilinx is correct. Addr is globally static because its dimensio is sized from the generic. Array case expression must have a STATIC subtype. Use the "if" statement instead. -------------------------------------------------------------------------- ----------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Component Design by Example ... a Step-by-Step Process Using VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 -------------------------------------------------------------------------- ------------------------------------------ >I always have something wrong with my >case when I check syntax in xilinx >foundation >here is my brief program > >the xilinx foundation says >" Expression must be the name of >an object whose subtype is locally >static, or it must be a qualified >expression or type conversion whose >type mark denote a locally static >subtype" >--LIBRARY ieee; > >ENTITY PWM IS > generic( DATAWIDTH: INTEGER :=23; > ADDRWIDTH:... > PORT( > CLK: in STD_LOGIC; > RESET: in STD_LOGIC; > DATA: IN >STD_LOGIC_VECTOR(DATAWIDTH DOWNTO 0); > ADDR: IN >STD_LOGIC_VECTOR(ADDRWIDTH DOWNTO 0); > WAVE1: out STD_LOGIC; > WAVE2: out STD_LOGIC > ); >END PWM; > >ARCHITECTURE ver1 OF PWM IS > > signal SWITCHING_F: >STD_LOGIC_VECTOR(DATAWIDTH downto 0); > >BEGIN >REG: PROCESS(ADDR,DATA,CLK,RESET) > BEGIN > IF RESET='1' THEN > SWITCHING_F<=DATAZERO; > ELSIF CLK'EVENT AND CLK='1' THEN > CASE ADDR IS > WHEN "0000" => SWITCHING_F<=DATA; > END CASE; > END IF; > END PROCESS; > >END ver1; > >Article: 29559
We are very interested in this project and have done others like it.=20= Please check out our web site and provide us with some more project=20 information so we can supply you with a project plan and an estimate of = the cost. Regards, Tom Dillon Dillon Engineering, Inc. http://www.dilloneng.com >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<< On 2/23/2001, 9:20:38 AM, AvdL <erikl80@nospam.hotmail.com> wrote regard= ing=20 Searching for FPGA designer (PCI interface,DES, IDE): > Dear Sir/Madam, > We (Argolis) are a small company that develops smartcard technology. > For our new project we need a PCI card that communicates with our > reader (RS232-protocol). We want to place a FPGA on the PCI board that= > communicates with the smartcard reader, the computer (PCI) and IDE > port. The FPGA must also be able to do DES. It would be nice if the > FPGA also could handle compression of the data. The last option is not= > necessary. > Please contact us if your are interested in this project. We will > provide the hardware and we ask from you to develop the source for the= > FPGA. > Kind regards, > Argolis > Ad van de Laar > email to : info<at>argolis<dot>nlArticle: 29560
Just a quick message. Thanks to all that replied to my first message. Many of your suggestions where very helpful and have been implemented. 'The Business Software Guide' is now easier to use and noticeably faster. For those that missed my first posting, the site www.businesssoftwareguide.co.uk offers a detailed software search function that matches software buyers requirements with the specifications of a wide variety of business, financial and accounting software products. Check it out if you have a few minutes, further suggestions are encouraged. The site also has news on software developments from around the world, a listing of software consultants and a detailed links page. In recognition of our recent launch, throughout March we will be giving away a Palm IIIxe. I hope that you all have a chance to enter and good luck!!!!!!!!!! Your time is greatly appreciated Warm Regards JamesArticle: 29561
This is a multi-part message in MIME format. ------=_NextPart_000_00AF_01C0A006.ADFADA00 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable I need help with partial reconfig of a virtex Chip. JBits has been = suggested to me. From what I understand of JBits I am under the impression that VHDL, BDE = source files cannot be used with JBits. Is this true ?=20 Jaimeet Aneja ------=_NextPart_000_00AF_01C0A006.ADFADA00 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META content=3D"text/html; charset=3Diso-8859-1" = http-equiv=3DContent-Type> <META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3DArial size=3D2><FONT face=3DArial size=3D2>I need help = with partial=20 reconfig of a virtex Chip. JBits has been suggested to = me.</FONT></FONT></DIV> <DIV><FONT face=3DArial size=3D2><FONT face=3DArial size=3D2>From = what I=20 understand of JBits I am under the impression that VHDL, BDE = source files=20 cannot be used with JBits. Is this true ? </FONT></FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV><FONT face=3DArial = size=3D2> <DIV><FONT face=3DArial size=3D2> <DIV><FONT face=3DArial size=3D2>Jaimeet=20 Aneja</FONT></DIV></FONT></DIV></FONT></BODY></HTML> ------=_NextPart_000_00AF_01C0A006.ADFADA00-- -- Posted from mail.nuron.com [63.100.168.245] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 29562
This is a multi-part message in MIME format. ------=_NextPart_000_00BA_01C0A006.EC7FCBA0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable > 2. fix the in-out nets of modules so that they can be replaced by a > new module and still line up perfectly with the rest of the design. Ermm, there in lies the rub. When you hand over your design to the mainstream implementation tools, you are basically telling them to make single, optimised, static version of your design. The tools are free to do things like move blocks of logic around to achieve this goal. Most people just want a version of their design that a. meets timing requirements and b. uses enough resources to justify the size of chip. Even if you work at the lowest level and hand place each primitive LUT and FF, the tools will still conspire against you in order to meet timing, and do things like swap address lines into the look-up tables.=20 Similarly routes will pass through the middle of the module you wish to swap out. AFAIK, the only tool that will help you out here is JBits, allowing you total control over placement and mapping, and also allow run-time routing of your modules. This allows cooperation with other parts of your design, allowing your new module to talk to the same parts of the circuit the previous module did. Drop us a line at jbits@xilinx.com and we can sort you out. =20 Phil From what I understand of JBits I am under the impression that VHDL, BDE = source files cannot be used with JBits. Is this true ?=20 =20 Jaimeet Aneja ------=_NextPart_000_00BA_01C0A006.EC7FCBA0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META content=3D"text/html; charset=3Diso-8859-1" = http-equiv=3DContent-Type> <META content=3D"MSHTML 5.00.3103.1000" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3DArial size=3D2> <DIV><FONT face=3DArial size=3D2><FONT face=3DArial size=3D2>> 2. fix = the in-out nets=20 of modules so that they can be replaced by a<BR>> new module and = still line=20 up perfectly with the rest of the design.<BR><BR>Ermm, there in lies the = rub. When you hand over your design to the<BR>mainstream = implementation=20 tools, you are basically telling them to make<BR>single, optimised, = static=20 version of your design. The tools are free to<BR>do things like = move=20 blocks of logic around to achieve this goal. Most<BR>people just = want a=20 version of their design that a. meets timing<BR>requirements and b. uses = enough=20 resources to justify the size of chip.<BR>Even if you work at the lowest = level=20 and hand place each primitive LUT<BR>and FF, the tools will still = conspire=20 against you in order to meet<BR>timing, and do things like swap address = lines=20 into the look-up tables. <BR>Similarly routes will pass through the = middle of=20 the module you wish to<BR>swap out.<BR>AFAIK, the only tool that will = help you=20 out here is JBits, allowing you<BR>total control over placement and = mapping, and=20 also allow run-time<BR>routing of your modules. This allows cooperation = with=20 other parts of<BR>your design, allowing your new module to talk to the = same=20 parts of the<BR>circuit the previous module did.<BR>Drop us a line at=20 jbits@xilinx.com and we can sort you out. = <BR>Phil</FONT></FONT></DIV> <DIV><FONT face=3DArial size=3D2><FONT face=3DArial = size=3D2></FONT></FONT> </DIV> <DIV><FONT face=3DArial size=3D2><FONT face=3DArial = size=3D2></FONT></FONT> </DIV> <DIV><FONT face=3DArial size=3D2><FONT face=3DArial size=3D2>From = what I=20 understand of JBits I am under the impression that VHDL, BDE source = files=20 cannot be used with JBits. Is this true ? </FONT></FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV><FONT face=3DArial = size=3D2> <DIV><FONT face=3DArial size=3D2> <DIV><FONT face=3DArial size=3D2>Jaimeet=20 Aneja</FONT></DIV></FONT></DIV></FONT></FONT></DIV></BODY></HTML> ------=_NextPart_000_00BA_01C0A006.EC7FCBA0-- -- Posted from mail.nuron.com [63.100.168.245] via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 29563
You can do it in VHDL if the VHDL compiler supports user attributes (synplicity does). You can't do it in the UCF files because UCFs are not hierarchical. Last time I checked, there was no support in verilog for this. Reinoud wrote: > > Hi, > > Is it possible to use a hierachy of RLOC constraints for a HDL > (Verilog) design with instantiated primitives? > > The documentation indicates that it is possible to do RLOC placement > not only on primitives, but also on sets of primitives, in a nicely > hierarchical fashion (adding relative positions down the hierarchy). > I don't see how to make this work with UCF file statements for a > Verilog module hierarchy, though. Is there a way, or does this only > work with library macros or schematics? > > Thanks! > > - Reinoud > > ---- > > Spam goes to wanabe, mail to wanadoo. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 29564
You can build RPMs it in Synplicity Verilog too. I had a problem using multi-level hierarchical RPM modules with xc_rloc, but thankfully no such problem using xc_props="RLOC=R1C2" and xc_map="lut". For example, here's a floorplanned 16-bit register: module dff16_s1(clk, ce, d, q) /* synthesis syn_hier="hard" */; input clk, ce; input [15:0] d; output [15:0] q; dff4_s1 q0(.clk(clk), .ce(ce), .d(d[3:0]), .q(q[3:0])) /* synthesis xc_props="RLOC=R6C0" */; dff4_s1 q4(.clk(clk), .ce(ce), .d(d[7:4]), .q(q[7:4])) /* synthesis xc_props="RLOC=R4C0" */; dff4_s1 q8(.clk(clk), .ce(ce), .d(d[11:8]), .q(q[11:8])) /* synthesis xc_props="RLOC=R2C0" */; dff4_s1 q12(.clk(clk), .ce(ce), .d(d[15:12]), .q(q[15:12])) /* synthesis xc_props="RLOC=R0C0" */; endmodule module dff4_s1(clk, ce, d, q) /* synthesis syn_hier="hard" */; input clk, ce; input [3:0] d; output [3:0] q; FDE q0(.C(clk), .CE(ce), .D(d[0]), .Q(q[0])) /* synthesis xc_props="RLOC=R1C0.S1" */; FDE q1(.C(clk), .CE(ce), .D(d[1]), .Q(q[1])) /* synthesis xc_props="RLOC=R1C0.S1" */; FDE q2(.C(clk), .CE(ce), .D(d[2]), .Q(q[2])) /* synthesis xc_props="RLOC=R0C0.S1" */; FDE q3(.C(clk), .CE(ce), .D(d[3]), .Q(q[3])) /* synthesis xc_props="RLOC=R0C0.S1" */; endmodule I consider it such a privilege to have to build and maintain .S0 and .S1 versions of all my RPMs. And based upon code I've seen from Arrigo Benedetti and others I now realize it's more elegant to use VHDL (with its generics and generates). Jan Gray, Gray Research LLCArticle: 29565
Andy, I will probably shock someone somewhere, but I agree with you. There are some things that are so well entrenched, so ubiquitous, and/or so screwey to implement (perhaps intentionally), that FPGA's are not even a realistic consideration. The ASIC is just too cheap and easy not to use. Sometimes people paint themselves into a corner, and have to provide a solution without adding anything, or without increasing the cost, but it can be very painful, and all of the cost savings often disappear. If it is popular enough (like PCI), we will do a core as IP from the IP center. If it requires a special hardware interface, then it might end up as a built in hardware design (like LVDS, or LDT/ULVDS in Virtex II). By the way, they are promoting USB II now, so we are not highly motivated to implement an older interface. More exciting are the newer Infiniband 2.4 Gb/s interfaces! Austin Andy Peters wrote: > "George P. Burdell" wrote: > > > > Has anyone had success implementing a USB interace with the Xilinx > > Virtex series chips? I imagine you would need a transceiver chip, but > > which one is best to use? And has anyone gotten it working? And more > > specifically, does anyone have design docs or schematic files for it? > > Otherwise it looks like I'm going to have to start from scratch using > > the PDIUSBP11A. > > You're probably better off putting the USB functions into one of the > dozen or so USB microcontrollers you can buy. Most of them are based on > an 8051 core. For instance, I'm doing a USB audio project and I'm using > the TI TUSB3200 part. It literally does everything I need it to do, > with very little programming (mostly setting up endpoints). And it's > like $5.50 in 1K quantities. > > Cypress has their EZ-USB-FX parts which cost more (maybe $15 each) but > they're also easy to program. > > I think doing USB in a big Virtex part is exactly the wrong thing to do. > > just my opinion, of course. > > -aArticle: 29566
"Will" <dont@mail.me> wrote in message news:978r8n$hp9$1@news.inet.tele.dk... > > You can download free software from both Xilinx and Altera to design > > FPGAs in VHDL or Verilog. So why both learning CUPL? You don't need to > > be limimted by your software. > > CUPL is bad comparad to vhdl? CUPL is a _toy_ compared to VHDL. "Bad" is a little more subjective... ---Joel KolstadArticle: 29567
Austin Lesea wrote: > > Rick, > > Call it what you will. > > It is intended to aid those that have less than the 500 mA available. > > Initially, we thought, "anyone using this IC will probably run it at a clock speed, > and with enough IO's that 500 mA will be required for its normal operation." > Obviously, there is a smaller contingent of users that do not use the fast clock > rates, or the large drive strengths, and need to get by with 200 or so mA. > > To help those users, we are working on the kick start circuit. > > As I said before, it is now being built, and we hope to have some results to report > by next week. > > The area we are talking about here is pretty tiny. Surface mount caps are required > anyway for good bypassing. The comparator is a tiny three leaded surface mount part > (2 X 2 mm?). Resistors are pretty tiny as well. I can't see them anymore (getting > old). > > The LDO will supply the voltage to the Vccint from the big capacitor, and at the > output of the LDO, the power will be rising monotonically. The 3.3 Vdc may droop > (that is why it is better if available to run the core voltage LDO off 5 Vdc), but > the droop is something one engineers (I=C dV/dt) to be small. > > The monotonicity "rule" is not a hard rule. We care about the voltage rising > through the POR trip point, and not falling back down after once passing through the > POR trip point. I believe this is stated in a number of tech notes/tech tips. It > may also be stated in the configuration section of the data sheet similar to how I > have stated it above. This is even to be relaxed at some point in the future Virtex > II as we designed it to not care about this point in the power on ramp. This is > something we will later test and verify as not being a problem. As well, Virtex II > power on is in the tens of mA range, so we do try to improve in every subsequent > generation. > > Austin I think this is an issue that is a bit too complex to iron out in the newsgroup, so I will wait for the app note. I think one point I may be missing is that this circuit is not in addition to the 2.5v supply that I have on my board for the FPGAs, but rather is in place of them. So I lose the efficiency of the switcher that I planned to use and instead would get the efficiency of a lossy LDO, 75% vs 95% or worse, 50% if powered by 5v. The loss in efficiency is a problem for me. I am designing a board that is intended to be very low power when required. The only LDO on the board is for the DSP core voltage which is less than 100 mA. But I do understand the concept that you are using a current limited regulator for startup. Or did I miss your meaning and the "kick start" circuit is intended to parallel the main regulator? BTW, I am not aware of any 500 mA LDO regulators in the SC70 (2mm x 2mm) package you describe. The highest current I have found in this small package is about 100 mA. SOT-23 packages boost that up to about 150 to 200 mA and you can get 300 or better from a MSOP8 package, 3mm x 5mm. The caps you mention, 1000 uF may come in surface mount, but they are hardly tiny as the resistors are. This cap is likely bigger than the regulator. So the total area will be nearly as large as the FPGA in my application (FG256, 17mm sq or CS144 12mm sq). I am also puzzled that Xilinx felt that these chips would not often be used with low power requirements. The smaller XC2S chips are available in CS144 packages that are quite tiny and have a limited power capacity. With a theta JA of 35C/W, 500 mA will put the junction temp at 125C with an ambient temp of just 81C. This is not much of a margin of saftey. The TQ100 package is potentially much worse with a theta JA of up to 47C/W. This puts the maximum ambient at 66C. I am glad to hear the the Virtex II chips have reduced the startup current to below 100 mA. This is much more workable. Now if we could only get the low price combined with the low current! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 29568
Lower level derived clocks do not appear in the GUI, unfortunately you will need to constrain these clocks by type the command Andy Gil Golov schrieb in Nachricht <3A81212C.EF8967DB@sony.de.REMOVE_THIS>... > >I try to use DLL using the standard connection path >Ibufg->DLL_input->DLL_clk0->Gbuf->DLL_fb+my_system_clock. >Leonardo Spectrom does not understand that there is a connection between >the input and the output of the DLL. Therefore under the >constrains/clock I get nothing and instead my input clock appears under >the input signal sections. This is wrong because the tool does not >realize that my clock signal is the input clock of the system. > >Any ideas? > >Many thanks > >Gil Golov > >Article: 29569
"Jan Gray" <jsgray@acm.org> wrote in message news:iGEm6.2375$XA.414596@dfiatx1-snr1.gtei.net... > You can build RPMs it in Synplicity Verilog too. > And based upon code I've seen from Arrigo Benedetti and others I now realize > it's more elegant to use VHDL (with its generics and generates). And with attributes which can be evaluated via table lookups or via functions. Verilog attributes are static comments, unless you use something like an auxiliary Perl script to massage the source code.Article: 29570
Jan, Ray: thanks. So hierarchy works with attributes in source (and most Verilog synthesis tools support attributes in some way nowadays). That's tempting to use, but I originally decided to use UCF for portability (should work independent from synthesis tool peculiarities) and power (e.g. can also set routing priorities on nets). Maybe I'll stick with UCF; when generating UCF statements (with C) the lack of hierachy isn't so bad... - Reinoud ---- Spam goes to wanabe, mail to wanadoo.Article: 29571
Ray Andraka wrote: > As for using UCFs for placement, that works fine for a one-off design, but it is > horrible for reuse. Not only is the UCF flat, but the placement information in > a UCF is absolute, not relative, and is therefore device specific. UCF supports relative placement just fine, it's the hierarchy that's lacking. There is no reuse issue; actually, UCF statements are synthesis tool independent and hence more portable (as long as Xilinx is the target)... - Reinoud ---- Spam goes to wanabe, mail to wanadoo.Article: 29572
As Jan mentioned, VHDL's generate statements permit parameterized construction of elements, something that is harder to do with verilog. I stand corrected on the availability of the user attributes in Verilog (it has been a while since I last investigated using Verilog). As for using UCFs for placement, that works fine for a one-off design, but it is horrible for reuse. Not only is the UCF flat, but the placement information in a UCF is absolute, not relative, and is therefore device specific. Reinoud wrote: > > Jan, Ray: thanks. So hierarchy works with attributes in source (and > most Verilog synthesis tools support attributes in some way > nowadays). That's tempting to use, but I originally decided to use > UCF for portability (should work independent from synthesis tool > peculiarities) and power (e.g. can also set routing priorities on > nets). Maybe I'll stick with UCF; when generating UCF statements > (with C) the lack of hierachy isn't so bad... > > - Reinoud > > ---- > > Spam goes to wanabe, mail to wanadoo. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 29573
USB is a bit awkward for a strictly hardware implementation because of the rather complex protocol layer. If you are doing it in an FPGA, it would probably make sense to use a microcontroller core for the protocol layer such as the risc processor published by Jan Gray, or if you are using the Altera parts, perhaps the NIOS processor (someone recently told me NIOS was an acronym for "not in our system" :-) ). As long as the microcontroller is one that is designed to the FPGA fabric, you can get pretty good performance in a fairly small footprint. The short answer then is, yes you can do the USB in an FPGA, and if you have enough spare CLBs in a design that already uses an FPGA, this could make lots of sense provided the extra engineering effort is balanced by sufficient production volume to make the amortized effort less than the cost of the extra board area and component costs of a less integrated design. Another consideration is that the USB bus powered specification has a fairly low power requirement. For many FPGA designs, you'll be forced to use a dedicated power supply for your USB appliance. Austin Lesea wrote: > > Andy, > > I will probably shock someone somewhere, but I agree with you. There are > some things that are so well entrenched, so ubiquitous, and/or so screwey to > implement (perhaps intentionally), that FPGA's are not even a realistic > consideration. The ASIC is just too cheap and easy not to use. > > Sometimes people paint themselves into a corner, and have to provide a > solution without adding anything, or without increasing the cost, but it can > be very painful, and all of the cost savings often disappear. > > If it is popular enough (like PCI), we will do a core as IP from the IP > center. If it requires a special hardware interface, then it might end up > as a built in hardware design (like LVDS, or LDT/ULVDS in Virtex II). > > By the way, they are promoting USB II now, so we are not highly motivated to > implement an older interface. More exciting are the newer Infiniband 2.4 > Gb/s interfaces! > > Austin > > Andy Peters wrote: > > > "George P. Burdell" wrote: > > > > > > Has anyone had success implementing a USB interace with the Xilinx > > > Virtex series chips? I imagine you would need a transceiver chip, but > > > which one is best to use? And has anyone gotten it working? And more > > > specifically, does anyone have design docs or schematic files for it? > > > Otherwise it looks like I'm going to have to start from scratch using > > > the PDIUSBP11A. > > > > You're probably better off putting the USB functions into one of the > > dozen or so USB microcontrollers you can buy. Most of them are based on > > an 8051 core. For instance, I'm doing a USB audio project and I'm using > > the TI TUSB3200 part. It literally does everything I need it to do, > > with very little programming (mostly setting up endpoints). And it's > > like $5.50 in 1K quantities. > > > > Cypress has their EZ-USB-FX parts which cost more (maybe $15 each) but > > they're also easy to program. > > > > I think doing USB in a big Virtex part is exactly the wrong thing to do. > > > > just my opinion, of course. > > > > -a -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 29574
IIRC, you can get around the monotonicity requirement by holding the program pin until the power is stable. As to the boot current, this should not be a problem if you are really using the FPGA to its potential, as the operating current for a well utilized FPGA is higher than the boot current (if it is not, then you can usually use serial or time multiplex techniques to get into a smaller part with a smaller boot current). Austin Lesea wrote: > > Rick, > > Call it what you will. > > It is intended to aid those that have less than the 500 mA available. > > Initially, we thought, "anyone using this IC will probably run it at a clock speed, > and with enough IO's that 500 mA will be required for its normal operation." > Obviously, there is a smaller contingent of users that do not use the fast clock > rates, or the large drive strengths, and need to get by with 200 or so mA. > > To help those users, we are working on the kick start circuit. > > As I said before, it is now being built, and we hope to have some results to report > by next week. > > The area we are talking about here is pretty tiny. Surface mount caps are required > anyway for good bypassing. The comparator is a tiny three leaded surface mount part > (2 X 2 mm?). Resistors are pretty tiny as well. I can't see them anymore (getting > old). > > The LDO will supply the voltage to the Vccint from the big capacitor, and at the > output of the LDO, the power will be rising monotonically. The 3.3 Vdc may droop > (that is why it is better if available to run the core voltage LDO off 5 Vdc), but > the droop is something one engineers (I=C dV/dt) to be small. > > The monotonicity "rule" is not a hard rule. We care about the voltage rising > through the POR trip point, and not falling back down after once passing through the > POR trip point. I believe this is stated in a number of tech notes/tech tips. It > may also be stated in the configuration section of the data sheet similar to how I > have stated it above. This is even to be relaxed at some point in the future Virtex > II as we designed it to not care about this point in the power on ramp. This is > something we will later test and verify as not being a problem. As well, Virtex II > power on is in the tens of mA range, so we do try to improve in every subsequent > generation. > > Austin > > Rick Collins wrote: > > > Austin, > > > > I don't mean to be rude, but is this circuit intended to be a "fix" to > > the power up issue? > > > > I can just as easily increase the surge capacity of my power converter > > than to add a secondary circuit to handle the few mS of startup current. > > The cost of this added startup circuit may be small, but it uses a lot > > of board space. By the time you account for the power requirement of the > > I grade, the board space of the chip has doubled. > > > > The other issue that I would raise with this circuit is the requirement > > that the voltage at startup be increased monotonically. If you depend on > > capacitors to provide current to the load, then the voltage will sag > > during that time. Perhaps the parts are not affected by a small voltage > > droop, hence the huge capacitor requirement. But doesn't the data sheet > > say that the voltage must increase monotonically? I can't find that now. > > Perhaps I saw it in an app note or the data sheet for the Virtex parts? > > Or am I mistaken about this? > > > > Austin Lesea wrote: > > > > > > Rick & Paul, > > > > > > Been out on vacation, so I missed this question. > > > > > > Spartan II is a Virtex derivative, so it has the same behavior during power up > > > as the Virtex family. Now this is about 2.5 years old, so it is a pretty well > > > known behavior. > > > > > > The ramp up time has a secondary effect on the amount of current required. > > > The shortest ramps require more current than the longer ramps, but as they get > > > close to 50 ms (the spec), the currents may start going back up again. > > > Current increases as temperature decreases. > > > > > > The current is required at about twice the Vt of the transistors (~0.7 to 1.0 > > > Vdc), and lasts perhaps as long as 200 us in the smaller parts of Spartan. > > > > > > We are now building the "kick start" circuit I had previously described. It > > > uses a 500 mA current limited LDO regulator with an enable pin. > > > > > > The enable pin comes from a micro power comparator /voltage reference ( we > > > abandoned the simple RC -- too unpredictable). > > > > > > When the input voltage (3.3 or 5 Vdc) passes a set threshold (set by two > > > resistors), the LDO is enabled. > > > > > > Ahead of the LDO is a ~1,000 uF 6.3 V cap that stores the necessary current to > > > start up the part. > > > > > > For four devices, this same technique can be extended to a larger cap, and a 2 > > > ampere LDO. > > > > > > The idea is quite simple: use the stored charge in the big cap to provide the > > > necessary kick to get all the parts started. For the I grade, at -40C, you > > > need 2 amps per part, and again, it is bigger capacitor, and larger regulators > > > (better is a low voltage switcher enabled by the comparator). > > > > > > The added cost is the mico power comparator / reference (less than 1$), two > > > resistors, and a big cap (<25 cents for a good aluminium electrolytic of large > > > value). (This assumes you have to provide a 2.5 V power supply regulator > > > anyway). > > > > > > In the meantime, the Spartan designers continue to optimize process / design / > > > test to improve the startup behavior. > > > > > > As soon as we have tested the kick starter with all process corner silicon, I > > > will publish it as a note. > > > > > > Again, I apologize for the delays, > > > > > > Austin > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.com
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