Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Bob Perlman wrote: > > "Where can I get cheap development tools for programmable devices?" > You see that question frequently in this group. > > Brian Dipert has written a nice article in EDN on just that subject. > Go to: > > http://www.e-insite.net/ednmag/index.asp?layout=article&articleid=CA300026&pubdate=5%2F29%2F2003 Hmmm, I'd rate it OK, but a little thin on the CPLD end of the scale, and suspect it did not take a lot of time. Working forward from his 1997 time line, my understanding of the CPLD end is : AnaChip (ex ICT): Have Free SW called Place (and recently WinPlace), which does layout and fitting for all their SPLD and CPLD devices. Devices: They offer CMOS Zero power SPLD, and include hysteresis on newer models. Atmel: Have Free SW called WinCUPL. This was count limited, or qualified, but is now fully free - it makes a good teaching tool, and is good for SPLD/CPLD level designs. They also offer ProChip designer, with Altium bundles further up the price curve - tho their largest PLD device is 128 Macrocells. For HW development, Atmel have ISP cables, and ATF15xx-DK2 is an eval PCB with a PLCC84 ZIF (ATF1504/ATF1508) and 8x7 seg LEDS. IIRC this was $99. Devices: Atmel have 5V and 3V offerings, and have low static Icc values, on all SPLD and CPLD devices. Speeds and Max sizes are not 'leading edge'. Atmel also have niche FPGA solutions, not widely deployed. STm : Used to charge for full PSD Tool flow (ABEL variant), but I believe it is now free. Have recently released a 80C51+SPLD+Memory JTAG ISP device family, where the SPLD is appx 16 Macrocells. Time-bombed Sw generally 'goes down like a lead balloon', but sometimes it is not the chip vendors themselves that mandate that, but the tools they license. Teaching environments may lie unused for many months, and tutors do not want to find first monday that the tools have timed out over the holidays! There are also version control issues :- many companies like to 'freeze' the Design file AS WELL AS the tool chains used, for later revisions. -jgArticle: 56651
Nick, you can try here www.fpga4fun.com and let me know how that works. Jean "Nick Young" <nick_young@talk21.com> wrote in message news:bc55aa$9ml$1@titan.btinternet.com... > Hi, > > I want to get into FPGA's but havnt the first clue about how to go about it. > I would like to learn, hands on projects, about how to use and program > FPGA's. I have a very small budget so the less I can spend the better. Can > anyone suggest where to start > > Cheers, > Nick > > -- > ------------------oOo------------------------------- > Mr Nick Young - MIEE MEng (Hons) > nick_young@talk21.com > http://www.nickbits.co.uk > >Article: 56652
> Hmmm, I'd rate it OK, but a little thin on the CPLD end of the scale, >and >suspect it did not take a lot of time. Yeah, if I just didn't require those blasted two minimum hours of sleep every night.....or if the scientists would just quit fooling arond and perfect human cloning.... ...biting his tongue... NOTE NEW ADDRESS AND FAX NUMBER Brian Dipert Technical Editor: Mass Storage, Memory, Multimedia, PC Core Logic and Peripherals, and Programmable Logic EDN Magazine: http://www.edn.com Contributing Editor, CommVerge Magazine: http://www.commvergemag.com 5000 V Street Sacramento, CA 95817 (916) 454-5242 (voice), (617) 558-4470 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.edn.com Visit me at http://www.bdipert.comArticle: 56653
I think you understood what I meant. But, it's OK to poke a little fun at loosely used terminology. No problem. There's lot to be laugh at with FPGA's. As a hardware person I look with amazement at how hardware people mucked this FPGA thing up to the point of having to speak in metaphores (inference) "hey, if you say this it will think you mean this and do that, but not always, so you might want to preceed it with this just in case". Yeah, I dig that. Not. Regarding my loose utilization of LSB/MSB. The languages we use force us to call one end LSB and the other MSB by means of the index-based notation. I know damn well that you can call the bits whatever you want. I'm guilty of not using architecturally precise language when asking the question. let's try again: Are there architecture-dependent reasons to prefer building a shift register that shifts from the bottom of the carry chaing to the top vs. going the other way? What if one needs access to intermediate flip-flop outputs rather than just the input and output of the shift register? My prior posts made the assumption that what is the LSB in HDL is located farther south in the carry logic chain. Isn't it the case that the Xilinx tools will place the (HDL defined) LSB lower in the carry chain? If that's the case, wouldn't it be correct to speak in terms of LSB and MSB when discussing how the bits flow in this shift register, since the LSB is always at the bottom? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Peter Alfke" <peter@xilinx.com> wrote in message news:3EE6381C.9EFD2A57@xilinx.com... > As a hardware-oriented guy, I have been watching this thread in amazement. > The difference between calling something LSB or MSB, or bit number > whatever is just in your mind. The circuitry does not give a damn, it > just shifts the content of one latch or flip-flop into the neighbor that > it is connected to. Whether you call that left-shift or right-shift is > entirely up to you, ditto for the bit numbering. > Physically, the carry logic goes vertically up ( in Xilinx parts), and > LFSR shifting is towards the higher binary address, but that should not > be confused with an architectural limitation. A name is just a name... > Peter Alfke > > > Martin Euredjian wrote: > > > > Say you can't use an SRL, as in: > > > > output <= sr[3]; > > sr[3] <= sr[2]; > > sr[2] <= sr[1]; > > sr[1] <= sr[0]; > > sr[0] <= input && sr[1] && sr[2]; > > > > Are there architecture-driven advantages (speed, logic utilization, etc.?) > > for going LSB-to-MSB vs MSB-to-LSB on Virtex 2? > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu"Article: 56654
On Tue, 10 Jun 2003 14:16:28 GMT, Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: >I have this Pseudo Random Shift Register with some XORed feedbacks. >Now this generates a one-bit random distribution, while I should >have a few more bits for a DAC. Can I just combine any >shift register intermediate taps to my parallel DAC [snip] Connecting the (Fibonacci) LFSR internal state to a DAC in parallel can be modeled as a 1 bit LFSR followed by an FIR filter. The FIR filter taps are just the DAC bit weights. If you are shifting LSB to MSB, the impulse response is: 1/128, 1/64, ... 1/2, 1. If you are shifting MSB to LSB, the impulse response is: 1, 1/2, ... 1/64, 1/128, which is the time reversal of the other impulse response (which means that the magnitude response is the same, but the phase has been reversed). This response is equivalent to a single pole low pass filter. (If that's what you actually wanted, it's much cheaper just to use a single bit output of the LFSR and an RC LP filter.) As the other posters said, this isn't the way to make a random voltage generator. What are you actually trying to achieve? Allan.Article: 56655
Hello, I want to program a Xilinx CPLD XPLA3 device via JTAG with a microcontroller. I found on the Xilinx Homepage the appnote with the C-Code to program, but I have the following problem: I generate the SVF File with the XPLA Programmer 4.14 (program the device). This code works fine. If I want to verify the device with my microcontroller I have to use the XSVF file which will be created from the Xilinx iMPACT 4.2 Tool. The code which is created by the XPLA Programmer 4.14 won't be work. If I do a program and verify in one step the CPLD will be died. Is there a explanation for this behaviour? Thank you for your answer. bye martinArticle: 56656
>Any clocks connected to the pld ? The chip must not have any free running >signal on any pin during programming. What's going on there? Is there something in the chip that gets confused if a signal changes? Or is that just a symptom of something being right on the edge and some extra noise pushing it over? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56657
>> The problem there is that the interface levels are tied to the VCC while >> the Xilinx FPGA has different VCCIO and VCCINT voltages. The delay I need >> is in the 30-40ns range total but I would like to have taps at each 2-3ns >> point. > > That's relatively coarse, by modern device standards. > If you can tolerate quantize jumps, of this order, then > a simple digital multi-tap delay line should do ? > If the circuit self-centers, (by the phase comp action) > then the temp/batch/routing variations are taken care of. > -jg Yes, that's the plan. Only do it inside an FPGA (using LUTs and timing constraits or manual routing). Thanks again for all the help, AndrasArticle: 56658
>I don't really want to go off-chip with this. As soon as I have to through >the IO ring I loose a bunch of time, consume a bunch of power, use up a >bunch of I/O etc. Also, these are ECL devices and that standard is not >directly supported by the Xilinx device. You need interface chips which add >additional delay and PCB space and power consumption and price, the whole >design starts to explode... I'm not trying to get you to use those chips, but please don't be discouraged because they say ECL. The data sheet even has info on PECL mode vs NECL. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56659
In article <3EE6C7F1.6020702@displaign.de>, Martin Sauer <msau@displaign.de> wrote: >If I do a program and verify in one step the CPLD will be died. Did you erase it first? -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 56660
"Andrea Sabatini" <sabatini@nergal.it> wrote in message news:<bc4mag$mp2$1@newsreader2.mclink.it>... > I have a project based on ACEX1k100 made using Synopsys Altera Edition for > synthesys and MaxPlusII v10.0 for fitting. Now I have to make some changes > and I would like to migrate to Synplify and Quartus. So I syntesyzed the > opriginal files with Synplify and I made a new project with Quartus, > importing the MaxPlusII .acf file in it. Quartus was not able to fit the > project that MaxPlus did because it was not able to route all the nets! to > be more precise, it was not able to compile the project even with the > original Synopsys synthetyzed files! > > Does someone have any suggestions? > > Regards > > Andrea Have you checked if the clocks which were "global" in Maxplus 2 are still "global" after Quartus II placement ? An unnecessary multiplication of clock lines could be the cause of your problem. Hope this helps Giuseppe GiachellaArticle: 56661
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote: >Are there architecture-dependent reasons to prefer building a shift register >that shifts from the bottom of the carry chaing to the top vs. going the >other way? What if one needs access to intermediate flip-flop outputs >rather than just the input and output of the shift register? > >My prior posts made the assumption that what is the LSB in HDL is located >farther south in the carry logic chain. Isn't it the case that the Xilinx >tools will place the (HDL defined) LSB lower in the carry chain? If that's >the case, wouldn't it be correct to speak in terms of LSB and MSB when >discussing how the bits flow in this shift register, since the LSB is always >at the bottom? No. The place-and-route tool is smart enough to place the synthesised gates in a way that minimises propagation delays. The synthesiser is the problem, here. The Xilinx documentation implies that XST won't infer a shift-register if the syntax is not just so, in which case, it will use its general-purpose algorithms for synthesising distributed logic, and that _might_ create a less efficient solution in terms of gate count. -- Dave FarranceArticle: 56662
Right, in summary, it looks like (as we had thought) V-II is not capable of doing the PHY of DVI :-( Thanks all! Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 56663
Hello, Thanks to all for help. The details I have omitted are: 1. I am using the Parallel Cable III 2. I have a second chip in my jtag chain (VIRTEX XCV800-HQ240-4) The symptom for iMPACT is that the programming process dies at some point in the process. Disconnection of free running clocks did not help. So, we have done a step back and installed the Xilinx Foundation 3.1i with the jtagprogrammer. That was it and now the programming process finishes OK. Regards, KrzysiekArticle: 56664
The erase command is in the svf file included. Ben Jackson schrieb: > In article <3EE6C7F1.6020702@displaign.de>, > Martin Sauer <msau@displaign.de> wrote: > >>If I do a program and verify in one step the CPLD will be died. > > > Did you erase it first? >Article: 56665
I have to write the documentation for several designs. Is there a good method to include Modelsim waveforms into word-documents ? The cut-and-paste method doesnt work good, because the labels become unreadable when sizing the picture. I tried the evaluation-version of Timing Tool (www.timingtool.com) The disadvanteges are: I have to re-draw the waveform manually (maybe it is only lack of kwnowledge) and the tool is very expensive. Are there any tools that can do the job ? Thanks -Manfred Kraus makra_at_cesys_dot_comArticle: 56666
The smart move for Xilinx would be to release the source code for Impact so that this recurring problem can be addressed by the community. Krzysztof Szczepanski wrote: > Hello, > > Thanks to all for help. > > The details I have omitted are: > 1. I am using the Parallel Cable III > 2. I have a second chip in my jtag chain (VIRTEX XCV800-HQ240-4) > > The symptom for iMPACT is that the programming process dies at some > point in the process. > Disconnection of free running clocks did not help. > So, we have done a step back and installed the Xilinx Foundation 3.1i > with the jtagprogrammer. > That was it and now the programming process finishes OK. > > Regards, > KrzysiekArticle: 56667
Allan Herriman wrote: > > Connecting the (Fibonacci) LFSR internal state to a DAC in parallel > can be modeled as a 1 bit LFSR followed by an FIR filter. The FIR > filter taps are just the DAC bit weights. > > If you are shifting LSB to MSB, the impulse response is: > > 1/128, 1/64, ... 1/2, 1. > > If you are shifting MSB to LSB, the impulse response is: > > 1, 1/2, ... 1/64, 1/128, which is the time reversal of the other > impulse response (which means that the magnitude response is the same, > but the phase has been reversed). > > This response is equivalent to a single pole low pass filter. (If > that's what you actually wanted, it's much cheaper just to use a > single bit output of the LFSR and an RC LP filter.) > > > As the other posters said, this isn't the way to make a random voltage > generator. What are you actually trying to achieve? Thanks for all replies this far. A random voltage generator. With a variable clock, such as the LT6900, which can generate from 1kHz to 30MHz, and the property of the LFSR to have a spectrum between the clock and the clock divided by the number of bits, a system can be tested without a sweeper. Since there appears not to be a paper about parallel output of a LFSR, I'll run a PC simulation when time permits. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 56668
Hello, A big thanks to Paul Hartke for getting in touch with the solution to my problem. I had assumed that I could not debug these startup files because they were not being listed in the source files list taken from the elf headers but in fact a simple nexti with the right pc works fine. Cheers, Jon.Article: 56669
Hi philip and other's I saw in my *.PAR file as suggested by you on my message reply on google group. I find that I defined an input signal of 32 bits and I out of 32 bits I am sending data on first 18 bits rest of them will not used and it will remained zero. Also I am using 18 pin's and in my UCF file I already have commented rest of the pins which I will not used. Meaning out of 32 pins first 18 are uncommented and last 14 are commented. In my actual par file the actual pin assignment being done by PAR is amazingly only 7. This is shown below: Resolved that IOB <SR_DATA_IO<0>> must be placed at site P94. Resolved that IOB <SR_DATA_IO<1>> must be placed at site P96. Resolved that IOB <SR_DATA_IO<2>> must be placed at site P99. Resolved that IOB <SR_DATA_IO<3>> must be placed at site P101. Resolved that IOB <SR_DATA_IO<4>> must be placed at site P103. Resolved that IOB <SR_DATA_IO<5>> must be placed at site P107. Resolved that IOB <SR_DATA_IO<6>> must be placed at site P109. There is one warning is also occuring which is given below : par -w -ol 4 -xe 2 -d 4 ..\..\map.ncd routed.ncd ..top.pcf WARNING:Par:266 - The "-d" switch has been obsoleted. This switch will be ignored. Now in my par file there should be 11 more SR_DATA_IO's pin assignment but it's not there. My simulation result are working perfeclty according to the logic and I can see the correct output. But when I download this into the chip then the result are not according to the logic and now I understand that there is no proper pin assignemt done by PAR. You people are very much experinced in this field, could you please give me suggestion what's going wrong.Article: 56670
Hi philip and other's I saw in my *.PAR file as suggested by you on my message reply on google group. I find that I defined an input signal of 32 bits and I out of 32 bits I am sending data on first 18 bits rest of them will not used and it will remained zero. Also I am using 18 pin's and in my UCF file I already have commented rest of the pins which I will not used. Meaning out of 32 pins first 18 are uncommented and last 14 are commented. In my actual par file the actual pin assignment being done by PAR is amazingly only 7. This is shown below: Resolved that IOB <SR_DATA_IO<0>> must be placed at site P94. Resolved that IOB <SR_DATA_IO<1>> must be placed at site P96. Resolved that IOB <SR_DATA_IO<2>> must be placed at site P99. Resolved that IOB <SR_DATA_IO<3>> must be placed at site P101. Resolved that IOB <SR_DATA_IO<4>> must be placed at site P103. Resolved that IOB <SR_DATA_IO<5>> must be placed at site P107. Resolved that IOB <SR_DATA_IO<6>> must be placed at site P109. There is one warning is also occuring which is given below : par -w -ol 4 -xe 2 -d 4 ..\..\map.ncd routed.ncd ..top.pcf WARNING:Par:266 - The "-d" switch has been obsoleted. This switch will be ignored. Now in my par file there should be 11 more SR_DATA_IO's pin assignment but it's not there. My simulation result are working perfeclty according to the logic and I can see the correct output. But when I download this into the chip then the result are not according to the logic and now I understand that there is no proper pin assignemt done by PAR. You people are very much experinced in this field, could you please give me suggestion what's going wrong. Philip Freidin <philip@fliptronics.com> wrote in message news:<f3bcevct6t6kneae5hlc6r5gn1q2arbajc@4ax.com>... > On 9 Jun 2003 13:10:34 -0700, kalimuddin@hotmail.com (Muhammad Khan) wrote: > >Hi there , > > > >I am Khan and I have a problem regarding material suppiled by Xilinx. > > Ther is nothing wrong with the Xilinx "material". > > >I am using Xilinx FPGA Editor to view the placed route in actual > >hardware. The problem is the proper pin assignment. For example in my > >Constraint file I define signal X to pin 57 and when I observed that > >particular signal in the editor than I find that this signal is being > >placed at pin 107. > > The problem will be with the way you are specifying the constraint > in the constraint file, or whether the constraints are even being > read in. Either you have the syntax wrong, or you are not processing > the file correctly. The place and route process produces several] > report files. If there is a syntax error in your constraints, it will > be reporting an error, assuming that the constraint file was correctly > supplied. > > Constraints can come from many places .UCF, .NCF, .NGC (probably), and > via the EDIF files. These are all combined by NGDBUILD. > > The MAP phase creates an output file of <design-name>.PCF that has the > combined constraints. You should look at this file and see if your > constraint is in there, and if it is correct. Until this is correct, > there is no point in continuing. > > >I am using actual hardware to implement my design > >so I can not just download the code in to chip. > > Right. You need to get this right, or else you will damage things. > > Another file you will need to look at, and is much easier than the FPGA > editor (if all you want to do is check the pinout constraints) is to check > the <design-name>.PAD file that reports the actual pin assignments. This > is created by PAR. > > >The package I am using > >is HQ240 and device is Xilinx Vertex XCV600 with speed 4. I used all > >the above mentioned parameter in my project file. > > > >Does any body have any idea how to overcome this problem. > > See above. > > >Thanking you in advance. > > I hope this gets you to where you want to be. > > Philip Freidin > > > > Philip Freidin > FliptronicsArticle: 56671
"Manfred Kraus" <news@cesys.com> wrote: >I have to write the documentation for several designs. >Is there a good method to include Modelsim waveforms >into word-documents ? The cut-and-paste method doesnt >work good, because the labels become unreadable when sizing >the picture. Try the print-postscript/save-to-file feature. I don't know if Word can directly import ps files, in which case you'd need GSview and Ghostscript (free tools) to convert the file to eps or bitmap. -- Dave FarranceArticle: 56672
Hi there, Following my message on the google since last two days regarding probelm in pin assignemnt and constraint file.The following error occur previously while doing Ngdbuild using command line option. As in my previous message I said that my first 7 bits of the input signal are being assigned correctly and the rest are not. So the error is shown below for rest of the pins from 7 to 17. The error shows the same error for signal SR_DATA_IO<7> : Annotating constraints to design from file "../VIR3_top/VIR3.ucf" ... ERROR:NgdBuild:755 - Line 49 in '../VIR3_top/VIR3.ucf': Could not find net(s) 'SR_DATA_IO<7>' in the design. To suppress this error use the -aul switch, specify the correct net name or remove the constraint. Previously I used -aul switch and it work's properly. But in my actual imlpementation I was getting wrong result. Then when I see my *.par file then I came to know that there is no pin assignment of signal's from SR_DATA_TO<7 to 17>. I need to get rid of this error. What's your suggestion in this lieu. Regards KhanArticle: 56673
On 11 Jun 2003 04:08:05 -0700, kalimuddin@hotmail.com (Muhammad Khan) wrote: >Hi philip and other's > >I saw in my *.PAR file as suggested by you on my message reply on >google group. I find that I defined an input signal of 32 bits and I >out of 32 bits I am sending data on first 18 bits rest of them will >not used and it will remained zero. Also I am using 18 pin's and in my >UCF file I already have commented rest of the pins which I will not >used. Meaning out of 32 pins first 18 are uncommented and last 14 are >commented. In my actual par file the actual pin assignment being done >by PAR is amazingly only 7. This is shown below: >Resolved that IOB <SR_DATA_IO<0>> must be placed at site P94. >Resolved that IOB <SR_DATA_IO<1>> must be placed at site P96. >Resolved that IOB <SR_DATA_IO<2>> must be placed at site P99. >Resolved that IOB <SR_DATA_IO<3>> must be placed at site P101. >Resolved that IOB <SR_DATA_IO<4>> must be placed at site P103. >Resolved that IOB <SR_DATA_IO<5>> must be placed at site P107. >Resolved that IOB <SR_DATA_IO<6>> must be placed at site P109. >There is one warning is also occuring which is given below : >par -w -ol 4 -xe 2 -d 4 ..\..\map.ncd routed.ncd >..top.pcf >WARNING:Par:266 - >The "-d" switch has been obsoleted. This switch will be ignored. > >Now in my par file there should be 11 more SR_DATA_IO's pin assignment >but it's not there. My simulation result are working perfeclty >according to the logic and I can see the correct output. >But when I download this into the chip then the result are not >according to the logic and now I understand that there is no proper >pin assignemt done by PAR. >You people are very much experinced in this field, could you please >give me suggestion what's going wrong. So if some of your constraints work and others dont, you need to look VERY carefully at the constraint file you are supplying, and see what the difference is between the constraints that work, and the ones that dont. Maybe do some trial and error stuff. For example, re-assign some of the constraints that are working to the signals that are not working: do these signals now get assigned to the pins you have just specified. If not maybe you are not getting the signal name correct. Try the other way: for the signals that are being assigned correctly, change the pin number to one of the ones that isnt working. Does this work? if not, maybe the way you are enterin the pin number is wrong. You didn't tell us what you found in the PCF file. Did it have the constraints that you entered in the UCF??? if bot then you need to look at everything that comes from ngdbuild and map, to see why the constraints in your UCF are not getting to the PCF file that is written by map. Keep hacking, you will get it eventually. Philip Philip Freidin FliptronicsArticle: 56674
Thank you for your hint. When I try to print to postscript,
I get an error message. Do you know if "lp" has to be installed
seperatly ? Is it part of windows or part of Modelsim ?
Error Message:
# Trace back: Postscript write failed: couldn't execute "lp": no such file
or directory
# while executing
# "PrintWave -postscript -dialog -win .wave"
# (menu invoke)
# 2: tkerror {Postscript write failed: couldn't execute "lp": no such file
or directory}
# 1: bgerror {Postscript write failed: couldn't execute "lp": no such file
or directory}
"Dave Farrance" <davefarrance@yahooERASETHIS.co.uk> schrieb im Newsbeitrag
news:j05eevgd0dga7fsvt2k4d08njju6sbq102@4ax.com...
> "Manfred Kraus" <news@cesys.com> wrote:
>
> >I have to write the documentation for several designs.
> >Is there a good method to include Modelsim waveforms
> >into word-documents ? The cut-and-paste method doesnt
> >work good, because the labels become unreadable when sizing
> >the picture.
>
> Try the print-postscript/save-to-file feature. I don't know if Word can
> directly import ps files, in which case you'd need GSview and
> Ghostscript (free tools) to convert the file to eps or bitmap.
>
> --
> Dave Farrance
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z