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Rick, SpartanXL is still the best FPGA when it comes to quiescent leakage current. Most parts come in below 100 uA. We have customers who use the SpartanXL for applications where they need this extrememly low standby current. Note that we do not specify this current (as it is a low cost product, and leakage current is not supposed to be a limiting factor for yield). Also, don't forget startup current. SpartanXL has none, and Virtex II, II Pro, and Spartan 3 have no startup current that is any larger than the standby current. This can not be said for other FPGAs (from X as well as ....). Austin rickman wrote: > Iode wrote: > > > > Hi to everyone, > > > > Has anyone had experience porting a design from Acex to Cyclone? What should > > I expect from the point of view of power consumption? Using the calculator > > tools give worrying results: comparing a c30 with a 1k50 I have 33.5mA of > > standby current for Cyclone, 5 mA for Acex; I/Os consumption also seems to > > be higher in Cyclone; core consumption seems to be less but, all in all, am > > I going to need more or less power using Cyclone? > > > > Perhaps less power while the clock is running but more power when in > > stand-by? > > I am very glad you posted this question. I had been looking at using a > CPLD in this design for the PC/104 bus interface, but all of the parts I > was considering had limitations. But the ACEX 1K parts seem to meet all > the needs and are still relatively low power. 5 mA standby is better > than some of the CPLDs! I estimated a max power consumption of 40 mA > running at 50 Mhz so this part hangs in there with the CPLDs in terms of > dynamic power as well. > > If I can get a decent price, this part will solve a lot of my problems. > > BTW, I suggest that you call Altera support at 800-800-3753. I have > found them to be very helpful and they even answer the phone fairly > quickly. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56901
Sorry, I did not see the V. :-( You are looking for the XC2V6000, the next-to-largest member of the Virtex-II family. You find it at http://direct.xilinx.com/bvdocs/publications/ds031-1.pdf Peter Alfke ===================== Prashant wrote: > > Hi, > > I have been unable to find a data sheet for the XCV6000 device. Have I > got the number wrong ? Does such a device exist ? If so, where can I > find a data sheet for this device. > > Thanks, > PrashantArticle: 56902
Isaac wrote: > > Dear Fellows, > > I need help regarding two way data transfer using pin's as inout port > mode. I am trying to write VHDL code for read and write operation. > > 1) I want my code to do write operation using data bus into device > when particular address ( say X on the address bus)and signal > indicating to do write operation appears. > 2) I want to do read operation using the same data bus from device > when particular address ( say Y on the address bus) and signal > indicating to read appears. > To accomplish this I have defined data bus as inout port. There is a > read and write signal ( active low) along with the clock signal. > > WRITE: > > To start with I am just taking the signal (say INPUT) from DATA bus > storing in a internal signal ( say INTERNAL) during write operation. > Note: Both signal's have same width. > INTERNAL <= INPUT; > > READ : > And during read operation I am raeding the same stored signal ( which > is INTERNAL). For this I have just assigned > INPUT <= INTERNAL; > > Problem: > > The problem is that while writing everthing is fine. I can see in my > simulation INTERNAL signal contains the value on the DATA bus. But If > I change the signal values from write to read along with the read > address ( Y), then the INTERNAL signal is not being assigned to INPUT > ( data bus acting as inout port). > You can see my code which is giving below: > here case a when '1' then I am doing read operation: > ---------------------------------------------------------------------------- > > if Rising_Edge (Clock) then > case a is > when '0' => -- Write Operation > if Address = "11" then > INTERNAL <= INPUT; > end if; > when '1' => -- Read Operation > if Address = "01" then > INPUT <= INTERNAL ; > > end if; > when others => > Null; > end case; > ------------------------------------------------------------------------------ > Also I tried by assigning a constant value to INTERNAL and try to see > the result at the INPUT. But without any success. > > Does any one have any idea how to accomplish this task? You have shown us only a part of your code. It looks to me like you intend to infer an external tristate bus (INPUT) and an internal tristate bus. To do this you need to get the software to understand that the INPUT bus is a pin. Often the easiest way is to instantiate the IO buffers. The other issue is that you are doing this in a clocked process which will infer a register in each direction. Is that what you intended? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56903
"Isaac" <fpga_uk@yahoo.co.uk> wrote in message
news:889eb3fb.0306180657.15604106@posting.google.com...
> Dear Fellows,
>
> I need help regarding two way data transfer using pin's as inout port
> mode. I am trying to write VHDL code for read and write operation.
>
> 1) I want my code to do write operation using data bus into device
> when particular address ( say X on the address bus)and signal
> indicating to do write operation appears.
> 2) I want to do read operation using the same data bus from device
> when particular address ( say Y on the address bus) and signal
> indicating to read appears.
> To accomplish this I have defined data bus as inout port. There is a
> read and write signal ( active low) along with the clock signal.
>
>
> WRITE:
>
>
> To start with I am just taking the signal (say INPUT) from DATA bus
> storing in a internal signal ( say INTERNAL) during write operation.
> Note: Both signal's have same width.
> INTERNAL <= INPUT;
>
>
> READ :
> And during read operation I am raeding the same stored signal ( which
> is INTERNAL). For this I have just assigned
> INPUT <= INTERNAL;
>
> Problem:
>
> The problem is that while writing everthing is fine. I can see in my
> simulation INTERNAL signal contains the value on the DATA bus. But If
> I change the signal values from write to read along with the read
> address ( Y), then the INTERNAL signal is not being assigned to INPUT
> ( data bus acting as inout port).
> You can see my code which is giving below:
> here case a when '1' then I am doing read operation:
> --------------------------------------------------------------------------
--
>
> if Rising_Edge (Clock) then
> case a is
> when '0' => -- Write Operation
> if Address = "11" then
> INTERNAL <= INPUT;
> end if;
> when '1' => -- Read Operation
> if Address = "01" then
> INPUT <= INTERNAL ;
>
> end if;
> when others =>
> Null;
> end case;
> --------------------------------------------------------------------------
----
> Also I tried by assigning a constant value to INTERNAL and try to see
> the result at the INPUT. But without any success.
>
> Does any one have any idea how to accomplish this task?
>
> Rgds
>
> Isaac
Try something like this (which is over simplistic, but gives a general idea
of one way);
write_it: PROCESS(clk)
BEGIN
IF rising_edge(clock) THEN
IF read_write = [write] THEN
IF address = X THEN
register1 <= bus;
END IF;
END IF;
END IF;
END PROC;
read_it ; PROCESS(read, address, register)
BEGIN
IF read_write = [read] AND address = Y THEN -- could even be X address to
read back written register1
bus <= register2; -- or whatever you want to read
ELSE
bus <= (OTHERS => 'Z');
END IF
END PROC;
Article: 56904Amontec Team, Laurent Gauch wrote: > Steve Lass wrote: > >> The 3S50, 3S200 and 3S400 will be included in the 6.1i WebPACK (coming >> this Fall). Is this new WebPack going to run under Linux (at least, with Wine) I'm particularly interested in getting iMPACT there. Or, is there a functional iMPACT equivalent capable of programing at least SII devices (say Digilent boards).... lukasz >> John wrote: >> >>> Hello, >>> Does anyone know when Spartan3 devices other than the 50K will be >>> supported by ISE WebPack. Also, does anybody know what the largest >>> Spartan3 supported by the WebPack tools will be? >>> >>> Thanks >>> >>> >> > Nice feedback > > ------------ And now a word from our sponsor ------------------ > Do your users want the best web-email gateway? Don't let your > customers drift off to free webmail services install your own > web gateway! > -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ---- -- ------------------------------------------------------------------------- Lukasz Salwinski E-MAIL: lukasz@mbi.ucla.edu DOE-MBI Center for Genomics and Proteomics PHONE : 310-825-1402 UCLA, Los Angeles FAX : 310-206-3914 -------------------------------------------------------------------------Article: 56905
Austin Lesea wrote: > > Rick, > > SpartanXL is still the best FPGA when it comes to quiescent leakage current. Most > parts come in below 100 uA. We have customers who use the SpartanXL for > applications where they need this extrememly low standby current. Note that we do > not specify this current (as it is a low cost product, and leakage current is not > supposed to be a limiting factor for yield). > > Also, don't forget startup current. SpartanXL has none, and Virtex II, II Pro, > and Spartan 3 have no startup current that is any larger than the standby > current. This can not be said for other FPGAs (from X as well as ....). IIRC, SpartanXL is a 4000XL type chip. I would have concerns about the remaining lifetime of this part. Also, the pricing is way too high compared to the other devices available. Price is the problem I have with the Coolrunner parts too. They are priced ok up to 256 macrocells and then the price jumps like a polevaulter. Otherwise I would use the XCR3512XL. I am looking for a part below $20 and prefer below $15. The startup current is only a major issue with the Xilinx parts from what I have seen. The A parts I have looked at may have a higher startup current than the idle current, but it is not higher than the operating current I will be seeing. I can live with 200 mA while 2000 mA is not an option for this part. That is a big reason for waiting for the Spartan 3 rather than the Spartan 2E on the other FPGA. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56906
Rick, All true and accurate obsevations. SpartanXL has such a large following, that it is not going anywhere soon (ie it is fully supported for new designs). For example, we still support and manufacture the 3000A and 3100A FPGAs (although not recommended for new designs). Who else has support for designs that are this old? By Peter's IC time scale, these are ancient history! Have you looked at the small Virtex II parts recently (ie for price)? The 2V40, 2V80, 2V250 are all still there, and might be a good choice (no startup current)? Just because it is in the Virtex line doesn't automatically mean that it isn't used for volume or low cost applications. It was the intent of the APD group here to cover the smaller and higher volume applications with a more advanced product when we created the smaller Virtex II parts. As with any smaller geometry, the leakage is going up (fast), so I am beginning to think of Virtex II as something like "classic cola" which represents a really good price/performance/feature point in the FPGA space, and one that is hard to improve upon (but we never stop trying). Austin rickman wrote: > Austin Lesea wrote: > > > > Rick, > > > > SpartanXL is still the best FPGA when it comes to quiescent leakage current. Most > > parts come in below 100 uA. We have customers who use the SpartanXL for > > applications where they need this extrememly low standby current. Note that we do > > not specify this current (as it is a low cost product, and leakage current is not > > supposed to be a limiting factor for yield). > > > > Also, don't forget startup current. SpartanXL has none, and Virtex II, II Pro, > > and Spartan 3 have no startup current that is any larger than the standby > > current. This can not be said for other FPGAs (from X as well as ....). > > IIRC, SpartanXL is a 4000XL type chip. I would have concerns about the > remaining lifetime of this part. Also, the pricing is way too high > compared to the other devices available. Price is the problem I have > with the Coolrunner parts too. They are priced ok up to 256 macrocells > and then the price jumps like a polevaulter. Otherwise I would use the > XCR3512XL. I am looking for a part below $20 and prefer below $15. > > The startup current is only a major issue with the Xilinx parts from > what I have seen. The A parts I have looked at may have a higher > startup current than the idle current, but it is not higher than the > operating current I will be seeing. I can live with 200 mA while 2000 > mA is not an option for this part. That is a big reason for waiting for > the Spartan 3 rather than the Spartan 2E on the other FPGA. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56907
Just make sure that you compare worst-case X against worst-case A. Not typicals! This is an ugly parameter, make sure you get full and honest information from both manufacturers. Peter Alfke ========== rickman wrote: > > The startup current is only a major issue with the Xilinx parts from > what I have seen. The A parts I have looked at may have a higher > startup current than the idle current, but it is not higher than the > operating current I will be seeing. I can live with 200 mA while 2000 > mA is not an option for this part. That is a big reason for waiting for > the Spartan 3 rather than the Spartan 2E on the other FPGA. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56908
Lukasz Salwinski wrote: > Amontec Team, Laurent Gauch wrote: > >> Steve Lass wrote: >> >>> The 3S50, 3S200 and 3S400 will be included in the 6.1i WebPACK >>> (coming this Fall). >> > > Is this new WebPack going to run under Linux Not in the 6.1i release. Even though ISE will run on Linux, we will probably wait until 7.1 for the WebPACK. > (at least, with Wine) > I'm particularly interested in getting iMPACT there. It depends on which cable you are using. The parallel 3 and 4 cables will not run under Linux because the drivers are different. We haven't tested it yet, but serial cables (Multilinx) should work under Wine. The iMPACT gui should run on Wine as well. Steve > Or, is there > a functional iMPACT equivalent capable of programing at least SII > devices (say Digilent boards).... > > > lukasz > >>> John wrote: >>> >>>> Hello, >>>> Does anyone know when Spartan3 devices other than the 50K will be >>>> supported by ISE WebPack. Also, does anybody know what the largest >>>> Spartan3 supported by the WebPack tools will be? >>>> >>>> Thanks >>>> >>>> >>> >> Nice feedback >> >> ------------ And now a word from our sponsor ------------------ >> Do your users want the best web-email gateway? Don't let your >> customers drift off to free webmail services install your own >> web gateway! >> -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ---- > > >Article: 56909
Nagaraj wrote:
>
> Hello all,
> I have my prototype design in Spartan IIE 400K -7 device (package
> FT256). As our high volume application is power,size and cost
> oriented, we have to migrate to ASIC.
You should define this very carefully first.
High volume = ?? with what forecast probability ?
Power Oriented = Total Power budget / FPGA portion / Static / Operating
?
Size Oriented = Total product size, FPGA portion,
Size in FPGA offerings ? - is Smaller pin-count
possible in ASIC ?
Cost Oriented = Std bean counter mantra
What is selling cost, and FPGA portion ?
What is NRE amortize portion ?>
> Because of time crunch, we are not in a position to follow the entire
> ASIC design flow.
> I want you to suggest some alternatives. One alternative I have in
> mind is this. If Xilinx or 3rd party can take our FPGA design and map
> it to a one-to-one customized ASIC, we can save the time on ASIC flow
> and ASIC verification.
How, exactly ?. Most ASICs (should) have some form of FPGA test vehicle.
> What I mean is that start with the FPGA device
> and do these things:
> 1. Remove the unused dedicated resources as well as logic/routing
> resources (for example we are using only 5% of BRAMs. So all other
> BRAMs can be removed)
> 2. Remove IOBs of unused pins and keep only those pins which are in
> use (we are using only 30% of I/O pins.)
> 3. Change the packaging if possible.
>
> My question is whether this kind of service is available with XILINX
> or any other 3rd parties?
> If not could you suggest some other alternative?
Make sure you use the smallest possible FPGA resource.
- ie can a bump to the next faster/bigger processor reduce the FPGA
workload.
- Is your design truly optimum ? etc
If you really do have 'High volume' from a semiconductor companies
viewpoint,
then go and twist some arms.
Prices can do amazing things with volume :)
- jg
Article: 56910Austin Lesea wrote: > > Rick, > > SpartanXL is still the best FPGA when it comes to quiescent leakage current. Most > parts come in below 100 uA. We have customers who use the SpartanXL for > applications where they need this extrememly low standby current. Note that we do > not specify this current (as it is a low cost product, and leakage current is not > supposed to be a limiting factor for yield). Not sure I follow. Leakage should only impact yields if you set the bar in the wrong place ? If a MAX is specified, it's usually way above this, and I think most IC vendors use this anamolous leakage test as a failure indicator anyway. ( so it's probably ALREADY in the test process .. ) In most apps, leakage is used to calculate battery lifetimes, which is at best a 'waving wet finger in the air' exercise. Do not be scared to quoting a typical, and give some simple histogram plots, as is quite common in analog vendors devices. Show the designers HOW it varies with TEMP and Voltage, and clearly state typical only. This should be a 'carefull typical', so not derived from a single device :) but a general average from a few wafer lots. If you have 'good fab lines' and 'not so good lines', the typical should be from the poorest one. I have seen test-lot figures from other digital IC vendors, and they have surprisingly process-tight leakage values - tho that of course varies on your fab :) -jgArticle: 56911
Hello, what is the best way for an FPGA to access data in order to process an image? When doing signal processing with processors, data are usually stored on ram (sd-ram or equivalent). But with FPGA, this seems to be an issue or at least data need to be re-ordered or scheduled to be accessed by an FPGA. Have you any links or good advices to understand this subject ? I understand well ram organization and synthesis on FPGA. It's only the interaction between the two that I need to investigate. thanks a lot, ErwanArticle: 56912
Jim, Good points. Typically there is no variation (mature product, fab line, etc.). But there are occasional lots with higher values (shorter gates, much much faster) and we don't wish to be penalized and not able to ship them as the slowest speed grade (if we have orders). Austin Jim Granville wrote: > Austin Lesea wrote: > > > > Rick, > > > > SpartanXL is still the best FPGA when it comes to quiescent leakage current. Most > > parts come in below 100 uA. We have customers who use the SpartanXL for > > applications where they need this extrememly low standby current. Note that we do > > not specify this current (as it is a low cost product, and leakage current is not > > supposed to be a limiting factor for yield). > > Not sure I follow. > Leakage should only impact yields if you set the bar in the wrong place > ? > > If a MAX is specified, it's usually way above this, and I think most IC > vendors use this anamolous leakage test as a failure indicator anyway. > ( so it's probably ALREADY in the test process .. ) > > In most apps, leakage is used to calculate battery lifetimes, which is > at best a 'waving wet finger in the air' exercise. > > Do not be scared to quoting a typical, and give some simple histogram > plots, > as is quite common in analog vendors devices. > Show the designers HOW it varies with TEMP and Voltage, and clearly > state > typical only. > > This should be a 'carefull typical', so not derived from a single device > :) > but a general average from a few wafer lots. If you have 'good fab > lines' > and 'not so good lines', the typical should be from the poorest one. > > I have seen test-lot figures from other digital IC vendors, and they > have > surprisingly process-tight leakage values > - tho that of course varies on your fab :) > > -jgArticle: 56913
I've gone through the process of defining my CR-II inputs as
SCHMITT_TRIGGER, yet the fitter report proclaims
"WARNING: Cpld:965 - Ignoring SCHMITT_TRIGGER design property on invalid
net 'sw1_ibuf'. SCHMITT_TRIGGER applies to input pads only." What's more,
it issues each of these warnings twice, in two lists, one right after the
other.
Now, I've carefully specified each of these nets to be an input, and I
definitely want them to be SCHMITT_TRIGGERed.
What's going wrong here?
thanx,
--
regards,
Richard Erlacher
Principal Engineer
id Communications
Article: 56914I've found that ISE v5.2.03 is apparently producing an erroneous netlist for a 4-bit shift register. This happens both for a discretly implemented one, using the FD (no enable, preset, or clear) or the SR4CE library element, with its enable hooked to Vcc and its clear stroked once at the outset of the testbench. It shows evidence of an erroneous netlist both in the fitter report and in the simulation waveform. Is there a way of finding out why this is occurring and of fixing it? thanks, -- regards, Richard Erlacher Principal Engineer id CommunicationsArticle: 56915
So could a Spartan IIe 300K be used to create a graphics processor (GPU Only) for a homebrew console on par with like a 16 Bit SuperNintendo (SNES) ? Or for that matter could any FPGA board under $1000 give this kind of performance or could they even do better? Thanks. On Wed, 18 Jun 2003 10:44:31 +0200, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: > >"Bazaillion" <nospam@nospam.org> schrieb im Newsbeitrag >news:kjcvevsik67eb2nhs2vdkl4bbgi1084gm3@4ax.com... >> I forgot to add "With exteral Ram for the Video." > >www.fpgaarcade.com > >I rebuilded these pacman with a 200k Spartan-II. What it needs are two >external FLASH memories for program and character storage. But if you have >plenty of BRAMS, you can integrate at least on of the two ROMs. >You also need some small adaptors for VGA, audio and joystick. But this is >just some bell wire on a breadboard.Article: 56916
Why the use of a Mictor Connector? In the past, I've used them in conjuction with a termination pack to interface the connector to a logic analyzer -- in this case you need to make sure the FPGA of choice can drive the termination load. Prashant wrote: > Hi, > > Problem Definition: > FPGA 1 on board 1 will be driving its output through a Mictor > connector (male) to board 2's Mictor connector (female) and then to > FPGA 2 on board 2. > > Do FPGAs have the drive capability for such a connection OR will I > need to find a way to buffer this ? How about APEX20K1500E > specifically ? > > Thanks, > PrashantArticle: 56917
Here is what I learned: Based on idle-current measurements of the Spartan3-50 and -1000 (the -50 has 1536 LUTs and flip-flops, the -1000 has 15,360 LUTs and f-fs) The -50 has a typical Icc0 for the core of 50 mA, and 75 mA for Iccaux The -1000 has a typical Icc0 for the core of 150 mA, and again 75 mA for Iccaux. The core uses 1.2 V, Vccaux is 2.5 V. These idle-current measurements were taken at room temperature, and they are not guaranteed max values. Peter Alfke ======================== Peter Alfke wrote: > > ok, give me a day to collect some data. > The bad new is that there is a big difference between typical and > worst-case, like 1:10, plus temperature dependence. > I'll get back to you before there is any panic... > > Peter Alfke > > Jim Granville wrote: > > > > rickman wrote: > > > > > > Peter Alfke wrote: > > > > > > > > I don't like to be the harbinger of bad news, but these are > > > > industry-wide facts, and the user community has to face them, even > > > > though it hurts. > > > > (Have you heard of 80 W in a 3 GHz Pentium, and many watts of idle current?) > > > > This is not your father's CMOS anymore... > > > > > > Can you give us any idea of what to expect for idle current on the > > > Spartan 3 chips? I am looking at using one in a not-so-high current > > > application (at a low clock speed). I can't make any sort of an > > > analysis since there is no power consumption data available (at least in > > > the April data sheet). I am just looking for an order of magnitude, > > > nothing I will use as a fixed number. Are we talking 10's of mA or > > > 100's of mA? > > > > A few are waiting on replies to this, and the silence/delays > > suggests the news is 'not good' ? > > The Pentium has been used more than once as a reference point, > > also not a good sign.. > > > > Present devices are 10's of mA, so we could start an informal > > 'canteen sweepstake' on if this will go over 100mA :) > > My 5c goes on 125mA....( or should I say 150mW ? ) > > [ Place your educated guess here ] > > > > -jgArticle: 56918
Hi, I am looking at validating a Digital filter implemented on Xilinx FPGAs. I would like to know more about the implmentation procedure. The task is two-fold: 1.Implementing a digital filter on Xilinx FPGAs 2.Validating the hardware implementation with its frequency response. Any inputs in this regard will be helpful.Thanks, Regards, MadhuraArticle: 56919
There is leakage current, and then there is leakage current... In the distant past, leakage current was usually the current through a reverse-biased junction or diode, and any good process allowed very low leakage current at room temperature. Microamps of leakage were a sign of something fishy, and the part was (or should be) rejected. Now we have something called sub-threshold leakge current. It is a current that takes the normal, legitimate path from source to drain through a transistor that is supposed to be turned off by a high enough gate voltage. Trouble is, the available gate voltage does not exceed the threshold enough to really turn the transistor off. So there are several nanoamps of current, sub-threshold leakage current, but NOT reverse-biased diode leakage current. And it is not an indication of poor processing. With millions of transistors even in our small chips, this current takes on undesirable proportions, but there is nothing we or you can do about it. Of course you can always buy the older more conservative 0.25 and 0.35 micron parts that can turn off their transistors perfectly... High-performance sub-micron CMOS cannot have low idle current. Peter AlfkeArticle: 56920
If you have a feedback mechanism to adjust the delay, you could build a delay line
out of LUTs and tap (or bypass parts of it) the delay line with a mux type
arrangement. That should work out well with your desired 2.3ns resolution. It
would be much cleaner than diddling the VCC, and would keep it all digital.
You'll probably have to hand-route the delay line to make sure the routing doesn't
spoil your queue. For finer resolution you can use the carry chains as the delay
line. Feedback to dynamically adjust the delay line is desirable to keep
variations due to process, voltage and temperature in check.
Jim Granville wrote:
> Andras Tantos wrote:
> >
> > >>How much delay skew do you need ? - it might be cleaner to
> > >>apply the same idea to an external tiny-logic gate, where the
> > >>Vcc range can be wider, and there is no Vcc/Gnd competing noise
> >
> > The problem there is that the interface levels are tied to the VCC while the
> > Xilinx FPGA has different VCCIO and VCCINT voltages. The delay I need is in
> > the 30-40ns range total but I would like to have taps at each 2-3ns point.
>
> That's relatively coarse, by modern device standards.
> If you can tolerate quantize jumps, of this order, then
> a simple digital multi-tap delay line should do ?
> If the circuit self-centers, (by the phase comp action)
> then the temp/batch/routing variations are taken care of.
> -jg
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56921Steve Lass <lass@xilinx.com> wrote: : Lukasz Salwinski wrote: :> Amontec Team, Laurent Gauch wrote: :> :>> Steve Lass wrote: :>> :>>> The 3S50, 3S200 and 3S400 will be included in the 6.1i WebPACK :>>> (coming this Fall). :>> :> :> Is this new WebPack going to run under Linux : Not in the 6.1i release. Even though ISE will run on Linux, we will : probably wait until 7.1 for the WebPACK. Okay, wine still needed. :> (at least, with Wine) :> I'm particularly interested in getting iMPACT there. : It depends on which cable you are using. The parallel 3 and 4 cables : will not run under Linux because the drivers : are different. We haven't tested it yet, but serial cables (Multilinx) : should work under Wine. The iMPACT gui : should run on Wine as well. Steve, any chance that Xilinx delivers the Linux Windriver with webpack or in any other way? That way I could write an indirection layer in Wine, that accepts the Windows IOCTRL and resubmits them to the Linux kernel as Linux IOCTRLs?(*) I would resubmit to CVS wine... Bye (*) Despite that: The concept of "Windriver" is totally broken from a security point of view. E.g. with the parport/ppdev device, on Linux there is a generic and transparent way to handle the parallel port without breaking all seciurity. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56922
Austin Lesea wrote: > > Rick, > > All true and accurate obsevations. > > SpartanXL has such a large following, that it is not going anywhere soon (ie it is fully > supported for new designs). > > For example, we still support and manufacture the 3000A and 3100A FPGAs (although not > recommended for new designs). Who else has support for designs that are this old? By > Peter's IC time scale, these are ancient history! > > Have you looked at the small Virtex II parts recently (ie for price)? The 2V40, 2V80, > 2V250 are all still there, and might be a good choice (no startup current)? Thanks for the ideas. I guess I had forgotten that the startup current was fixed in the XC2V parts. Sometimes it is hard to keep it all straight. But they require 1.5 volt power which is not present in that part of the board. The board has three separate power zones and this one has 5, 3.3 and 2.5 volts. I don't really want to add another regulator. Also 65 mA typ Iccintq is not so low. I am trying to keep the total FPGA power to about 50 mA or less. But the main problem is the price. Unless the web pricing is way out of whack, I can't afford $80 for the XC2V250 which I need to get the IO count. The Coolrunner starts lower than that and I still have not been able to get disti prices to my $20 target. The XC2V40 is really tiny and the XC2V80 is only a bit better. > Just because it is in the Virtex line doesn't automatically mean that it isn't used for > volume or low cost applications. It was the intent of the APD group here to cover the > smaller and higher volume applications with a more advanced product when we created the > smaller Virtex II parts. That sounds good to me, but the prices are way up there still. The XC2V40 might have some applications, but I can't use it at $25. > As with any smaller geometry, the leakage is going up (fast), so I am beginning to think > of Virtex II as something like "classic cola" which represents a really good > price/performance/feature point in the FPGA space, and one that is hard to improve upon > (but we never stop trying). I know it is hard to make much money on the smaller, low cost parts. But those are what most of our boards need. The XC3S400 fits our needs because of the IO count, not the slice count. For our needs it is actually large by any other measure. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56923
Peter Alfke wrote: > > Just make sure that you compare worst-case X against worst-case A. Not typicals! > This is an ugly parameter, make sure you get full and honest information > from both manufacturers. > Peter Alfke > ========== > rickman wrote: > > > > The startup current is only a major issue with the Xilinx parts from > > what I have seen. The A parts I have looked at may have a higher > > startup current than the idle current, but it is not higher than the > > operating current I will be seeing. I can live with 200 mA while 2000 > > mA is not an option for this part. That is a big reason for waiting for > > the Spartan 3 rather than the Spartan 2E on the other FPGA. Yes, Altera does not spec this in the data sheet for all their parts. But I called and pointedly asked for the max over temp, etc. They say this was the number, but they are double checking and I expect an answer in writing. 200 mA is about the max I can tolerate. The cap switcher I am using is rated at 250 mA and there is very little else to draw power. But I definitely don't want to push the power issue. That can be a real bear to debug and I don't think I have many options without going to an inductor, (out of room). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56924
Hello, Yes, you most certainly can do that. You could probably fit that, as well as a Xilinx Microblaze processor in the part you're talking about. You'd end up with a small game system on a chip. I find the projects to re-implement existing games very interesting, although I haven't tried any yet. I think I will. My primary hobby interest is to see if I can build my own console, and write my own games for it. If you are thinking about doing similar work, I would be interested to hear from you directly. Feel free to email me privately. Thanks, Eric Bazaillion wrote: > > So could a Spartan IIe 300K be used to create a graphics > processor (GPU Only) for a homebrew console on > par with like a 16 Bit SuperNintendo (SNES) ? > > Or for that matter could any FPGA board under $1000 give > this kind of performance or could they even do better? > > Thanks.
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