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Hello guru's I was wondering if anyone has ever attempted a phase lock loop in digital before (specifically VHDL). I'm looking for some examples or pointers on trying to build one for a low frequency range of 200 Hz to 200 kHz. I would appreciate any comments or suggestions. Google didn't get me very far, so if you know of any app notes, etc. please let me know. Thanks, JasonArticle: 56826
Jim Granville wrote: > > rickman wrote: > > > > Peter Alfke wrote: > > > > > > I don't like to be the harbinger of bad news, but these are > > > industry-wide facts, and the user community has to face them, even > > > though it hurts. > > > (Have you heard of 80 W in a 3 GHz Pentium, and many watts of idle current?) > > > This is not your father's CMOS anymore... > > > > Can you give us any idea of what to expect for idle current on the > > Spartan 3 chips? I am looking at using one in a not-so-high current > > application (at a low clock speed). I can't make any sort of an > > analysis since there is no power consumption data available (at least in > > the April data sheet). I am just looking for an order of magnitude, > > nothing I will use as a fixed number. Are we talking 10's of mA or > > 100's of mA? > > A few are waiting on replies to this, and the silence/delays > suggests the news is 'not good' ? > The Pentium has been used more than once as a reference point, > also not a good sign.. > > Present devices are 10's of mA, so we could start an informal > 'canteen sweepstake' on if this will go over 100mA :) > My 5c goes on 125mA....( or should I say 150mW ? ) > [ Place your educated guess here ] When you say "present devices" are you talking about the Virtex II parts? Or do you mean the very preliminary CES Spartan 3 chips? The VII parts seem to range from 50 to 300 mA for typical values and TBD to 1100 mA for max quiescent Iccintq. I know that transistor leakage goes up as the feature size goes down, but I'm not clear if the smaller total die area is a factor as well. So in general, I would guess that it will only go up from the VII numbers. I noticed that the VII Iccauxq is not insignificant at about 10% of the Iccintq. But with the much higher voltage, it will be about 20 to 25% of the total quiescent power. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56827
ok, give me a day to collect some data. The bad new is that there is a big difference between typical and worst-case, like 1:10, plus temperature dependence. I'll get back to you before there is any panic... Peter Alfke Jim Granville wrote: > > rickman wrote: > > > > Peter Alfke wrote: > > > > > > I don't like to be the harbinger of bad news, but these are > > > industry-wide facts, and the user community has to face them, even > > > though it hurts. > > > (Have you heard of 80 W in a 3 GHz Pentium, and many watts of idle current?) > > > This is not your father's CMOS anymore... > > > > Can you give us any idea of what to expect for idle current on the > > Spartan 3 chips? I am looking at using one in a not-so-high current > > application (at a low clock speed). I can't make any sort of an > > analysis since there is no power consumption data available (at least in > > the April data sheet). I am just looking for an order of magnitude, > > nothing I will use as a fixed number. Are we talking 10's of mA or > > 100's of mA? > > A few are waiting on replies to this, and the silence/delays > suggests the news is 'not good' ? > The Pentium has been used more than once as a reference point, > also not a good sign.. > > Present devices are 10's of mA, so we could start an informal > 'canteen sweepstake' on if this will go over 100mA :) > My 5c goes on 125mA....( or should I say 150mW ? ) > [ Place your educated guess here ] > > -jgArticle: 56828
Jason Berringer wrote: > > Hello guru's > > I was wondering if anyone has ever attempted a phase lock loop in digital > before (specifically VHDL). I'm looking for some examples or pointers on > trying to build one for a low frequency range of 200 Hz to 200 kHz. I would > appreciate any comments or suggestions. Google didn't get me very far, so if > you know of any app notes, etc. please let me know. > > Thanks, > > Jason I once worked on a DPLL that was part software. We had a data stream that contained samples at a nominal 8 kHz rate. We wanted to play them back at the rate they were sampled. We constructed an NCO which could be adjusted to +- a few Hz resolution. The sample buffer was counted after each block was uploaded. If it deviated from a defined value the NCO was adjusted a number of steps defined by the deviation. Now that I look at what I just wrote, I guess this is a Frequency Locked Loop instead of a PLL. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56829
Jason Berringer wrote: > > Hello guru's > > I was wondering if anyone has ever attempted a phase lock loop in digital > before (specifically VHDL). I'm looking for some examples or pointers on > trying to build one for a low frequency range of 200 Hz to 200 kHz. I would > appreciate any comments or suggestions. Google didn't get me very far, so if > you know of any app notes, etc. please let me know. Look for 74HC297. Also, if you have clock ratio to burn, an insert/swallow scheme can give a good jitter-average/LPF. Usually, you are using a PLL to phase align and/or reject bad samples, or reduce jitter. eg Divide by 127/128/129 where 128 represents locked, and 127/129 are move left/move right. Phase detect can be two or three level. Three level takes 128 as 'hold' state, and only does a 127/129 when it drifts enough to kick a response. -jgArticle: 56830
Well, it's no big deal for me to find the entire file in a MS-DOS/FAT formatted disk. However, the area i am not 100% clear is how the bits are formatted from 'byte' in FAT to 'bit' in the stream, for example, the LSB/MSB, endianism, and issues which i don't know, etc... Is there a document in Xilinx discussing this? Thanks. Kelvin pagercam@yahoo.com (Mark Sandford) wrote in message news:<aabba8bf.0306161200.41a21e6a@posting.google.com>... > I have been thinking about doing something similar, I see three > solutions : > > 1) Don't use MS-DOS, use a raw disk disk/file editor and place data > sector by sector this allows you to specify the exact location you > want to use, but if you want easy access from PC and want to have > other files this may not be an option. > > 2) Have software on the uP that can can read the directory and find > the file and of course read the file. This is the most flexiable but > requires the most software look for FreeDos via google which is a open > source clone of MS-DOS that has file system code available port that > code to your uP and you're done. > > 3) If there is some easily identifyable data at the begining of the > file you could search the disk for that data or append data to the > front of the file to act as a flag of the file start. > > "Kelvin @ Clementi" <cobraxu@singnet.com.sg> wrote in message news:<bckelg$sm9$1@reader01.singnet.com.sg>... > > I learnt that it's fairly easy to download an FPGA with a microprocessor, > > from the > > datasheet of a PROM. My question is, if the bit-stream file is stored in a > > Window > > formatted disk. My uP can only read out the bitstream byte by byte. > > How do I associate these bytes with the serial bit-stream we see in the > > EPROM's > > datasheet? > > > > Kelvin.Article: 56831
The easiest solution is to turn off "verify" in Impact. Personally, I've never been able to verify a Xilinx FPGA. Ed Stevens wrote: > Hi, > > Im trying to program a Spartan 2E using the XILINX 4.2i software and iMPACT. > When I tell iMPACT to program the device I get the following error: > > > Device #1 selected > PROGRESS_START - Starting Operation. > Validating chain... > Boundary-scan chain validated successfully. > ERROR:Bitstream:2 - The input bitstream file > "C:\Xilinx\ISEexamples\intro\intro.msk" is not in the specified location. > Please check the correct location of the file. If the .bit file was not > created consult the "BitGen" Section in Chapter Twelve of the Development > System Reference Guide for the appropriate command-line options to create a > bitstream file or consult the "Implementation Options" Section of the Design > Manager/Flow Engine Reference/User Guide for Configuration Template > Settings. > ERROR:iMPACT:123 - Mask file C:\Xilinx\ISEexamples\intro\intro.msk is > invalid. > PROGRESS_END - End Operation. > Elapsed time = 2 sec. > => > > > Anyone got any ideas on what im doing wrong? In the XILINX Project > Navigator I've generated the programming file without any errors. > > Thanks for any help, > > > -- Marc Guardiani To reply directly to me, use the address given below. The domain name is phonetic. fpgaee81-at-eff-why-eye-dot-netArticle: 56832
Depends on the video decoder's PLL. The Phillips NTSC decoder has too
much jitter and will cause the DLL to unlock. Some of the others are
better in that regard.
rob d wrote:
> Does anyone know whether a spartan 2e DLL can lock to a video clock
> and multiply it by 2. The video is from a PAL/NTSC camera about 3
> meters away so I'm hoping that the video decoder will output a very
> stable clock.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56833In article <pan.2003.06.16.22.46.11.992789.12401@freeby.mesanet.com>, Peter C. Wallace <pcw@freeby.mesanet.com> wrote: >I dont think its much as it just seems to be folded into the SM assembly >cost at least for the cards we do, certainly no more than a few dollars. >If you had to do it separately it would be more... Also, given an FPGA on the board, much/all of the board functionality can be tested using the FPGA, which would include BGA short/gap detections etc. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 56834
Thanks that works great now! cheers, Jamie Morken "Leon Heller" <leon_heller@hotmail.com> wrote in message news:bcje1d$s2o$1@sparta.btinternet.com... > > "Jamie Morken" <truespace1@hotmail.com> wrote in message > news:z%6Ha.235070$Vi5.6216826@news1.calgary.shaw.ca... > > Hi, > > > > I have a xilinx 9536 CPLD ISP demo board with a parallel cable III. I am > > using webpack with VHDL. I am trying to program the chip with a my simple > > design but I get this error: > > "Error: impact: 583 - the idcode read from the device does not match the > > idcode in the bsdl file" > > > > My chip is a couple years old, does this error mean there is some damage > to > > the chip? I am new to > > webpack so am not sure of what I'm doing yet! :) > > > > I had this problem, also. > > The WebPack Impact software doesn't work with the older 9536, you will have > to download the earlier programming software from the Xilinx web site (JTAG > programmer 3.3WP8.x). I sent a msg to the group about it a year or so ago. > > Leon > -- > Leon Heller, G1HSM > leon_heller@hotmail.com > http://www.geocities.com/leon_heller > >Article: 56835
hi, > First, which do you want, a Mux-DFF, or a DFF with enable (which is what you > describe in the code - sort of...) I want to implement Mux-DFF only.(without using the LUT resources..) > As you have described it, you have asked the synthesis tool to infer a 2-1 > MUX and then connect the output to a FF, however if you had instead coded (I > will use Verilog, but it is the same...) > always @(posedge clk) > begin > if (se) > begin > d <= sin > end > end > In this code 'd' is being used as output, but in my case 'd' is input. Your code won't result as Mux-DFF. I have verified in the Xilinx Library manual...I couldn't locate any library element which is equivalent to Mux-DFF... Any inputs are welcome... Thanks, Valli. > what you have encoded is a DFF with enable. All Flip-Flops in the Virtex > architectures have enables, and hence this can be implemented without any > LUTs. A good synthesis tool SHOULD be able to realize that a 2-1 MUX > connected to the D of a flop, with one of the two inputs being the Q of the > same flop can be converted to a FF with enable, but it might not always do > so... > > AvrumArticle: 56836
On 16 Jun 2003 18:49:43 -0700, kelvin_xq@hotmail.com (Kelvin Tsai @ Singapore) wrote: >Well, it's no big deal for me to find the entire file in a MS-DOS/FAT >formatted disk. > >However, the area i am not 100% clear is how the bits are formatted >from 'byte' in FAT to 'bit' in the stream, for example, the LSB/MSB, >endianism, and issues which i don't know, etc... > >Is there a document in Xilinx discussing this? > >Thanks. >Kelvin Several articles in the FAQ should help. Try these, and the articles they link to. http://www.fpga-faq.com/FAQ_Pages/0006_The_Bit_Stream.htm http://www.fpga-faq.com/FAQ_Pages/0026_Tell_me_about_bit_files.htm http://www.fpga-faq.com/FAQ_Pages/0028_Downloading_a_Bitstream_under_Linux.htm Philip Freidin Philip Freidin FliptronicsArticle: 56837
"Antonio Pasini" <pasini.a@tin.it> wrote in message news:<XwoHa.99165$pR3.2133465@news1.tin.it>... > "rob d" <rjd@transtech-dsp.com> ha scritto nel messaggio > news:e44f5c31.0306160647.530d6b28@posting.google.com... > > Does anyone know whether a spartan 2e DLL can lock to a video clock > > and multiply it by 2. The video is from a PAL/NTSC camera about 3 > > meters away so I'm hoping that the video decoder will output a very > > stable clock. > > I'm doing exactly that in my last design. Using a 27 Mhz clock output of a > video decoder (Micronas VPX3226), and multiply internally by two to get a 54 > Mhz clock for SDRAM. > > Works very well, so far. Great news. I need the *2 for exactly the same reason you do. I'll look to see if the output jitter from a Micronas VPX3226 is better than the SAA7110 that I had in mind. RobArticle: 56838
On 16 Jun 2003 22:48:48 -0700, sri_valli_design@hotmail.com (Valli) wrote: > >I want to implement Mux-DFF only.(without using the LUT resources..) The only muxes in the CLB that feed the D pin of the flip flops are controlled (input selection) by configuration bits, so their selection is static, per the configuration. What you are asking for is going to need to use a LUT to implement the mux. An example application where this occurs a lot is when you are implementing a scan chain. Note though, that if that is what you are trying to do, then this is a nearly pointless task. Scan chains within a design (as opposed to just the I/O in JTAG) is for gaining better visibility/coverage for manufacturing production test. This is not needed for designs in FPGAs, as the devices that you have will have already passed manufacturing test. >I have verified in the Xilinx Library manual...I couldn't locate any >library element which is equivalent to Mux-DFF... The library manual is the wrong place to look, as it is a mixture of macros and primitives. The definitive answer is the detailed logic diagram of the CLB in the data sheet. It shows you what the resources really are, and allows easy analysis of what is possible and what is not. Another good resource is the FPGA editor, which also gives detailed CLB capabilities, as well as routing details. >Any inputs are welcome... You are welcome. >Thanks, >Valli. Philip Freidin Philip Freidin FliptronicsArticle: 56839
"Peter C. Wallace" <pcw@freeby.mesanet.com> wrote in message news:<pan.2003.06.16.22.46.11.992789.12401@freeby.mesanet.com>... > On Mon, 16 Jun 2003 15:16:56 -0700, Patrick MacGregor wrote: > > > Does anyone here have any guestimates or general rules-of-thumb used to > > figure the cost of Xray inspection for a BGA part on a PCB? > > > > Here's the scenario: We are designing a board and can choose between > > inexpensive Cyclone FPGAs in the 240-pin TQFP, or we could move to a > > Stratix in the 672 BGA. The Cyclone in question costs under $30. The > > Stratix costs ~$230. > > > > Without going into excessive detail, if I use Cyclone, I need more > > expensive external CDR + SERDES. Stratix would allow me to use cheaper > > external CDR + SERDES due to it's higher I/O speeds. > > > > In order to decide which solution is ultimately most cost-effective, I > > need to have some feel for what the added cost of Xray inspection of the > > BGA part would be. Assume one component per board, board size = about > > 7" x 9" and 6 layers. > > > > I'm assuming that the cost is somewhat fixed, regardless of board > > quantity, as you have to do the same amount of work on each board -- > > quantity 1 or 1000. > > > > Thanks, > > > > PMac BGA's really aren't the problem many people think it is. We are happily using a ERSA infra-red rework station to place xc2v8000 -5's (gues how many K dollars a piece) which are 1152 pin. We've placed about 25. Also placed about 75 xc2v3000/xc2v6000 also 1152, one or two which we re-balled in house. We haven't x-rayed yet, but we have a lot of experience with JTAG. Our main customer is one of the big telco's and they are happy that we haven't XRAYed. They are also happy that in production we don't XRAY, allthough that will be through a proper oven. If it's your first design with BGA then I'm not going to get you to not x-ray but I suggest that when you start thinking "why are we xraying" after getting your yields much higher than a pqfp you realize that many companies don't. RobArticle: 56840
Hello everyone. I would like to automatically perform a series of tests on my design. For each test, I need to change the input to the design, run the test, and examine the output. I can implement the testing logic in VHDL and run everything under my VHDL simulator, but there is a major problem with that. Every time I ran an exceptionally long VHDL simulation, my computer crashed. I'm using quite a strong server, so I don't think the problem is in the computer. I'm assuming that the long VHDL simulation simply "ate up" all of my system's memory. The only solution I can see, is to implement the input generation and output examination in software, and call the VHDL simulator on each test at a time. Does anyone know a better solution to the long VHDL simulation problem? Thanks, Gilad.Article: 56841
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3EE10E28.70F61B36@xilinx.com>... > Eric, > > Absolutely correct. But you also need to examine what the probability of > actually affecting the design is. > 90% of the memory cells are not even > used in a customer pattern, so if only 1 in 10 memory cells is used for > something that matters, then the probability that you hit that one cell is > of course, 10 times less likely. > Is it really the case that in a "full" FPGA you can toggle (slowly) 90% of the config SRAM without interacting with the design. I can easily believe that only 10% have been set but surely setting an unused bit will have an effect. > See Peter & my article "1000 years between Singel Event Upsets" on our > website. > > Just type that into google. It is the number one "hit" -- pun intended. > > Austin > > Eric Smith wrote: > > > Colin Marquardt <c.marquardt@alcatel.de> writes: > > > You might want to be careful here. If this RAM stores data that is > > > rarely refreshed, over the course of several days or weeks, it could > > > still be that your data is corrupted due to environmental influences > > > like radiation. Be pessimistic. > > > > If you've using a small number of BRAMs and a lot of logic cells, I'd > > expect there to be a higher probability of an SEU in a logic cell, for > > which parity is not, in general, going to help.Article: 56843
Hi Bill, Thanks. But, I've tried. When I did that .. The process failed in bitgen stage. Best regards. Basuki -----Original Message----- From: Bill Hanna [mailto:billh40@aol.com]=20 Posted At: Monday, June 16, 2003 11:34 PM Posted To: fpga Conversation: Xilinx Mapping Problem Subject: Re: Xilinx Mapping Problem "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> wrote in message news:<F9gz9T8MDHA.2420@exchnews1.main.ntu.edu.sg>... > I have the following error message in mapping stage. Anybody know how=20 > to encounter this error messages ? >=20 > ERROR:MapLib:32 - lut4 l symbol "iRD/iCMA0" (output > signal=3DiRD/iCMA0/O) > has an > equation that uses an input pin connected to a trimmed signal. Make > sure that > all the pins used in the equation for this LUT have signals that are > not > trimmed (see trim report for details on which signals were trimmed). >=20 > Thanks. >=20 > Basuki Keren >=20 > Ps: I am using ISE 5.1i I received that message in ISE 4.2, 5.2. =20 Solution: Go to Implement Design right click on properties select Map properties disable TRIM UNCONNECTED SIGNALS (REMOVE CHECK) Close properties Then re-run Implement Design The design will pass MAP. Report the problem to Xilinx as a web case. Bill HannaArticle: 56844
"Christian Widtmann" <e0125145@student.tuwien.ac.at> writes: > "Martin Thompson" <martin.j.thompson@trw.com> schrieb im Newsbeitrag > news:uptleeajt.fsf@trw.com... > > You've got most of the way there - you just need to put a to_X01() > > translation between your bus pin and the logic that uses it. This > > will convert the 'H' on the bus from the 'pull-up-resistor' to a '1' > > that the logic can use. > > Where would I have to put this? Into the original VHDL-code or into a file > generated by synopsis' design_analyzer? > Depends on which file you want to simulate - start in the original VHDL files and get that bit working forst. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 56845
Given this construct
always @(posedge CLK or posedge RST) begin
if(RST || crrst) begin
mst <= 0;
end else if(en1) begin
mst <= 1;
end
end
the current XST barfs about not matching "known FF".
XST is happy with this equivalent construct
always @(posedge CLK or posedge RST) begin
if(RST) begin
mst <= 0;
end else if(en1 || crrst) begin
mst <= !crrst;
end
end
Is this the least ugly alternative?
Article: 56846Hello, we want to realize a controller for Sharp LM641542 (or LM641541, 640x480 passive monochrome VGA display) in a Spartan2 FPGA. Has anybody any experience, sources (VHDL, schematic, Program sources...), links to existing projekts or other helpful information??? Thanks for help, with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 56847
Hi Jason! > I was wondering if anyone has ever attempted a phase lock loop in digital > before (specifically VHDL). Riad Stefo, Jörg Schreiter, Jürgen Dohndorf, and René Schüffny. A Portable All-Digital Phase-Locked Loop for Frequency Synthesis. In 9th International Conference, Design of Integrated Circuits and Systems (MIXDES'02), pages 217-222, June 2002. I'm not sure, if they working on it up to now. The last thing I knew is, that a test-run in a fab was successful. I do not have any direct links. Further links: German (!) Website of the authors: http://www.iee.et.tu-dresden.de/iee/hpsn/ It was a cooperative project with http://www.ipms.fraunhofer.de/ Ralf I'm not involved into this project.Article: 56848
Rob, The simple answer, yes. The long answer is that the ratio went from 1:10 to 1:80 over a suite of designs. This was work done by two separate universities, that agreed with our tests that we had done in the lab, and in the beam. By the way, we are live at White Mountain Rsearch Center, Barcroft Station with another group of 100 2V6000's. Acceleration factor is ~26, so we expeft to see upsets every 2 to 3 days at this altitude. So far, we are seeing exactly what the "theory" predicts for altitude. Austin rob d wrote: > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3EE10E28.70F61B36@xilinx.com>... > > Eric, > > > > Absolutely correct. But you also need to examine what the probability of > > actually affecting the design is. > 90% of the memory cells are not even > > used in a customer pattern, so if only 1 in 10 memory cells is used for > > something that matters, then the probability that you hit that one cell is > > of course, 10 times less likely. > > > Is it really the case that in a "full" FPGA you can toggle (slowly) > 90% of the config SRAM without interacting with the design. I can > easily believe that only 10% have been set but surely setting an > unused bit will have an effect. > > > See Peter & my article "1000 years between Singel Event Upsets" on our > > website. > > > > Just type that into google. It is the number one "hit" -- pun intended. > > > > Austin > > > > Eric Smith wrote: > > > > > Colin Marquardt <c.marquardt@alcatel.de> writes: > > > > You might want to be careful here. If this RAM stores data that is > > > > rarely refreshed, over the course of several days or weeks, it could > > > > still be that your data is corrupted due to environmental influences > > > > like radiation. Be pessimistic. > > > > > > If you've using a small number of BRAMs and a lot of logic cells, I'd > > > expect there to be a higher probability of an SEU in a logic cell, for > > > which parity is not, in general, going to help.Article: 56849
Dear Peter:
Opencores has two VGA designs. One is in the PCI Bus chip source code
testbench. www.opencores.org
"Peter Seng" <p.seng@seng.de> wrote in message
news:bcn3dl$10b$1@online.de...
> Hello,
>
> we want to realize a controller for Sharp LM641542 (or LM641541, 640x480
> passive monochrome VGA display) in a Spartan2 FPGA. Has anybody any
> experience, sources (VHDL, schematic, Program sources...), links to
existing
> projekts or other helpful information???
>
> Thanks for help,
>
> with best regards,
>
> Peter Seng
>
>
> #############################
> SENG digitale Systeme GmbH
> Im Bruckwasen 35
> D 73037 Göppingen
> Germany
> tel +7161-75245
> fax +7161-72965
> eMail p.seng@seng.de
> net http://www.seng.de
> #############################
>
>
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