Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Jens Nowack" <its.me.hates-spam@uni.de> wrote in message news:<bbpi2g$c80fu$1@ID-192450.news.dfncis.de>... > Hallo, > > I have a clock e.g.: s_asck and a delayed clock: s_asck_delay > > s_asck_delay <= s_asck after 50ns; > > q1<=s_asck; > q2<=s_asck_delay; > > When I simulate it with Quartus II the two graphs show the same > characteristics. But the Output q2 should be delayed 50 ns to q1. > How can I show it in Quartus II correctly? Howdy Jens, Remember that when doing HDL: *think hardware* Based on what you know or can figure out about the Altera architecture from the data sheet, what is there that would produce such an exact delay? Good luck, MarcArticle: 56501
Eric, Absolutely correct. But you also need to examine what the probability of actually affecting the design is. > 90% of the memory cells are not even used in a customer pattern, so if only 1 in 10 memory cells is used for something that matters, then the probability that you hit that one cell is of course, 10 times less likely. See Peter & my article "1000 years between Singel Event Upsets" on our website. Just type that into google. It is the number one "hit" -- pun intended. Austin Eric Smith wrote: > Colin Marquardt <c.marquardt@alcatel.de> writes: > > You might want to be careful here. If this RAM stores data that is > > rarely refreshed, over the course of several days or weeks, it could > > still be that your data is corrupted due to environmental influences > > like radiation. Be pessimistic. > > If you've using a small number of BRAMs and a lot of logic cells, I'd > expect there to be a higher probability of an SEU in a logic cell, for > which parity is not, in general, going to help.Article: 56502
Hi all, We are a fabless company and are interested in outsourcing hardware verification. Am asking the question in this newsgroup as was not sure where to post it. What I am interested in knowing is that what could be outsourced, where do I find companies who can do it for low price (India/china maybe ???) and what are the going rates. We are working with TSMC in Taiwan as our foundry. Thanks in advance for your help -pooArticle: 56503
Colin Marquardt <c.marquardt@alcatel.de> writes: > You might want to be careful here. If this RAM stores data that is > rarely refreshed, over the course of several days or weeks, it could > still be that your data is corrupted due to environmental influences > like radiation. Be pessimistic. DEC had a problem with unreliable RAM chips used for the control store of the KS10 processor, a low-end PDP-10 used in the DECSYSTEM-2020. They added parity to the control store, and on a parity error, the main processor would shut down. The console processor (8080-based) would then reload the microcode from disk and restart the main processor, which would continue as if nothing had happened. This is the subject of U.S. Patent 4,231,089.Article: 56505
Hi Matt,
First, it's a good idea to report these sort of problems via the
mysupport.altera.com web site. You're more likely to get an answer on
Altera-specific issues via the web site than on this group.
That said, I asked a colleague who is responsible for the HDL compiler about
this; the short answer is that this is illegal in Verilog 2001, but probably
legal in Verilog 1995. The long answer is as follows:
It is illegal in Verilog 2001 (which is the default in Quartus). Here's an
excerpt from the Verilog 2001 LRM, section 4.1.14:
Another form of concatenation is the replication operation.
The first expression shall be a non-zero,non-X and non-Z
constant expression,the second expression follows the rules
for concatenations.This example replicates "w" 4 times:
{4{w}} // This is equivalent to {w, w, w, w}
a[31:0] = {1'b1, {0{1'b0}} }; //illegal.
However, the Verilog 1995 Language Reference Manual says nothing more than
that the replication multiplier (which just to be different from the 2001
LRM it calls the repitition multiplier) must be a constant expression - so
in theory {-3{w}}} is legal! On this basis, we allow 0 in Verilog 1995 mode,
but not in 2001 mode as it is very clearly disallowed by the LRM.
If you pull up the Quartus on-line help page associated with this error, you
should find this problem described.
To rectify the problem, you can either:
(a) switch to 1995 mode (Assignments->Settings->Verilog HDL Input Settings)
or
(b) make the code 2001-legal.
Regards,
Paul Leventis
Altera Corp.
"Matt Ettus" <matt@ettus.com> wrote in message
news:e8fd79ea.0306061329.792ab52f@posting.google.com...
> I have the following verilog code which gets flagged as an error in
> quartus, but not in Icarus --
>
> {{shift{yi[bitwidth-1]}},yi[bitwidth-1:shift]}
>
> "shift" is a parameter, and the error gets flagged only when it is
> equal to zero. Quartus says "replication multiplier must be positive.
>
> I'm pretty sure this is legal verilog.
>
> Matt
Article: 56506
Whoops -- jumped the gun on this one. In Quartus II 2.2, the case where the
replication multiplier is 0 is treated as illegal in both 2001 and 1995
modes. As of Quartus II 3.0 (which will be released at the end of the
month), we have relaxed the treatment under Verilog 1995 mode to accomodate
HDL from concerned customers (such as you!)
So for now, you'll just have to change your HDL.
Regards,
Paul Leventis
Altera Corp.
"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message
news:3zbEa.21660$j9%.7600@news04.bloor.is.net.cable.rogers.com...
> Hi Matt,
>
> First, it's a good idea to report these sort of problems via the
> mysupport.altera.com web site. You're more likely to get an answer on
> Altera-specific issues via the web site than on this group.
>
> That said, I asked a colleague who is responsible for the HDL compiler
about
> this; the short answer is that this is illegal in Verilog 2001, but
probably
> legal in Verilog 1995. The long answer is as follows:
>
> It is illegal in Verilog 2001 (which is the default in Quartus). Here's an
> excerpt from the Verilog 2001 LRM, section 4.1.14:
>
> Another form of concatenation is the replication operation.
> The first expression shall be a non-zero,non-X and non-Z
> constant expression,the second expression follows the rules
> for concatenations.This example replicates "w" 4 times:
> {4{w}} // This is equivalent to {w, w, w, w}
>
> a[31:0] = {1'b1, {0{1'b0}} }; //illegal.
>
> However, the Verilog 1995 Language Reference Manual says nothing more than
> that the replication multiplier (which just to be different from the 2001
> LRM it calls the repitition multiplier) must be a constant expression - so
> in theory {-3{w}}} is legal! On this basis, we allow 0 in Verilog 1995
mode,
> but not in 2001 mode as it is very clearly disallowed by the LRM.
>
> If you pull up the Quartus on-line help page associated with this error,
you
> should find this problem described.
>
> To rectify the problem, you can either:
> (a) switch to 1995 mode (Assignments->Settings->Verilog HDL Input
Settings)
> or
> (b) make the code 2001-legal.
>
> Regards,
>
> Paul Leventis
> Altera Corp.
>
> "Matt Ettus" <matt@ettus.com> wrote in message
> news:e8fd79ea.0306061329.792ab52f@posting.google.com...
> > I have the following verilog code which gets flagged as an error in
> > quartus, but not in Icarus --
> >
> > {{shift{yi[bitwidth-1]}},yi[bitwidth-1:shift]}
> >
> > "shift" is a parameter, and the error gets flagged only when it is
> > equal to zero. Quartus says "replication multiplier must be positive.
> >
> > I'm pretty sure this is legal verilog.
> >
> > Matt
>
>
Article: 56507In article <66c23f42.0306060731.6180ea01@posting.google.com>, SAF <safahmy@hotmail.com> wrote: > Hi, > > I've been trying for days to get the Xilinx 1024point FFT core working > in the Single Memory Space configuration. I get answers, but they > don't match MATLAB at all. I do get a peak for a sine-wave, but its a > few samples to the left of the one in MATLAB, and I don't get a second > peak. But if I create a random vector of 1024 complex numbers (of > fixed aplitude, eg. 32-32i, 32+32i...) it gies comeletely different > answers. I'm not worried about the amplitudes, just the signs (using > for OFDM demodulation). Has anyone used this core? I've used the > CoreGen blockram thingy, is that okay? It's a Virtex II. I've attached > my code, sorry it's quite long. I really would appreciate any help, as > I'm running to a deadline. Nothing specific about the Xilinx FFT but-- In FFTs there are various differences in the order the data come out (e.g. bit reversal), the normalization (dividing by N), etc. You may want to try running a series of sine waves through your FPGA with 1,2,3... cycles per 1024 samples and looking at where the peak ends up and what its magnitude is. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 56508
Eric Smith wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > If even the BaseX system does not support devices beyond 3S200, I guess > > we can expect Webpack support to be pretty short for a long time to > > come, no? > > > > I really don't understand the idea behind not supporting the full > > Spartan3 line in the *paid for* tools. I know BaseX is not expensive, > > but what is the rational behind *NOT* supporting any devices in the paid > > for tools? > > To encourage you to pay *more*. I probably should have worded it differently. I guess I miss the concept behind supporting nearly all of the Spartan II parts even in the *free* Webpack tools, but not all of the Spartan 3 devices. After all, they are targeted to the same market where cost is the main concern. It just seems odd that they would not fully support the entire Spartan 3 line in even the lowest priced *paid for* tools. To some people, that would push them over to a competitor. In our case, this may be a consideration since it gives a large advantage to the people who buy our boards if they can try their own FPGA development with out having to invest in tools. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 56509
>Tests show that the rate of upsets (soft errors) in a 2V1000 BRAM is one >every 800 years at sea level in San Jose..... > >Weeks? Days? come on! > >Do you have a nuclear reactor door open somewhere? 800 years looks like a long time, but is it long enough? [Are we being paranoid enough?] Consider a design where you install 1000 units. Now we are down to one failure per year. Suppose that system runs 24x7 and is supposed to be reliable and that the software guys get their act together so it actually does run for a long time. That means they are serious about making it work so they investigate every crash and glitch that they find. If that RAM is in a critical section, say holding microcode for a disk controller, the fan could get real dirty from a single bit error, and people could spend a lot of time trying to track down that sort of bug. Thanks for doing the work to collect and publish some solid data. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 56510
Hi, I'm am looking to license a great synthesis toolset suitable for ambitious fpga projects utilizing the largest Actel Flash and Fuse chipsets. (not interested in sram based architectures). We will be using sun ultrasparc boxes and avoiding microsoft where we possibly can. So, how you would _you personally_ rank the following tools for synthesis support for the ProAsic Plus and Axcelerator family? What do you feel the pro's and con's of the various tools are? And what is your experience level with them? :-) Also, could you point out if any of the tools have support for Async (delay) based circuits. Actel designer (obviously a basic reference point) Cadence BuildGates Cadence BuildGates Extreme Synopsys FPGA Compiler II Synplicity Synplify Synplicity Synplify Pro other Any other constructive advice is always welcome! (such as best simulation tools, etc) If you don't have experience with actel in particular, i am still interested in your experiences. Thanx. Ben GittinsArticle: 56511
I have not done this my self, but I think Orcad should be able to recognise the xxx.pin file created by the Quartus software. If you import this pin file into orcad you should get the I/O specification into your design. BenArticle: 56512
Looking for a logical anayzer (a pod connected to a PC via USB or printer port), Any recommendations?Article: 56513
QBA hal-pc wrote: > Looking for a logical anayzer (a pod connected to a PC via USB > or printer port), Any recommendations? Take a look at the Ant8 at http://www.rockylogic.com -- Morris Dovey West Des Moines, Iowa USA C links at http://www.iedu.com/cArticle: 56514
Morris Dovey wrote: > QBA hal-pc wrote: > > Looking for a logical anayzer (a pod connected to a PC via USB > > or printer port), Any recommendations? > > Take a look at the Ant8 at http://www.rockylogic.com The Ant16 (same page) is worth a look, too. -- Morris Dovey West Des Moines, Iowa USA C links at http://www.iedu.com/cArticle: 56515
"QBA hal-pc org>" <bwang<ATDOT> schreef in bericht news:3ee1cb35$0$54853$a726171b@news.hal-pc.org... > Looking for a logical anayzer (a pod connected to a PC via USB or printer > port), Any recommendations? > > ??? Elektor published the design of a logic analyzer that is controlled by the serial interface. In he Dutch version it was the februari issue. pieterArticle: 56517
In article <3ee1cb35$0$54853$a726171b@news.hal-pc.org>, "QBA" <bwang<AT> hal-pc<DOT>org> says... > Looking for a logical anayzer (a pod connected to a PC via USB or printer > port), Any recommendations? I have to say that I'm constantly amazed by the (apparently) broadly-held misconception that the PC is the answer to so many test equipment needs. One thing before I start; I'm venturing into territory I don't often use. I would appreciate corrections from others in the group if I screw something up. Anyway: The maximum possible bandwidth for a USB port is 12Mb/s (that's megaBITS, not bytes). Dividing that by 8 (assuming 8 bits per byte) gives us 1.5 megaBYTES per second, which (for the sake of discussion) can be considered equivalent to 1.5 MHz. This means that, if you assume a bus width of 8 bits being monitored simultaneously (most logic analyzers I've seen are parallel- input devices), your USB-connected "pod" would top out at 1.5 MHz, or just a bit more than 1/100th the speed of a typical PC's microprocessor clock. The parallel port? Assuming a high-end (read: not something you find on a typical motherboard) dedicated parallel port card on the PCI bus, your top end would be around 3-5 MHz. A little better than USB, but still pathetic in terms of what a dedicated analyzer can do. Here's my recommendation for you. Poke around at whatever ham radio/electronic swap meet(s) or electronic surplus places are local to you, and on Ebay as well, for an older Tektronix or HP logic analyzer. I think you'll find that a dedicated-purpose instrument will be a much better choice, and the older stuff is plenty cheap. For Tektronix, check around for a 1240 or 1241 series. Even with the low-speed cards, they're good to at least 50MHz. With the high-speed cards, they're good to 100. For HP, the late-model 16xxx series would probably do just fine. Good hunting. -- Dr. Anton Squeegee, Director, Dutch Surrealist Plumbing Institute. (Known to some as Bruce Lane, KC7GR, Owner and Head Hardware Heavy, Blue Feather Technologies -- http://www.bluefeathertech.com) kyrrin a/t bluefeathertech dot c=o>m (Reassemble to use). "Raf tras spintern. Raf tras spoit." (Keith Laumer, "The Galaxy Builder")Article: 56518
Dr. Anton Squeegee <SpammersAreVermin@dev.nul> writes: > Anyway: The maximum possible bandwidth for a USB port is 12Mb/s > (that's megaBITS, not bytes). Dividing that by 8 (assuming 8 bits per > byte) gives us 1.5 megaBYTES per second, which (for the sake of > discussion) can be considered equivalent to 1.5 MHz. This is only the speed of transferring the sample buffer over to the PC for display. Acquisition speed is totally unrelated to that. Even the 'dedicated' logic analyzers don't sample into the memory of their CPUs. Many (most?) 'dedicated' logic analyzers are just PCs (or 'workstations') anyway. For the hobbyist, the problem with the Ant8 or Ant16 is likely not the speed. It can sample at 500 Mhz (but the trigger logix is slower I think). But it can only store about 2000 or 3000 samples in its buffer, which might be a little tight. (And of course the low numer of channels.) But I do agree with your recommondation. If you can get a used analyzer for the same amount, you might get more channels and/or more memory. But probably not more speed. -- GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3 331E FAF8 226A D5D4 E405Article: 56521
"Jon Elson" <jmelson@artsci.wustl.edu> schrieb im Newsbeitrag news:3EE1039E.5080404@artsci.wustl.edu... > Did you actually make the 74HC14 and RC change on a cable, and see it work > reliably on the same computer where it was marginal before? Yes. I used a ORIOGINAL Parallel cable III, which did not work on one computer (but did on another). So I builded my modified version (with 3m cabel between POD and parallel connector) and it works fine. Looks like this Parallel cable was designed by a lazy intern . .. .;-)) -- Regards FalkArticle: 56522
"David Kinsell" <kinsell@poboxyz.com> schrieb im Newsbeitrag news:6kdEa.891727$Zo.202680@sccrnsc03... > I've seen multiple computers where the P-III cable would not > load a Spartan part through JTAG, but just tacking the small cap > on TCK fixed the problem. Totally fair side-by-side comparison. > > I doubt that it really needed low-pass filtering. Signal quality I've > looked at has always been extremely clean, full amplitude, text-book > quality, not a hint of ringing or other noise. I expect the cap on the HA!!! Did you REALLY measure it, or just hooked up a probe?? OK, no bad things to see, must be clean. NOOO!!! This is not high speed probing. As I said, the JTAG port is (unfortunately) as fast as all other IOs, this means, TCK can "see" glitches and spikes on the TCK line, which are only some (means here less than two or three) nanoseconds wide. To see such a glitch, you need at least a 300 MHz scope, better have 500 MHz++ and a damm good probe. NO, a classic 10:1 probe will most probably not do the trick. Even more, it will load the TCK line with 8..12 pF, wich can cause the problem to disapear. Removing the probe (and so the 8..12 pF) can restore the problem. > clk line added a bit of delay, which is what really did the trick. The > Schmitt triggers would be another way of adding a bit of delay. I > think there's a bug somewhere in the system related to setup time. The schmitt-triggers are cheap and bullet-proof. And a fully academic recognized solution ;-) -- MfG FalkArticle: 56523
"Dr. Anton Squeegee" <SpammersAreVermin@dev.nul> schrieb im Newsbeitrag news:MPG.194babd24173f0a99898ed@192.168.42.131... > Anyway: The maximum possible bandwidth for a USB port is 12Mb/s > (that's megaBITS, not bytes). Dividing that by 8 (assuming 8 bits per > byte) gives us 1.5 megaBYTES per second, which (for the sake of > discussion) can be considered equivalent to 1.5 MHz. How about local RAM on the Logic analyzer?? All the USB/Serial Connetion must do is to control some settings and to copy the local, fast tracking memory content to the PC for evaluation. Would this work?? ;-) > This means that, if you assume a bus width of 8 bits being > monitored simultaneously (most logic analyzers I've seen are parallel- > input devices), your USB-connected "pod" would top out at 1.5 MHz, or > just a bit more than 1/100th the speed of a typical PC's microprocessor > clock. > > The parallel port? Assuming a high-end (read: not something you > find on a typical motherboard) dedicated parallel port card on the PCI > bus, your top end would be around 3-5 MHz. A little better than USB, but > still pathetic in terms of what a dedicated analyzer can do. Not everyone needs a ferrari. Even a few kwords can be very usefull. -- Regards FalkArticle: 56524
> I have to say that I'm constantly amazed by the (apparently) >broadly-held misconception that the PC is the answer to so many test >equipment needs. ... > Anyway: The maximum possible bandwidth for a USB port is 12Mb/s >(that's megaBITS, not bytes). Dividing that by 8 (assuming 8 bits per >byte) gives us 1.5 megaBYTES per second, which (for the sake of >discussion) can be considered equivalent to 1.5 MHz. ... The bandwidth of the link to the PC isn't the critical factor. You can solve that with buffering out at the device. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z