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Hal, I already said, that for the 24x7 folks, there are well known, and already used techniques, and cores, that take care of the issue. In fact, I would suggest that our FPGAs are the only technology capable of performing these functions, which leads to an interesting thought: how are CPUs, ASIC's and ASSP's going to deal with this issue? If they do nothing, then they will be the most likely cause of failures. In our FPGAs, we are already capable of hardened uP soft cores, ECC, and now soft error detection and correction. Combine that with the selective use of TMR, and other techniques, and I challenge you can not design a robust fail safe system any other way (using a single chip). Austin Hal Murray wrote: > >Tests show that the rate of upsets (soft errors) in a 2V1000 BRAM is one > >every 800 years at sea level in San Jose..... > > > >Weeks? Days? come on! > > > >Do you have a nuclear reactor door open somewhere? > > 800 years looks like a long time, but is it long enough? > [Are we being paranoid enough?] > > Consider a design where you install 1000 units. Now we are down > to one failure per year. > > Suppose that system runs 24x7 and is supposed to be reliable and > that the software guys get their act together so it actually does > run for a long time. That means they are serious about making it > work so they investigate every crash and glitch that they find. > > If that RAM is in a critical section, say holding microcode for > a disk controller, the fan could get real dirty from a single > bit error, and people could spend a lot of time trying to > track down that sort of bug. > > Thanks for doing the work to collect and publish some solid data. > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.Article: 56551
I am starting a new project and yet again I have hit the usual documentation wall with XILINX. Historically Xilinx documentation assumed that you definitely wanted gate size X and gave you a table with "Internal IO number" down the left column followed by n columns of pin names for each package size. Which complete twit thought that this is how we do design. Presumably "customer feedback" has made Xilinx realize that most of us start with X number of IO and then decide which package gives us our "ideal plus or minus one gate size". Xilinx now provide a table per package with pin number down the first column and function for each gate size down the following columns. They have nearly got it right with spartan 3 excell pinouts. Sorry to rant and rave but I am about to spend the afternoon squinting at lots of little dots in the V2PRO user guide (the composite pinout diagram) so that I can work out which banks to put: A ttl which doesn't need impedance control, B ttl which does(needs vrn,vrp), C HSTL (needs vref, vrn,vrp), D ttl clocks and E HSTL clocks. Our warketing people want to know the options for an FF1152 & an FF1157 package so I have to do it twice. I am about to make a table with different types of IO down the first column and 8 more columns (one for each bank). Am I the only person that has to do this (it took a day with VirtexE) or worst still is there a table somewhere that has been hiding from me?Article: 56552
"Kyle Davis" <kyledavis@nowhere.com> wrote in message news:CPTEa.475$7H6.47184948@newssvr13.news.prodigy.com... > I am looking for Xilinx FPGA Development Board that has these features. > 1. The board has several empty sockets. Each sockets support different > family of Xilinx FPGA family. > 2. If you want to test drive your design, you need to plug in the FPGA chip > to one of the socket. Once your design is completely correct, you just need > to unplug it, put it to your own board, wire-wrap it, and connect it to a > PROM so it will be ready to be programmed each time you turn your board on. > > So, can anyone help me to find this development board? Most the board that I > have seen has their FPGA chip soldered to the board. I don't like that! I > want to have the flexibility of putting the FPGA chip to my own system. > > Thanks in advance! > > Hendra > Hi, There is no difference between the FPGA that you test on your development board and a second FPGA that you would use in your prototype. As you mention, you still have to connect it to a PROM, and the PROM determines the FPGA's behaviour. So why not just buy two FPGA's, and save yourself al lot of hassle with swapping IC's ? Maybe you'd be better of with a small PCB that contains an FPGA, oscillator, PROM and JTAG connector, which you could easily plug into your system. I think someone mentioned such a board in the thread "I want a 800kgates FPGA in a 40-pin DIL", but the only thing I found back was this : http://www.quickcores.com/ Hope this helps, MarcArticle: 56553
Dave Farrance <davefarrance@yahooERASETHIS.co.uk> wrote in message news:<loi8evkhe5h3dvmkjqhk82f2oaaplt5igr@4ax.com>... > Hi. > > I'm trying to find information and approximate prices for the Insight > Spartan-II PCI Development Kit and its options. > > It seems that the original Insight website has been replaced and > reorganised by Memec, so a web-search for the kit turns up a load of > broken links. Memec's site search engine seems particularly useless. > > If anybody could suggest a suitable web resource, I'd be grateful. the Memec PCI kit is 250$ in US or 275$ in europe it makes sense to buy at least one P160 proto board as well ($80) there are not many similar options at all - most FPGA-PCI boards have some PCI bridge on it, also it seems that 5V PCI support is vanishing under PLD/FPGA silicon - Spartan II is possible one of the last options! (dirct 5v PCI support without level conversion). if your budget allows then the best option is avnet new Virtex II Pro board it has Virtex II Pro and Spartan IIE 300 as PCI bridge :) price from 1500 to 2900 depending on virtex II Pro device selected. www.mesanet.com look in price list there is "5I20" this is also one options the cheapest and has lots of connectors for IO the docu is not online, must ask for it. anttiArticle: 56554
A quick trip through google and the Xilinx web pages did not
disclose the interface description between the Parallel Cable IV
and the PC Parallel port. With the III version, they gave schematics,
which is enough information for third parties to write sofware to
run the dumb thing. Now that the IV schematics are "proprietary",
I need documentation on the host-side interface. While the data
sheet covers the chip-side quite nicely, it totally omits the
host-side, assuming that everyone will use the captive and
non-embeddable Xilinx programming software.
Can anyone from Xilinx forward me that the interface description?
Or has someone else already reverse engineered it?
- Larry
Article: 56555
Dear Priyal:
If the layout part of VLSI design interests you, look at what Tim
Edwards is doing with Magic 7.2 at
http://bach.ece.jhu.edu/~tim/programs/magic , download the source code and
see how it works.
Charles
"Priyal" <priyal1977@yahoo.com> wrote in message
news:ccbb3738.0306051934.243ecbd8@posting.google.com...
> Thanks Rickman and kumaran for your suggestions.
> Rickman, i looked through that website, and found some interesting topics.
> Let me know if u have some other websites too.
>
> Thanks,
> Priyal
>
Article: 56556In article <ccbb3738.0306051934.243ecbd8@posting.google.com>, Priyal <priyal1977@yahoo.com> wrote: >Thanks Rickman and kumaran for your suggestions. >Rickman, i looked through that website, and found some interesting topics. >Let me know if u have some other websites too. An interesting platform is the Charmed Labs xport board (www.charmedlabs.com) A Spartan II 50, 16 MB of SDRAM, 4 MB flash, which couples to a Gameboy advanced. I asked them, and it should be possible to get a board with a Spartan II 150 instead. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 56557
Andras Tantos <andras_tantos@yahoo.com> wrote: : Hi! : I have a crazy FPGA application idea for which I need precise timing inside : the FPGA. My thought was to create a delay line of a couple of CLBs inside : the chip, and measure the phase difference between it's input and output : outside the chip. Using this as an error signal I can control the VCCINT : regulator to keep the phase-shift (and consequently the speed of the FPGA) : under control. I plan to use Xilinx Spartan 2E as the device, but I guess : the technique can be used with almost any FPGA. So, my question is, how : much the delay of a CLB is depending on the supply voltage? Where can I : find (if any) documentation on this? How far can I deviate from the nominal : VCCINT value without damaging the device? (the datasheet says 1.8V+-5% in : my case, but also specifies 1.5V as the data retention limit) How constant : is the delay over the entire chip? I mean, if I measure the delay of CLB A, : will CLB B at the other side of the chip have the same delay? Has anybody : done something like this, any recommendations? You only control one aspect of delay: gate delay. The other ascpect is routing delay, which is substantial too and you don't have any influence. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56558
as the title Richard He email: hfwbvcom@163.comArticle: 56559
Benjamin Gittins wrote: > > I'm am looking to license a great synthesis toolset There may not be any "great" ones. > suitable for > ambitious fpga projects utilizing the largest Actel Flash and Fuse > chipsets. (not interested in sram based architectures). Consider the flash APAxxx family. BGA sockets are problematic with large fuse devices. > So, how you would _you personally_ rank the following tools for > synthesis support I've only used Synplify and Leonardo. I expect either would work fine for you. Leonardo covers up to APA1000. > Any other constructive advice is always welcome! (such as best > simulation tools, etc) modelsim and aldec are good HDL simulators. This is where you will spend most of your design time. Consider evaluating these first. > If you don't have experience with actel in particular, i am still > interested in your experiences. I used an ACT2 fuse part on a project about ten years ago. The parts worked fine, but we burnt through several rails of them during system debug. -- Mike TreselerArticle: 56560
Hello, I modeled my system in Xilinx System Generator and Matlab (using floating then fixed point blocks). I found I need to divide a 31 bits number by a 24 bits number and need to retain a 44 bit result consisting of an 8 bits representing the integer result and 38 bits the fractional part. I tried using the Xilinx pipelined divider core but it only handles 32 bit remainder or fraction. Anybody have any idea where I can get a core or should I try to code this thing from scratch (extremely painful)? Thanks in advance. SalmanArticle: 56561
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >Dave Farrance <davefarrance@yahooerasethis.co.uk> wrote: >: Hi. > >: I'm trying to find information and approximate prices for the Insight >: Spartan-II PCI Development Kit and its options. > >: It seems that the original Insight website has been replaced and >: reorganised by Memec, so a web-search for the kit turns up a load of >: broken links. Memec's site search engine seems particularly useless. > >: If anybody could suggest a suitable web resource, I'd be grateful. > >for the refernce designs try >http://legacy.memec.com/solutions/reference/xilinx It's for the support of existing kit owners. They ask for a kit serial number, and making one up doesn't work. Thanks anyway. -- Dave FarranceArticle: 56562
I would use the frequency of a ring oscillator, since a frequency can be measured with very high accuracy. But: You are forced to make a guess at a certain mixture of transistor and routing delays Plus: you will inevitably run out of adjustment range. If we make the very simplified assumption that delays change at a rate of 0.3% per degree C, and that delays are inversely proportional to Vcc, then you see that 5% allowable Vcc adjustment does not get you very far. Peter Alfke, Xilinx Applications Andras Tantos wrote: > > > You only control one aspect of delay: gate delay. The other ascpect is > > routing delay, which is substantial too and you don't have any influence. > > That was one of my conerns. However for my particular application it would > only mean a reduction in control range (i.e. total delay is x*<Gate > delay>+y*<routing delay> where I can control only one element while the > other is constant). Also, routing delay in an FPGA should be a complex > thing on it's own I guess so I'm not completely convinced it's totaly > independent from VCC. > > Andras TantosArticle: 56563
Hi all, Sorry to echo the common call on this group, but I've added a little twist. I was looking for FPGA prototype boards that fit the PC/104 form factor and standard. I've checked out the optimagic site, but most of the companies listed there either don't the newer fpga's. Closest I came was Nova Engineering's Altera boards, but Xilinx is much more in my comfort zone. Any suggestions? Thanks. --Josh Model MIT/LLArticle: 56564
> You only control one aspect of delay: gate delay. The other ascpect is > routing delay, which is substantial too and you don't have any influence. > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de This might not be true. All the routing goes through pass transistors. In fact there maybe more pass transistors in the routing than in a LUT. Remember that the "gate" is just more pass transistors. I would say as long as the circuit is adaptive and the start up frequency is near to what you need then this will work. I don't know how _well_ it will work though! SteveArticle: 56565
Salman Sheikh <sheikh@pop500.gsfc.nasa.gov> wrote: : Hello, : I modeled my system in Xilinx System Generator and Matlab (using floating : then fixed point blocks). I found I need to divide a 31 bits number by a 24 : bits number and need to retain a 44 bit result consisting of an 8 bits : representing the integer result and 38 bits the fractional part. I tried : using the Xilinx pipelined divider core but it only handles 32 bit : remainder or fraction. Anybody have any idea where I can get a core or : should I try to code this thing from scratch (extremely painful)? The opencore divider core is parameterizable and comes with source. However it calculates the remainder and not the fractional part. And I don't understand where you get the width of "38 bits" for your fractional part. However the opnecore design assumes a 2N by N division, so in your case you would need to divide 48 bits by 24 bits. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 56566
Xilinx, Virtex II Are there any architecture-related performance (or other) advantages in implementing shift registers with the output on the LSB vs. MSB? In other words: output <= sr[3]; sr[3] <= sr[2]; sr[2] <= sr[1]; sr[1] <= sr[0]; sr[0] <= input; vs, output <= sr[0]; sr[0] <= sr[1]; sr[1] <= sr[2]; sr[2] <= sr[3]; sr[3] <= input; Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 56567
Andras Tantos wrote: > > Hi! > > I have a crazy FPGA application idea for which I need precise timing inside > the FPGA. My thought was to create a delay line of a couple of CLBs inside > the chip, and measure the phase difference between it's input and output > outside the chip. Using this as an error signal I can control the VCCINT > regulator to keep the phase-shift (and consequently the speed of the FPGA) > under control. I plan to use Xilinx Spartan 2E as the device, but I guess > the technique can be used with almost any FPGA. So, my question is, how > much the delay of a CLB is depending on the supply voltage? Where can I > find (if any) documentation on this? How far can I deviate from the nominal > VCCINT value without damaging the device? (the datasheet says 1.8V+-5% in > my case, but also specifies 1.5V as the data retention limit) How constant > is the delay over the entire chip? I mean, if I measure the delay of CLB A, > will CLB B at the other side of the chip have the same delay? Has anybody > done something like this, any recommendations? Any logic family data sheet should give some feel for how this varies, plus it's not hard to actually measure it on the bench. You will find that the behaviour of such a linear element inside a FPGA is non ideal - it will have more jitter, and may even have 'flat-spots' due to cross talk, or worse, be non monotonic. Your circuit should have some 'self centering' scheme, or coarse control, before the fine-analog control is used, to cope with chip variations, routing and temperature. How much delay skew do you need ? - it might be cleaner to apply the same idea to an external tiny-logic gate, where the Vcc range can be wider, and there is no Vcc/Gnd competing noise -jgArticle: 56568
Hi there , I am Khan and I have a problem regarding material suppiled by Xilinx. I am using Xilinx FPGA Editor to view the placed route in actual hardware. The problem is the proper pin assignment. For example in my Constraint file I define signal X to pin 57 and when I observed that particular signal in the editor than I find that this signal is being placed at pin 107. I am using actual hardware to implement my design so I can not just download the code in to chip. The package I am using is HQ240 and device is Xilinx Vertex XCV600 with speed 4. I used all the above mentioned parameter in my project file. Does any body have any idea how to overcome this problem. Thanking you in advance.Article: 56569
On Mon, 09 Jun 2003 11:34:15 -0700, Josh Model wrote: > Hi all, > > Sorry to echo the common call on this group, but I've added a little > twist. I was looking for FPGA prototype boards that fit the PC/104 form > factor and standard. I've checked out the optimagic site, but most of > the companies listed there either don't the newer fpga's. Closest I > came was Nova Engineering's Altera boards, but Xilinx is much more in my > comfort zone. > > Any suggestions? Thanks. > > --Josh Model > MIT/LL We make a couple SpartanII based cards (both PC/104 and PC/104-PLUS) Peter Wallace Mesa ElectronicsArticle: 56570
Hi there I want to write the result of the calculation done in Xilinx Vertex device into the SRAM on board and then to the PC. Can anybody have any idea how to do this I know I can used PC API function in my C file to take data from memory location on SRAM. I don't know what should I write in my VHDL code in order to make sure that I output of the pin always goes to particular memory location in SRAM say X. Any help in this matter will be highly appreciated. Regards KhanArticle: 56571
> Thanks for pointing out the 5I20, an FPGA based IO card with a separate > PCI bridge chip, which might be better for my purposes. uups, my mistake, the 'other options' use pci bridge, 5I20 uses single XC2S200 ASFAIK, so you need some PCI IP but I guess mesanet might provide some examples, they do as example it for the ISA Xilinx board. BTW inside mesanet downloads there is pretty functional 16 Bit RISC core that they use in their motion controllers :) its not advertized on the web, but full VHDL sources are provided. doing PCI with spartan isnt so complicated - my PCI Core uses 65 Slices what I think is pretty small :) the lattice free PCI core(verilog) also compiles with XST :) 130 slices orso. the PCI chip would take the PCI stuff away, but then you are bound to the limitations of it (sure you can do spartan download with it and save configuration rom price) I did also investigate the PCI chips (PLX) but after getting my first own PCI core working I think I will not use the ready made PCI chips any more. antti lukatsArticle: 56572
Larry Doolittle <ldoolitt@recycle.lbl.gov> wrote in message news:<slrnbe9bc7.ni6.ldoolitt@recycle.lbl.gov>... > A quick trip through google and the Xilinx web pages did not > disclose the interface description between the Parallel Cable IV > and the PC Parallel port. With the III version, they gave schematics, > > Can anyone from Xilinx forward me that the interface description? > Or has someone else already reverse engineered it? > > - Larry Hi Larry, I think there will be silence from Xilinx, no matter how you ask. the IV interface specs are not public ASFAIK, but there may be a better way - ChipScope Pro what is a java application uses a windows native DLL that talks to all xilinx cables, so its much more elegant to extract the entry point information from this dll and call them :) its some guess work, and you may have to write a 'bypass dll' for trace logging, but then you are all the time 100% compatible with all the same hardware as ChipScope :) this may or may not work, but it could be one option at least. hmmm this may require chipscope license, even if the dll's work after trial period expires. I'd prefer of course if xilinx would disclose the cable IV specs, then I could write software/drivers that dont fail as badly as xilinx provided ones. antti lukatsArticle: 56573
On Mon, 09 Jun 2003 13:49:19 -0700, Antti Lukats wrote: >> Thanks for pointing out the 5I20, an FPGA based IO card with a separate >> PCI bridge chip, which might be better for my purposes. > > uups, my mistake, the 'other options' use pci bridge, 5I20 uses single > XC2S200 ASFAIK, so you need some PCI IP but I guess mesanet might > provide some examples, they do as example it for the ISA Xilinx board. The 5I20 does use a (PLX9030) Bridge chip.... Peter WallaceArticle: 56574
Hi, It looks like I'm going to have to use an FPGA in a BGA package... this circuit idea needs about 320 I/O pins, and no other package can do that. 12 10-bit flash ADCs, VME32 interface, 68332 uP interface, and tons of fast static RAM. Vibration measurement in jet engine turbine blades. Ouch. We use PADS for PCB layout. So, does anybody know where we can get a PADS library part for Xilinx Xc2S400E-6FG676 or similar, or just the PCB decal for the FG676 package? This monster has 676 solder balls in a 26x26 array, on 1 mm centers. Should be fun to solder and troubleshoot! Respondants will get gratitude, beer, or money, ideally in that order of priority. Thanks, John
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