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Hi.
Just a few questions about SystemC - very grateful for all answers...
Are SystemC hardware models synthesizeable?
Would the OO nature of SystemC aid hardware re-use?
Would running a hardware/software co-simulation in SystemC be
significantly faster/slower than in an RTL simulator?
Thanks in advance,
--
Brendan Lynskey
Comodo Research Lab
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Article: 55201My understanding: As far as synchronising the upper/lower bits to respective upper/lower bits at decoder is concerned, we can proceed with decoding. And check if say some signature in data is recovered or not which is sent frequenctly by the transmitter. If the signature is not found, we can assume that the decoder is not in sync and hence shift by one position to synchronise it. correct me and suggest if there are other ideas, There is a xilinx document regarding it, which i have sent it to your personal account. There is a MS thesis paper by Samirkuma Ranpara on the net which focusses on low power design. However its a flushing encoder. Another document available on the net is titled "Power Reduction Techniques for a Viterbi Decoder.pdf" by I. Bogdan, M. Munteanu, P. A. Ivey, N. L. Seed, N. Powell Please search in google to find where exactly they are available. regards, vikas sharan_nagashetty@yahoo.com (sharan) wrote in message news:<282bcf35.0304250231.6177b4ef@posting.google.com>... > Hi, > > I am also interested in Viterbi decoder..I have some things to clear.. > > 1) How do you synchronise the bits as the data transmitted is in > serial mode..ie. when decoding... > > 2) I would like to add Low power design features, can u tell me if u > have any idea to implement.. > > Thanks. > > regards, > > SharanArticle: 55202
Has anyone seen (or heard of) a spartan 3 development board yet? I know that there are none at Xilinx's homesite, but mayhap there are something else out there? Does anybody know if there currently are boards like this under development? Maybe even a scheduled release-date? Regards, ChristianArticle: 55203
Hello, Everytime I startup Modelsim I land in the Modelsim/examples directory. How do I change my default startup directory. Thanks in advance. SalmanArticle: 55204
Berend Ozceri (snip _news_ from address to reply) wrote: > I just came across Northwest Logic's (http://www.nwlogic.com) PCI/PCI-X > core offerings (for Altera and Xilinx) and was wondering if there were > any folks out there who have used them (or other cores from Northwest > Logic) and would like to share their experiences. What's wrong with the PCI core Xilinx is offering ? cheersArticle: 55205
Hi Salman, It depends. If you're running windows, you can just point the shortcut to the correct directory by: right-clicking on the shortcut, selecting properties. There you will see the "Start In" box. Fill in that box with the location you wish to start in every time. This applies to many, if not all, Windows programs so I've used it for several other applications. Next time you use that shortcut to launch Modelsim, you should land in the directory you specified. Someone else might be able to help you for Linux/Unix if need be. Ryan Salman Sheikh wrote: > Hello, > > Everytime I startup Modelsim I land in the Modelsim/examples directory. How > do I change my default startup directory. Thanks in advance. > > > Salman >Article: 55206
I have been having a problem getting a design which includes the
Xilinx OPB DDR core to work. I am using Memec's V2MB1000 board
(Virtex2-1000). My test case is a MicroBlaze core connected to some
BRAM over the LMB and to the OPB, using the uartlite for I/O. The DDR
core also sits on the OPB. The C code that fails is below:
void
test()
{
unsigned * pu = (unsigned*) 0x01000000;
xil_printf("Writing 0x87654321 to 0x01000000\r\n");
pu[0] = 0x87654321;
xil_printf("Writing 0x12345678 to 0x01000004\r\n");
pu[1] = 0x87654311;
xil_printf("Read 0x%x from 0x01000000\r\n", pu[0]);
xil_printf("Read 0x%x from 0x01000004\r\n", pu[1]);
}
I just get "Read 0x0 from..." messages, rather than my test pattern.
The OPB_DDR instantiation in the system.mhs file is below:
BEGIN opb_ddr
PARAMETER INSTANCE = myddr
PARAMETER HW_VER = 1.00.b
PARAMETER C_INCLUDE_CLK90_DCM = 0
PARAMETER C_INCLUDE_DDRCLK_DCM = 0
PARAMETER C_INCLUDE_DDRCLK_GEN = 0
PARAMETER C_INCLUDE_BURST_SUPPORT = 1
PARAMETER C_REG_DIMM = 1
PARAMETER C_FAMILY = virtex2
PARAMETER C_BASEADDR = 0x0100_0000
PARAMETER C_HIGHADDR = 0x01FF_FFFF
PARAMETER C_OPB_CLK_PERIOD_PS = 10000
PARAMETER C_DDR_CAS_LAT = 3
PORT OPB_Clk = chip_clock
PORT clk90_in = chip_clock90
PORT ddr_clk_in = ddr_clk_w
PORT dcm_rst = net_gnd
PORT ddr_cke = ddr_cke
PORT ddr_csn = ddr_csn
PORT ddr_rasn = ddr_rasn
PORT ddr_casn = ddr_casn
PORT ddr_wen = ddr_wen
PORT ddr_dm = ddr_dm
PORT ddr_bankaddr = ddr_bankaddr
PORT ddr_addr = ddr_addr
PORT ddr_dq = ddr_dq
PORT ddr_dqs = ddr_dqs
BUS_INTERFACE SOPB = myopb
END
I generate the chip_clock, chip_clock90, and ddr_clk_w signals in a
separate module with 2 DCMs (wait 600ms, then assert dcm reset for
1us, then assert OPB_Reset). The other ddr_* signals connect directly
to toplevel ports. Both DCMs are locked when I attempt the test.
Any help would be greatly appreciated. Thanks!
-Rick Copeland
Article: 55207First of all don't post questions or comments on the board if your going to be an A-hole about it. As far as your "Famous Last Words" goes that's what your going to be if you don't get up to speed with the current design techniques. Some people lead, some people follow, and some people go the way of the Do-Do Bird. As far as your clients go; some might prefer schematic now, but that's because they aren't hardware engineers. Yes C is still useful but what about Abel, Fortran, etc. As an engineer you need to learn the newer techniques or you will be left behind. My post was meant to be helpful and to point out where the new technology is going. Most if not all design tools now a days can read in VHDL or Verilog code and convert it to schematic designs. Then you can take the HDL code and give it to a hardware engineer who can make changes to the code quicker and easier then if they were given a schematic design. I'm sorry that you want to continue to use schematic entry for your design, but if you take the time to learn the current design techniques then the power of HDL languages will become apparent to you. But if you just want to be mad and run around like a twelve year old kid upset at the world then you can do that on your own time.....don't post messages here! "eric - Mtl" <notervme@sympatico.ca> wrote in message news:kzfqa.4757$2g5.692097@news20.bellglobal.com... > > > Michael Condon wrote: > > I'm sorry to have to tell you this, but schematic entry for FPGA design is > > dead. > > I'll add it to my collection of "Famous Last Words" ... > > VHDL is being taught at the undergrad level because the schools > > realize this. > > They teach "Java" too. does that make "C" irrelevant ? > > I would suggest that you learn VHDL or Verilog. These are > > two very powerful languages that make hardware design a lot easier and are > > more powerful then schematic entry will ever be. > > Do you *really* think I don't know what HDLs are ? > > VHDL and Verilog allow for > > the code to be portable accross operating platforms and simulator, > > synthesis, and implementation software. > > On portability, VHDL / Verilog clearly do better, since most schematic file > formats are (unfortunately) proprietary. > > I along with many other hardware > > engineers can already see the day when your boss doesn't hand you a Word or > > PDF document for the specifications of a design, but instead will hand you a > > VHDL or Verilog testbench file. > > Well, I don't have a boss. I have customers, and my customers are for now > way more comfortable with a schematic diagram of the functions they want > because everyone there can figure out what it's doing. This might change, > but for now, that's what they like. They would certainly take VHDL code, > if I make them a nice schematic diagram that explains what it does ... > > The testbench file will be able to test the > > design for not only logic accuracy, but also timing specifications since > > VHDL and Verilog files can be generated post implementation which contain > > both gate and path delays associated with the netlist. > > When using Xilinx tools, the schematic diagrams are converted to VHDL, so > I get exactly the same kind of simulation and timing analysis as if I was > coding using VHDL and I don't even need to write the HDL testbench if I > don't want to, thanks to "HDL Bencher" ... > Schematic entry is just an additional preprocessing layer ... > > I'm sorry that you > > are having trouble with the schematic software, but I imagine there will be > > a day(soon) where it is removed from the software completely and is only an > > option. Good luck.... > > > > > > Ain't that FUD ? There's life outside the Newsgroup, and it seems like Xilinx > is willing not only to fix ECS, but to improve it a lot. > > The whole point of this thread was that tool quality severely lags behind > silicon quality and capabilities, and that should be a concern for "X" & "A" > as well as for all users, no matter if they code using schematics, VHDL, > Verilog or whatever ... > > Eric. > >Article: 55208
lsimsic@altera.com (Lara Simsic) writes: > It looks like the problem is that it is not finding the perl that > should have been installed with Nios/SOPC Builder. In the bash shell > you should get "/bin/perl" when typing "which perl". The problem was probably due to that my current working directory was in the project directory, rather than in the cpu_sdk/src below the project directory. I'm sorry about the confusion. I managed to build the srec file under Solaris. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 55209
Michael Condon wrote: > First of all don't post questions or comments on the board if your going to > be an A-hole about it. As far as your "Famous Last Words" goes that's what > your going to be if you don't get up to speed with the current design > techniques. > > Some people lead, some people follow, and some people go the way of the > Do-Do Bird. > > As far as your clients go; some might prefer schematic now, but that's > because they aren't hardware engineers. > > Yes C is still useful but what about Abel, Fortran, etc. As an engineer you > need to learn the newer techniques or you will be left behind. My post was > meant to be helpful and to point out where the new technology is going. > > Most if not all design tools now a days can read in VHDL or Verilog code and > convert it to schematic designs. Then you can take the HDL code and give it > to a hardware engineer who can make changes to the code quicker and easier > then if they were given a schematic design. > > I'm sorry that you want to continue to use schematic entry for your design, > but if you take the time to learn the current design techniques then the > power of HDL languages will become apparent to you. > > But if you just want to be mad and run around like a twelve year old kid > upset at the world then you can do that on your own time.....don't post > messages here! I guess I missed the vote that made you moderator of this group.Article: 55210
Hi all, has anybody experience of designing a DDR SDram Controller on ACEX1K (EP1K100QC208-3) ? I need informations on: * does EP1K100QC208 speed grade -3 include a pll cell? * maximum reachable frequency * possible skew problems between fpga internal clock and ram clocks and some suggestion on how manage them. Moreover, does DDR SDram need a minimum clock frequency? Thanks in advance! AndreaArticle: 55211
"Ray Andraka" <ray@andraka.com> wrote in message
news:3EAEDDED.B54FD49E@andraka.com...
> What are the required specs for the ADC and DAC?
I wanted to experiment with FPGA/DSP techniques by playing with some
real-time spectral audio processing, so I was looking for (ideally) 16-bits
@ something like 48K samples/s.
I suppose maybe FPGAs aren't the best choice of hardware for this type of
processing (high complexity with low sample rate) but this choice of
application was made as an enjoyable vehicle for learning the techniques.
>If the sample rate is low,
> you might be able to use a run of the mill board and use delta-sigma
techniques
> for the converter. I believe xilinx has app notes available on that. If
you
> need more than audio rates, then the number of candidate boards is
narrowed
> considerably. You might start by looking at the links to 3rd party boards
on
> the Xilinx website.
>
Thanks for your help,
Brendan
Article: 55212Saurabh wrote: > My research group is interested in having a very fast network filter > before the packets are sent for further routing (gigabit order). > Preliminary searching has resulted in finding the following paper > which talks about acheiving 2.88 gigabit/sec using ALTERA EP20K. > www.ee.ucla.edu/faculty/papers/billms_FPL2002_sept02.pdf Learning networking and fpgas in the course of a single project will be challenging. Read the following link and then read the paper again. http://groups.google.com/groups?q=vhdl+wan+gorry -- Mike TreselerArticle: 55213
Hi all, How can I control if an I/O pin is registered or not? Thanks, AndreaArticle: 55214
Brendan Lynskey wrote: > "Ray Andraka" <ray@andraka.com> wrote in message > news:3EAEDDED.B54FD49E@andraka.com... > > What are the required specs for the ADC and DAC? > > I wanted to experiment with FPGA/DSP techniques by playing with some > real-time spectral audio processing, so I was looking for (ideally) 16-bits > @ something like 48K samples/s. If you only need audio processing, you could use one of our XSA-50 Boards with an XST-2 Board. The XST-2 has a stereo codec with 20-bit ADC and DAC for each channel. > > > I suppose maybe FPGAs aren't the best choice of hardware for this type of > processing (high complexity with low sample rate) but this choice of > application was made as an enjoyable vehicle for learning the techniques. > > >If the sample rate is low, > > you might be able to use a run of the mill board and use delta-sigma > techniques > > for the converter. I believe xilinx has app notes available on that. If > you > > need more than audio rates, then the number of candidate boards is > narrowed > > considerably. You might start by looking at the links to 3rd party boards > on > > the Xilinx website. > > > > Thanks for your help, > > Brendan -- || Dr. Dave Van den Bout XESS Corp. (919) 303-2883 || || devb@xess.com 2501-B Ten-Ten Road (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 303-2884 ||Article: 55215
Hi Pramod, ONEoverT from our website produces synthesizable IIR FPGA cores. It will give you the VHDL (easily readable). It will let you specify data and coefficient widths, and will let you see the effect of doing so. It isn't free but it is very cheap. The VHDL module is only £150 and generates FIRs, IIRs, hilbert transforms, halfbands etc, etc etc. They are then yours to keep or synthesize into whichever, FPGA / ASIC core you want to. You can get it at www.tyder.com If you even want we will generate and synthesize a core to your specifications for £30. You will only get the EDIF file though, but you can do whatever you want with it in a place and route tool. Best Regards Michael Gallen Tyder Ltd www.tyder.com "Pramod" <pramod@procsys.com> wrote in message news:a7c0720d.0304292309.2ab9f1f2@posting.google.com... > Hi, > Thanks for all the responses which were quite helpful. I would like to > point out that since this implementation should be very > cost-effective, I am on the lookout for free synthesizable IIR cores, > which have scalable data and coeff width. If you can direct me to any > such link it will be a great help for me. > Tom, thanks for the idea on confluence core. I hope you might have a > case study or app note on an IIR implementation using this core. I > would like to know the resource usage by the core. > Thanks and Regards, > Pramod > > tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0304291036.5b1af72a@posting.google.com>... > > pramod@procsys.com (Pramod) wrote in message news:<a7c0720d.0304152101.581c85be@posting.google.com>... > > > Hi All, > > > I am new to this group and also to the field of FPGA based design. > > > I have some doubts and issues which I feel will be easy for you guys > > > to answer. > > > 1. For a 4 pole IIR Filter in FPGA (targeted device EP1C6), I have a > > > spec of 24 bit wide data input and > > > 32 bit wide coeff (dynamic) inputs. So, the multiplied results should > > > ideally have > > > 56 bits width. Are these widths practically relevant for a 4 pole > > > filter > > > or can we get an affordable precision with rounding to lower sizes? > > > If so, can anyone suggest a standard procedure for > > > rounding the results with lowest error and without causing the output > > > to become unstable? > > > > > > Pramod, > > > > You may want to check out the Confluence State Space Processor > > on OpenCores: > > > > http://www.opencores.org/projects/cf_ssp/ > > > > We built the core specifically for linear operations including: > > FIR filters, IIR filters, and general multi-variable state > > space calculations; all of which are common in DSP and control > > applications. > > > > The core is a processor with a very simple instruction > > set -- only 8 instructions -- for addition, shifting, > > sign-extending, limiting, and loading constant coefficients. > > Multiplication is performed by sign-extending the data, then > > performing a series of shifts and conditional adds on an > > accumulator. > > > > The processor is designed for simplicity and takes up very > > little area. Because the processor runs a program every sample > > period, it works well for applications where the clock rate is > > significantly faster that the sample rate of the discrete function. > > > > The architecture gives you 16 registers for I/O, intermediate > > calculation, and state variables. Constants are stored in an > > external memory with an 8-bit address giving you a possible > > total of 256 different coefficients. > > > > The State Space Processor core is generated from Confluence with > > configuration parameters of data width and instruction address > > width. If you don't see the configuration you need, let me know > > and I'll generate a custom processor for you. > > > > Regards, > > TomArticle: 55216
Simon wrote: > > I would have to have a better idea of what's on it, how much free space > there is, and how many pins each BGA, and what constraints / routing is > required before quoting. > > you would have to also accept Protel 98 SE files as that's the software I > own I was half kidding, but I will shoot you all the info when I am ready for that. Right now I am still trying to figure out how to design the power up circuit. Finding the parts I want in an automotive temperature range is hard. I tried looking at the discrete chip approach in detail and found that "zero" power PLD parts are avaialble, but they don't come in the small CSP BGA packages. I guess the circuit board they use to make them won't take 125C temps. The smallest package the Xilinx coolrunner automotive parts comes in is a 44 pin QFP. Sounds small, but at half an inch square that is as large as the MCU it is controlling!!! I hate to make things hard for the layout person. Or maybe I should say I hate to make things *worse*. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55220
Opps, I forgot to include the more important group... c.a.f! I have been looking for a CPLD or even an SPLD that will take the full automotive temperature range. The parts I have found all have some limitation. The Coolrunner parts don't come in a small enough package and the Lattice part I found draws too much static current. However, I think I may have figured out a way to do this using the Xilinx Coolrunner industrial grade parts in the much smaller CSP package. The board will be powered by 5 volts. A small LDO will provide power to the XCR3032XL or XCR3064XL CPLD. The over temp sensor will disable the LDO cutting power to the CPLD. This way the CPLD will be protected. In addition, the CPLD outputs should go high impedance allowing the power control to the rest of the board to be pulled high turning off power. The only fly in the ointment I can see is voltage on some of the inputs. These inputs are pulled up to 5 volts at all times and one comes from off card and may be driven to 5 volts such as with a jumper. The data sheet says the inputs are only rated for voltage up to 4 volts above Vcc. Is there a way to provide protection to these inputs with a resistor in series and still allow inputs to the board to be actively pulled up to the 5 volt rail while the device is not powered? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55221
rickman wrote: > > Opps, I forgot to include the more important group... c.a.f! > > I have been looking for a CPLD or even an SPLD that will take the full > automotive temperature range. The parts I have found all have some > limitation. The Coolrunner parts don't come in a small enough package > and the Lattice part I found draws too much static current. > > However, I think I may have figured out a way to do this using the > Xilinx Coolrunner industrial grade parts in the much smaller CSP > package. The board will be powered by 5 volts. A small LDO will > provide power to the XCR3032XL or XCR3064XL CPLD. The over temp sensor > will disable the LDO cutting power to the CPLD. This way the CPLD will > be protected. In addition, the CPLD outputs should go high impedance > allowing the power control to the rest of the board to be pulled high > turning off power. > > The only fly in the ointment I can see is voltage on some of the > inputs. These inputs are pulled up to 5 volts at all times and one > comes from off card and may be driven to 5 volts such as with a jumper. > The data sheet says the inputs are only rated for voltage up to 4 volts > above Vcc. Is there a way to provide protection to these inputs with a > resistor in series and still allow inputs to the board to be actively > pulled up to the 5 volt rail while the device is not powered? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX What are you doing? I saw a similar question posted on SED. What is the maximum temperature you expect to see? What are the reliability requirements? We use certain industrial or automotive grade parts in oilfield tools to 175 Degrees C (350 F). They no longer behave exactly like the data sheet but do work. Usually the tool gets lost in hole before reliability in K's of hours is important. If it fails they have to pull out of the hole and replace the tool. Customers in this industry understand the problems and always have back up tools with them should the need arise. We have built special tools that have ran at 230 Deg C (450 F), but these are very expensive to produce. By the way most regulators will shut themselves off at around 160 Deg C die temperature which may solve your thermal limit problem without any extra hardware. Good Luck Jim StocktonArticle: 55222
rickman wrote: > > Opps, I forgot to include the more important group... c.a.f! > > I have been looking for a CPLD or even an SPLD that will take the full > automotive temperature range. The parts I have found all have some > limitation. The Coolrunner parts don't come in a small enough package > and the Lattice part I found draws too much static current. > > However, I think I may have figured out a way to do this using the > Xilinx Coolrunner industrial grade parts in the much smaller CSP > package. The board will be powered by 5 volts. A small LDO will > provide power to the XCR3032XL or XCR3064XL CPLD. The over temp sensor > will disable the LDO cutting power to the CPLD. This way the CPLD will > be protected. In addition, the CPLD outputs should go high impedance > allowing the power control to the rest of the board to be pulled high > turning off power. I'm not sure I see the problem. Coolrunner parts in static conditions will have (effectively) no thermal adders, and Tj will be == Ta. Why do you want/need to remove the Vcc ? - do you believe there is a sudden, drastic failure mode that occurs if the device hits 86'C when biased ? - how is that failure mode avoided if the IO pins are instead run at Abs max 4V ? If you have a clocked device, that has a high thermal loading, then removing the clock can buy a good chunk of 'thermal tolerance', ( and the system effectively goes into 'thermal pause' ) -jgArticle: 55223
I can relate to the problems you are having with the place and route tools. I have spent countless hours tring rewrite and optimze my VHDL or schematics designs. We all try to obtain the maximum performance in the smallest real estate possible. You need to better understand the technology your working with before comdeming it. On a Xilinx device, maximun performance can usually be obtained until 99% of the slices are consumed. After that, unrelated logic packing in the slice occures to fit the design. This unrelated logic, and associated rat nest of routes used to perform this packing, is where the delays start to become a problem. The constraints file setup my the designer helps the software determine which signals are the most critical and give highest priority. To maintain maximum performance, the size of the FPGA should be large enough to minimize or eliminate the unrelated logic packing. There will a large amount of unused resources, but performance usually doesn't come without a price. For large DSP's, you may need multiple smaller FPGA's instead of one large one. As far as SystemAce is concerned, it is still new software. Any bugs it may have, will be fixed eventually. Welcome to the real world. Ray Andraka <ray@andraka.com> wrote in news:3EA5A01C.3F9E2878@andraka.com: > The problem is that there are no third party place and route tools. > The place and route tools are where the worst bugs (features) are. > The one that is particularly debilitating is the laziness of the > router in versions 4.x and 5.x that makes all paths in a design become > critical paths. > > Evan wrote: > >> I've worked with various tools since FPGA's first appeared. You >> can't beat the price and performance of the software provided by >> Xilinx or Altera. Their software may have bugs, but you can usually >> work around them. If the vendor put as much effort to make the >> perfect software product you wanted. You wouldn't be able to afford >> it. Has it stands, the high end software tools cost $10,000 to >> $20,000+. Altera and Xilinx provide these tools as a low cost >> alternative, to help promote their sales. If you can't deal with it, >> put up the big bucks and buy the good software. Don't ruin a good >> thing for the rest of us. >> >> billh40@aol.com (Bill Hanna) wrote in >> news:97d137ce.0304171001.5ec5461d@posting.google.com: >> >> > I have been designing a Digital Signal Processor using the XC2V4000 >> > chip. >> > Software errors in ISE 4.2 and 5.1 have caused long hours of delay >> > in developing the design: >> > >> > Software bugs in SystemAce causes erase problems in the MPM. >> > Deleting signal wires in ECS causes Fatal errors that crash the >> > system. >> > A large design exceeds the 2GB memory limit and generates a >> > fatal >> > memory error. >> > >> > I have designed Altera chips for over 6 years and never had a >> > problem. >> > >> > All digital designers should stop designing new projects with >> > Xilinx ICs until Xilinx corrects all software problems with ISE. >> > >> > Bill Hanna > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >Article: 55224
Andrea,
I assume you mean that the Input signal feeds a register, or the Output
signal is fed by a register, and that you want the register in the IOE (IO
Element) to be used by the place and route tool. In Quartus II you may apply
the Fast Input Register or Fast Output Register assignment to the pins or
registers directly. This assignment can me made using the Assignment
Organizer in Quartus II.
- Subroto Datta
Altera Corp.
"AP" <NSP_a.paterniani@NSP_swapp-eng.it> wrote in message
news:b8p5aq$5l3$1@lacerta.tiscalinet.it...
> Hi all,
>
> How can I control if an I/O pin is registered or not?
>
> Thanks,
> Andrea
>
>
>
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