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Trying to get some numbers: In the ACEX data sheet there is a plot output current vs. output voltage. The Low output is strong => generates more problems. Using the this I get about 80 mA at 1 V. Results in an Rs of 12.5 R. Sample Load is a async. Ram with Cin = 8 pF, Cout of ACEX is 10 pF => Cl is about 20 pF. The resulting Trc = 250 ps. Tr(rise) = 2.2 * Trc = 550 ps. Thats pretty fast. Now mapping these results to the Cyclone. Acex garanties max. 0.45V at 12 mA for Vlow, Cyclone 24 mA at the same Voltage. => Rs is half of Acex (6 R). Output strength of LVTTL can be reduced to 4 mA (1/6). Does this result in an equivalent source resistor of 36 R? With 36 R Tr is 3.3 ns. This means no real problems at signal traces shorter than 10 cm (l[cm]/56ps < 1/6*tr, 56 ps/cm on outer layer of board with er 4.5). Does this simple calculation make sense? What changes with the slow slew rate control? Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag news:dL4ta.21181$e8.247077@news.chello.at... > I'm interested in the minimum switching time of current FPGAs. E.g. in a > Cyclone you can select IO drive strength and slew rate control. But I > haven't found the resulting timings in the data sheet. Am I reading > something wrong? > > Martin > > -------------------------------------------------------- > JOP - a Java Processor core for FPGAs now > on Cyclone: http://www.jopdesign.com/cyclone/ > >Article: 55351
Sudip, The Virtex II, II Pro, Spartan 3 DCMs will take a 1MHz input and multiply it by 24 to 32 for a 24 MHz to a 32 MHz output. Austin sudip saha wrote: > Hi All, > in Altera Apex20K we can use pll and generate higher clock. But the > minimum frequency for the clock input to the PLLs are 1.5 Mhz. > is there any way to use a slower clock like 1 mhz and generate a high > speed clock? > In Xilinx Fpgas, is there any PLL options? > In a nutshell, I want to generate a high speed clk from a 1 mhz clk > and both the clocks should be locked. > Your suggestions will be of great help.Article: 55352
4000 series parts didn't have the luxury of xpower. Late in the series Xilinx
did publish a spreadsheet estimator for 4K power. Before that, the data sheet
had a section that described the power of various features in the FPGA, enough
for a user to work up a power estimate by hand (it was very tedious). The
easiest method back then, and probably still now, was to make some measurements
and then degrade the measured results for margin.
Glen Herrmannsfeldt wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3EB2E430.2D44E007@andraka.com...
> > Xilinx can't tell you what the power is going to be. It depends very
> heavily on
> > your design. If you need to know the power, Xilinx does provide the
> XPOWER tool
> > that will compute your power based on the actual place and route and
> simulation
> > vectors you feed the tool. THe accuracy will depend on how representative
> your
> > simulation vectors are of the actual operation. Xilinx also has some
> spread
> > sheets that can be used to get an estimate based on your estimates of the
> logic
> > used, your assessment of 'routing complexity', and your declaration of
> clock
> > rates and toggle rates. Those spread sheets will get you to about
> +/-12dB.
>
> The original question was in the XC4000 days, so I don't know if things have
> changed since. 12dB is probably good enough. The important question was if
> a fan and/or heatsink would be required. It is easy to imagine high clock
> rates with a significant fraction of FF's changing state on each clock
> cycle.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55354Martin, do not forget that the Vol is a guaranteed value, at lowest Vcc and highest temperature and poor processing extreme. At typical operating conditions, the current will be double, or more. I suggest you do some measurements, or get Altera to send you IBIS models ( the preferred method !) Peter Alfke, Xilinx Applications ============================= Martin Schoeberl wrote: > > Trying to get some numbers: > In the ACEX data sheet there is a plot output current vs. output voltage. > The Low output is strong => generates more problems. Using the this I get > about 80 mA at 1 V. Results in an Rs of 12.5 R. > > Sample Load is a async. Ram with Cin = 8 pF, Cout of ACEX is 10 pF => Cl is > about 20 pF. > The resulting Trc = 250 ps. Tr(rise) = 2.2 * Trc = 550 ps. Thats pretty > fast. > > Now mapping these results to the Cyclone. Acex garanties max. 0.45V at 12 mA > for Vlow, Cyclone 24 mA at the same Voltage. => Rs is half of Acex (6 R). > Output strength of LVTTL can be reduced to 4 mA (1/6). > Does this result in an equivalent source resistor of 36 R? > With 36 R Tr is 3.3 ns. This means no real problems at signal traces shorter > than 10 cm (l[cm]/56ps < 1/6*tr, 56 ps/cm on outer layer of board with er > 4.5). > > Does this simple calculation make sense? What changes with the slow slew > rate control? > > Martin > -- > -------------------------------------------------------- > JOP - a Java Processor core for FPGAs now > on Cyclone: http://www.jopdesign.com/cyclone/ > "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag > news:dL4ta.21181$e8.247077@news.chello.at... > > I'm interested in the minimum switching time of current FPGAs. E.g. in a > > Cyclone you can select IO drive strength and slew rate control. But I > > haven't found the resulting timings in the data sheet. Am I reading > > something wrong? > > > > Martin > > > > -------------------------------------------------------- > > JOP - a Java Processor core for FPGAs now > > on Cyclone: http://www.jopdesign.com/cyclone/ > > > >Article: 55355
Tullio Grassi <tullio@umd.edu> writes: > On our Virtex2 board we have a single clock input; > if we disable the clock signal and than we re-enable it, > the device gets 'stuck'. > I read a posting in this newsgroup about a similar problem > that was traced back to the BUFGMUX. > Xilinx folks explained that the BUFGMUX is not a simple mux. > Is it possible that also my problem is related to that ? Have you tried a BUFGCE? A mux might not work in your situation. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 55356
Peter,
I don't have to get exact values. Just interested to get a feeling for the
rise time and the dI/dt. For my application fast rise time is not necessary
and just makes problems with the EMC test.
I took the 80 mA for 1 V from a static plot. Dynamic it can only be slower
(better for me).
After 1V the output is more like a current source. So using only the
resistance part of the output transistor is the worse case.
Perhaps it would be better to model it (the ACEX output) with 6 R till 1 V
(like you suggested) and than with, let's say, a 150 mA current source. (But
I'm now to lazy to calculate it by hand, will model it in spice).
About IBIS:
a.) IBIS is not available for Cyclone now.
b.) IBIS is not available with the Quartus Web edition. And I will not
bye a license till VHDL synth. works like in leonardo and the post route
simulator can simulate my design)
c.) I have no simulation sw for IBIS
Just to get an idea of the output stage it would be nice to add plots and
typical values in the Cyclone data sheet.
Martin
--
--------------------------------------------------------
JOP - a Java Processor core for FPGAs now
on Cyclone: http://www.jopdesign.com/cyclone/
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag
news:3EB68D30.9FEA4D5A@xilinx.com...
> Martin,
> do not forget that the Vol is a guaranteed value, at lowest Vcc and
> highest temperature and poor processing extreme. At typical operating
> conditions, the current will be double, or more.
> I suggest you do some measurements, or get Altera to send you IBIS
> models ( the preferred method !)
>
> Peter Alfke, Xilinx Applications
> =============================
> Martin Schoeberl wrote:
> >
> > Trying to get some numbers:
> > In the ACEX data sheet there is a plot output current vs. output
voltage.
> > The Low output is strong => generates more problems. Using the this I
get
> > about 80 mA at 1 V. Results in an Rs of 12.5 R.
> >
> > Sample Load is a async. Ram with Cin = 8 pF, Cout of ACEX is 10 pF => Cl
is
> > about 20 pF.
> > The resulting Trc = 250 ps. Tr(rise) = 2.2 * Trc = 550 ps. Thats pretty
> > fast.
> >
> > Now mapping these results to the Cyclone. Acex garanties max. 0.45V at
12 mA
> > for Vlow, Cyclone 24 mA at the same Voltage. => Rs is half of Acex (6
R).
> > Output strength of LVTTL can be reduced to 4 mA (1/6).
> > Does this result in an equivalent source resistor of 36 R?
> > With 36 R Tr is 3.3 ns. This means no real problems at signal traces
shorter
> > than 10 cm (l[cm]/56ps < 1/6*tr, 56 ps/cm on outer layer of board with
er
> > 4.5).
> >
> > Does this simple calculation make sense? What changes with the slow slew
> > rate control?
> >
> > Martin
> > --
> > --------------------------------------------------------
> > JOP - a Java Processor core for FPGAs now
> > on Cyclone: http://www.jopdesign.com/cyclone/
> > "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag
> > news:dL4ta.21181$e8.247077@news.chello.at...
> > > I'm interested in the minimum switching time of current FPGAs. E.g. in
a
> > > Cyclone you can select IO drive strength and slew rate control. But I
> > > haven't found the resulting timings in the data sheet. Am I reading
> > > something wrong?
> > >
> > > Martin
> > >
> > > --------------------------------------------------------
> > > JOP - a Java Processor core for FPGAs now
> > > on Cyclone: http://www.jopdesign.com/cyclone/
> > >
> > >
Article: 55357Tullio, The BUFGMUX is a state machine that is designed to prevent the clock output from having a low time shorter than the shortest low, or a high time shorter than the shortest high. That said, it must have both clocks operating to switch between them. Use BUFCE (as suggested in the other response) if you wish to gate the clock. Austin Tullio Grassi wrote: > On our Virtex2 board we have a single clock input; > if we disable the clock signal and than we re-enable it, > the device gets 'stuck'. > I read a posting in this newsgroup about a similar problem > that was traced back to the BUFGMUX. > Xilinx folks explained that the BUFGMUX is not a simple mux. > Is it possible that also my problem is related to that ? > -- > > Tullio Grassi > > ====================================== > Univ. of Maryland - Dept. of Physics > College Park, MD 20742 - US > Tel +1 301 405 5970 > Fax +1 301 699 9195 > ======================================Article: 55358
cfk wrote:
> Interesting you bring up firmware as opposed to hardware. That is one of the
> key points I am struggling with. Some seem to feel that firmware consists of
> everything in the FPGA, while others seem to think firmware is the
> instructions to a CPU such as a RISC that is implemented in the FPGA and
> runs software (firmware?). One of the reasons I am seeking this knowledge is
> to sort the wheat from the chaff regarding whether or not there even should
> be a CPU in a 802.11 MAC.
A media access controller is in charge of adding/stripping
the lowest level headers/trailers to/from a data packet,
generating or checking the crc and arbitrating data flow to the PHY.
A standard CPU cannot keep up with these functions at
line rates, so a MAC is normally done in hardware.
A CPU often handles the higher level protocols and the RAM buffers
used to convert a file to/from packets.
The PHY is always hardware and converts data words into
pulses, flashes or waves.
> I can take it either way, however. I am still seeking an example of packet
> framing at the lowest level of interface to a radio. Although the radio I am
> contemplating is not exactly the same as currently perceived 802.11, it is
> still similar in concept. Because of that, I am seeking an example, partial
> or complete.
It is unlikely that you will find a code example that does
exactly whatever it is you have in mind. Read the specs and books
then just begin.
-- Mike Treseler
Article: 55359
FPGA user wrote:
> Has anyone used LPM_ROM megafunctions in an EP1K50? They do NOT seem to
> work in simulation. However, an EP1K30 or an EP1K100 DOES work.
Sound like a bug.
Call Altera and wait or consider using
a constant array of vectors instead.
-- Mike Treseler
Article: 55360"Ben Jackson" <ben@ben.com> schrieb im Newsbeitrag news:XVyta.503129$Zo.109682@sccrnsc03... > In article <b966k0$fja5t$1@ID-84877.news.dfncis.de>, > Falk Brunner <Falk.Brunner@gmx.de> wrote: > > > >I suggest to put two schmitt-triggers (74HC14) in front of the TCK/CCLK and > >TMS/PROGRAM line, and in front of them a RC-filter of lets say 330 Ohm/1nF. > > Where do you mean "in front of"? Between the parallel cable and the > tris buffers? That makes sense but your signal naming makes me think > you're talking about a replacement for the existing 100/100pF output > filters. These "filters" dont make much sense to me, so I left them out. I have a RC filter between the (plain) signal from the parallel port (with Loooong cable and muuuuch noise) and the first schmitt-trigger. The second schmitt-trigger is just to invert he inversion ;-), so its logically identical to the original cable. Nice to hear that some people are running this config with looong cable and nooo trouble ;-). If its still unclear, I can send you a schematics. -- MfG FalkArticle: 55361
"Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag news:Xbxta.49767$e8.532192@news.chello.at... > c.) I have no simulation sw for IBIS Have a look for hyperlynx. Sorry, I dont have a link at hand (Austin, looks like this is your turn ;-). The software comes in a free trail version, nice to play with and get a feeling about output drivers and terminations. -- MfG FalkArticle: 55362
Falk, What, and help someone trying to use a Cyclone IC? Sigh. That is why I am generally looked at as a nice guy. 'White hat' on: http://www.mentor.com/hyperlynx/ is the link for Hyperlynx. 'Black Hat' on: I will point out that Xilinx prides itself in having viable cross-checked IBIS models ready for designers....and there is no excuse whatsoever for not having them by the time you claim you are in 'production'. Austin Falk Brunner wrote: > "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag > news:Xbxta.49767$e8.532192@news.chello.at... > > > c.) I have no simulation sw for IBIS > > Have a look for hyperlynx. Sorry, I dont have a link at hand (Austin, looks > like this is your turn ;-). The software comes in a free trail version, nice > to play with and get a feeling about output drivers and terminations. > > -- > MfG > FalkArticle: 55363
Hi Joona, > Ibis model for Cyclone is coming soon, promises Altera's web page. > Does anyone have a specific information of relase date or something? > Is there some compatible models available now, or some other way? I'm expecting IBIS support in version 3.0, due in June. Given the fact that the Cyclone devices are built on the same process as Stratix I'd use those models in the meantime. Of course the Stratix have a different internal power distribution network so there will definitely be differences, but curve shapes should be similar. No idea about pin RLC values though. Best regards, BenArticle: 55364
> It is unlikely that you will find a code example that does > exactly whatever it is you have in mind. Read the specs and books > then just begin. > Fine, I spent the day reading the hermes code in Linux dealing with controlling the microcoded state machine in Intersil's HFA3842 and Lucent's Hermes. I am looking for some additional references regarding this state machine besides that. I would believe that this group might know where such references would be. I also have the O'Reilly book on 802.11 that I have been studying, but I am at the stage where I need some additional logical example information that is beyond what the specs and the books have. CharlesArticle: 55365
> Sound like a bug. > Call Altera and wait or consider using > a constant array of vectors instead. Better yet, file a report online at http://mysupport.altera.com. Paul Leventis Altera Corp.Article: 55366
Ziad: Check out http://www.mjl.com/product/mjlstratix.asp I like this board because it is inexpensive ($795) and has an EP1s25 device. It also has integrated VGA output. I anticipate a graphics project using FPGA's. Atif. zabulebdeh@yahoo.com (Ziad Abu-Lebdeh) wrote in message news:<f784b02b.0305030542.5976b082@posting.google.com>... > Hi Atif, > > I am not familiar with the MJL kit you are talking about, but Altera > does have a 1S80 Kit for DSP. Check it out here: > http://www.altera.com/products/devkits/altera/kit-dsp_stratix_pro.html > > Ziad Abu-Lebdeh > > azafar@iupui.edu (Atif Zafar) wrote in message news:<6ed146ef.0305010820.682b01be@posting.google.com>... > > Does anyone have experience with the MJL Stratix dev kit. It is the > > lowest cost Stratix EP1s25 kit I could find. Anyone know whether it > > can handle devices denser than the 1s25 (i.e. 1s40 or 1s80?). I have > > an imaging and 3d graphics pipeline project. Does anyone know whether > > the Virtex II are a better choice or the Stratix? Thanks. > > > > Atif Zafar > > Indiana UniversityArticle: 55367
jonesky1@hotmail.com (Joona R) wrote in message news:<2f3990c3.0305050252.36756f37@posting.google.com>... > Hi! > > Ibis model for Cyclone is coming soon, promises Altera's web page. > Does anyone have a specific information of relase date or something? > Is there some compatible models available now, or some other way? > > I should simulate PCB with Expedition PCB & Signal Vision/Analyzer. > > Thanks, > Joona Joona, The final Cyclone IBIS models will be released on www.altera.com in July. These models will be fully correlated to silicon and will include a silicon-to-model correlation report. They will be incorporated into Quartus II software in version 3.0 SP1. We are running a beta site on the models now. To join in and get these models, please contact your FAE or file a MySupport request on www.altera.com. Sincerely, Greg Steinke gregs@altera.comArticle: 55368
Martin, A few comments: - You had asked in a previous posting how slow slew rate works. In Cyclone devices (and most Altera FPGAs) the slow slew rate setting works by adjusting the rate at which the signal at the gate of the driver is switched from low to high or vice versa. In this way the actual DC drive strength is unchanged, but the slew rate is changed. It does make it difficult to model in a hand calculation however. - We have a beta program for the Cyclone IBIS models running today. Please contact your FAE to join this program. The final, fully correlated Cyclone IBIS models will be available in July. - In general, IBIS models are distributed either directly on the web (see http://www.altera.com/support/software/download/ibis/stratix/ibs-stratix.html) or through Quartus II, which makes the full-chip IBIS model. So even if the version of Quartus II that you use does not generate an IBIS model, you can still download them from the web site. - We (and some other FPGA companies) no longer publish the IV curves in the datasheet as there are many IO options. In the old days we'd have 5V, maybe 3.3V, that's it. But now there's often many IO options, between drive strength, IO standard, and so forth. Not to mention PCI clamp and slew rate, even though they don't directly affect the IV curve in the normal operating range. Sincerely, Greg Steinke gregs@altera.com "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<Xbxta.49767$e8.532192@news.chello.at>... > Peter, > I don't have to get exact values. Just interested to get a feeling for the > rise time and the dI/dt. For my application fast rise time is not necessary > and just makes problems with the EMC test. > I took the 80 mA for 1 V from a static plot. Dynamic it can only be slower > (better for me). > After 1V the output is more like a current source. So using only the > resistance part of the output transistor is the worse case. > Perhaps it would be better to model it (the ACEX output) with 6 R till 1 V > (like you suggested) and than with, let's say, a 150 mA current source. (But > I'm now to lazy to calculate it by hand, will model it in spice). > > About IBIS: > a.) IBIS is not available for Cyclone now. > b.) IBIS is not available with the Quartus Web edition. And I will not > bye a license till VHDL synth. works like in leonardo and the post route > simulator can simulate my design) > c.) I have no simulation sw for IBIS > > Just to get an idea of the output stage it would be nice to add plots and > typical values in the Cyclone data sheet. > > Martin > -- > -------------------------------------------------------- > JOP - a Java Processor core for FPGAs now > on Cyclone: http://www.jopdesign.com/cyclone/ >Article: 55369
Rather than 104 8x1 multiplexors, the 64 13-bit "hold" registers could be 64 13-bit loadable shifters themselves. A broadside load into 8 chains of fully exposed shift registers would be able to feed the dynamic shift registers. There would be no additional registers used though an extra LUT level is probably required. Depending on the logic, the existing hold registers might be direct-input registers allowing the additional LUTs to be the ones already paired with the hold (now load/shift) registers. The only other idea that comes to mind is a bizarre method of using XORs and zeroing the original hold registers in sequence to hand-tune things down to 2 LUTs per bit plus some overall system overhead and conceptual confusion rather than the 4 LUTs per bit to achieve the 8-1 multiplexing. Not recommended. If you can afford the LUTs, the load/shift might be the cleanest topology with little concern for routing delays. The 8-1 mux is the most efficient "easy" solution from a LUT count and isn't bad for routing since each hold register still only has a fanout of 1. And then, of course, there are those tristates you mentioned; perhaps not a bad alternative if you're truly tight on resources. Happy coding. Domagoj wrote: > Hi > > A project I'm working on requires in one stage to feed 64 13-bit values into > 8 buffers (dynamic > shift registers) in <10 cycles. Input values can be seen as divided in 8 > groups, and each group has > to be shifted into the buffer in some order in <10 cycles. Is there any > other trick to implement it, except > by using either three-state buses or 104 8x1 multiplexors (in 8 cycles) ? > > Those 64 values are all computed concurrently every 10 cycles and stored > into registers, but other > storage could also be used (like select ram). 10 cycles limit is the lower > bound, but changing it > would require heavy redesign at the moment (and lower throughput, of > course). > > thx, > > -- > Domagoj Babic > domagoj (et) engineer.com > >Article: 55370
Have found the HyperLynx, but only a demo version for download where you can't simulate a changed network :-( It's like in the old days to get the information: As I started with electronic/computer it was hard to get the datasheets/books. With the Web everything changed. Just type a part number in google and you get the datasheet. Now the important information is burried in simulation meodels. A very good thing if you have all the simulators. But without... Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ ----- Original Message ----- From: "Falk Brunner" <Falk.Brunner@gmx.de> Newsgroups: comp.arch.fpga Sent: Monday, May 05, 2003 10:40 PM Subject: Re: Output switching time > "Martin Schoeberl" <martin.schoeberl@chello.at> schrieb im Newsbeitrag > news:Xbxta.49767$e8.532192@news.chello.at... > > > c.) I have no simulation sw for IBIS > > Have a look for hyperlynx. Sorry, I dont have a link at hand (Austin, looks > like this is your turn ;-). The software comes in a free trail version, nice > to play with and get a feeling about output drivers and terminations. > > -- > MfG > Falk > > > >Article: 55371
Greg, thanks for the information. It would be nice if the change of the slew rate could be stated in the datasheet. You don't always want to run a simulation (with tools you don't have access to) to get a simple information like: When I turn the slow sr on, do I meet my timing e.g. for an async. ram? Sorry for my ignorance about the IBIS models on the web. Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "Greg Steinke" <gregs@altera.com> schrieb im Newsbeitrag news:5c1de958.0305051840.6fd3fca6@posting.google.com... > Martin, > A few comments: > - You had asked in a previous posting how slow slew rate works. In > Cyclone devices (and most Altera FPGAs) the slow slew rate setting > works by adjusting the rate at which the signal at the gate of the > driver is switched from low to high or vice versa. In this way the > actual DC drive strength is unchanged, but the slew rate is changed. > It does make it difficult to model in a hand calculation however. > > - We have a beta program for the Cyclone IBIS models running today. > Please contact your FAE to join this program. The final, fully > correlated Cyclone IBIS models will be available in July. > > - In general, IBIS models are distributed either directly on the web > (see http://www.altera.com/support/software/download/ibis/stratix/ibs-stratix.htm l) > or through Quartus II, which makes the full-chip IBIS model. So even > if the version of Quartus II that you use does not generate an IBIS > model, you can still download them from the web site. > > - We (and some other FPGA companies) no longer publish the IV curves > in the datasheet as there are many IO options. In the old days we'd > have 5V, maybe 3.3V, that's it. But now there's often many IO options, > between drive strength, IO standard, and so forth. Not to mention PCI > clamp and slew rate, even though they don't directly affect the IV > curve in the normal operating range. > > Sincerely, > Greg Steinke > gregs@altera.com > > > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<Xbxta.49767$e8.532192@news.chello.at>... > > Peter, > > I don't have to get exact values. Just interested to get a feeling for the > > rise time and the dI/dt. For my application fast rise time is not necessary > > and just makes problems with the EMC test. > > I took the 80 mA for 1 V from a static plot. Dynamic it can only be slower > > (better for me). > > After 1V the output is more like a current source. So using only the > > resistance part of the output transistor is the worse case. > > Perhaps it would be better to model it (the ACEX output) with 6 R till 1 V > > (like you suggested) and than with, let's say, a 150 mA current source. (But > > I'm now to lazy to calculate it by hand, will model it in spice). > > > > About IBIS: > > a.) IBIS is not available for Cyclone now. > > b.) IBIS is not available with the Quartus Web edition. And I will not > > bye a license till VHDL synth. works like in leonardo and the post route > > simulator can simulate my design) > > c.) I have no simulation sw for IBIS > > > > Just to get an idea of the output stage it would be nice to add plots and > > typical values in the Cyclone data sheet. > > > > Martin > > -- > > -------------------------------------------------------- > > JOP - a Java Processor core for FPGAs now > > on Cyclone: http://www.jopdesign.com/cyclone/ > >Article: 55372
Hello Ben! Well, I downloaded IBIS for Stratix and I try to use it before I get the right one. Thank you for your idea! Yours, Joona > I'm expecting IBIS support in version 3.0, due in June. Given the fact that > the Cyclone devices are built on the same process as Stratix I'd use those > models in the meantime. Of course the Stratix have a different internal > power distribution network so there will definitely be differences, but > curve shapes should be similar. No idea about pin RLC values though.Article: 55373
> > Hi! > > > > Ibis model for Cyclone is coming soon, promises Altera's web page. > > Does anyone have a specific information of relase date or something? > > Is there some compatible models available now, or some other way? > > > > I should simulate PCB with Expedition PCB & Signal Vision/Analyzer. > > > > Thanks, > > Joona > > Joona, > The final Cyclone IBIS models will be released on www.altera.com in > July. These models will be fully correlated to silicon and will > include a silicon-to-model correlation report. They will be > incorporated into Quartus II software in version 3.0 SP1. > > We are running a beta site on the models now. To join in and get these > models, please contact your FAE or file a MySupport request on > www.altera.com. > > Sincerely, > Greg Steinke > gregs@altera.com Hi Greg! Thank you for your answer! I did make the MySupport request. Hopefully I will receive beta version of model soon. =) Best Regards, JoonaArticle: 55374
Ben, what tool are you using for the IBIS models? Anything available for free :-) Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "Ben Twijnstra" <btwijnstra@SPAM.ME.NOT.chello.nl> schrieb im Newsbeitrag news:gGBta.1290893$sj7.53360703@Flipper... > Hi Joona, > > > Ibis model for Cyclone is coming soon, promises Altera's web page. > > Does anyone have a specific information of relase date or something? > > Is there some compatible models available now, or some other way? > > I'm expecting IBIS support in version 3.0, due in June. Given the fact that > the Cyclone devices are built on the same process as Stratix I'd use those > models in the meantime. Of course the Stratix have a different internal > power distribution network so there will definitely be differences, but > curve shapes should be similar. No idea about pin RLC values though. > > Best regards, > > > > Ben >
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