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Messages from 55325

Article: 55325
Subject: Re: PLL chips
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 04 May 2003 01:00:04 -0700
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) writes:
> Is there any obvious PLL chip to use with an FPGA?   I want to do
> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
> 100 MHz from 9.999999371 MHz)

Cypress CY22150 and CY22393/4/5 are quite easy to use.  You're not going
to get that many digits of precision, though.  Which is usually OK, because
typical clock sources (crystal oscillators) generally have at least +/-30 ppm
tolerance.  So unless you're planning to use a cesium or rubidium reference,
or a crystal oven locked to GPS, you're probably need to settle for
100.0003 MHz +/- 3 KHz.

Why do you think you need nine digits precision anyhow?  How would you
test that your circuit is actually that accurate?

> Are there any good articles on this aspect of PLLs?  I'm expecting
> there are some tricks for filtering out the low frequency noise
> injected by the occasional steps when the low bits accumulate to
> a whole tick and a cycle gets inserted/dropped.

Mostly I think you just have to live with the jitter.  I don't think
there's really any way to eliminate it.

Article: 55326
Subject: Output switching time
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Sun, 04 May 2003 09:07:21 GMT
Links: << >>  << T >>  << A >>
I'm interested in the minimum switching time of current FPGAs. E.g. in a
Cyclone you can select IO drive strength and slew rate control. But I
haven't found the resulting timings in the data sheet. Am I reading
something wrong?

Martin

--------------------------------------------------------
JOP - a Java Processor core for FPGAs now
on Cyclone: http://www.jopdesign.com/cyclone/



Article: 55327
Subject: Re: PLL chips
From: already5chosen@yahoo.com (Michael S)
Date: 4 May 2003 02:21:09 -0700
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message news:<vb8rj1h4742fe1@corp.supernews.com>...
> Is there any obvious PLL chip to use with an FPGA?   I want to do
> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
> 100 MHz from 9.999999371 MHz)
> 

Do you want 0.1Hz precision for the clock in order of 100MHz ? Leaving
PLL issues aside, where are you going to achieve a 0.001ppm clock
source ?

I assume that you want to produce a clock with DDS-like circuit within
FPGA and then feed the resulting signal to the PLL in order to filter
out the jitter. It looks like you would need a very low-bandwidth PLL
feedback chain. Are you sure you are comfortable with gigantic
capacitors on your board and a lock time of 1 minute ?

Article: 55328
Subject: Re: Schmitt Trigger an a Virtex
From: "louis" <louis@zyflex.com.tw>
Date: Sun, 4 May 2003 19:41:54 +0800
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> ????? news:3EB18382.1AA2A5A1@xilinx.com...
> Here are two solutions:
> You can make any input into a Schmitt trigger, but it costs you an extra pin:
> 
> http://support.xilinx.com/support/techxclusives/6easy-techX37.htm
> 
> or you can make the inside circuit immune to double-triggering. See
> www.xilinx.com/xcell/xl34_54.pdf
> 
> I hope either of these circuits helps.
> Peter Alfke, Xilinx Applications
> 
Hello Peter,

  It should be http://www.xilinx.com/xcell/xl34/xl34_54.pdf

Best regards,
louis lin

> 
> Jock wrote:
> > 
> > Is it possible to define a Xilinx Virtex input as a Schmitt trigger?
> > 
> > On my application, some inputs have a 30ns rise time which seems to be
> > causing an intermittant timing problem. Reducing the input capacitance so I
> > get 10ns rise time fixes the problem, but I get RF problems elsewhere.


Article: 55329
Subject: cable length on homemade Parallel Cable III
From: ben@ben.com (Ben Jackson)
Date: Sun, 04 May 2003 12:52:08 GMT
Links: << >>  << T >>  << A >>
I just noticed that several of the commercially built Xilinx
Parallel Cable III setups use long (eg 6'), poorly shielded
cables on both the parallel and JTAG ends.

I was planning to lop off a few feet from an old parallel cable
and use that, but if I can get away with using a RJ45 header
and satin wire (or CAT5 gaining no particular TP advantage) or even
a 6' shielded parallel cable then I'm all for it.  Some designs do
this on the parallel side and use short flying leads, and some cram
the circuit into the DB25 housing and use the RJ45 leads for the
JTAG signals.

What can I get away with?  Most of the circuit looks like cruft
accumulated in repeated attempts to fix signalling problems, so
I'm wary of building an iffy programmer.

-- 
Ben Jackson
<ben@ben.com>
http://www.ben.com/

Article: 55330
Subject: Re: PLL chips
From: Allan Herriman <allan_herriman.hates.spam@agilent.com>
Date: Mon, 05 May 2003 00:07:34 +1000
Links: << >>  << T >>  << A >>
On Sun, 04 May 2003 01:35:29 -0000, hmurray@suespammers.org (Hal
Murray) wrote:

>Is there any obvious PLL chip to use with an FPGA?   I want to do
>things like generate 100.0003001 MHz from 10 MHz.  (Or generate
>100 MHz from 9.999999371 MHz)
>
>I did a quick search the other day and didn't see much.


I get an awful lot of hits when I search for "fractional-N PLL".


>I found lots of clock generation/distribution chips, typically 0 delay
>buffers but sometimes including mul/div by 2 or 4.
>
>There are a few chips that include mul/div registers, but they are
>small integers.  I want to put that logic in the FPGA so I can
>implement many low order bits.
>
>Are there any good articles on this aspect of PLLs?  I'm expecting
>there are some tricks for filtering out the low frequency noise
>injected by the occasional steps when the low bits accumulate to
>a whole tick and a cycle gets inserted/dropped.

You can work this one out for yourself: the low frequency jitter will
often be deterministic (often a sawtooth wave).  Deterministic implies
predictable, which implies that you can make "anti-noise" to
(partially) cancel the jitter.  
You can find some chips that do this by adding a compenstation current
to the output of the phase detector.  I don't recommend doing it
yourself in an FPGA, as the matching of the currents is a little
tricky if you want to get any reasonable cancellation.

That said, I've designed sub-ppm frequency offset circuits for
SONET/SDH clocks by using a straighforward phase accumulator in an
FPGA as the feedback divider in an PLL.


I second what the other posters said about reference tolerance and
loop bandwiths.

Regards,
Allan.

Article: 55331
Subject: Re: 802.11
From: "cfk" <cfk_alter_ego@pacbell.net>
Date: Sun, 04 May 2003 15:43:34 GMT
Links: << >>  << T >>  << A >>
Interesting you bring up firmware as opposed to hardware. That is one of the
key points I am struggling with. Some seem to feel that firmware consists of
everything in the FPGA, while others seem to think firmware is the
instructions to a CPU such as a RISC that is implemented in the FPGA and
runs software (firmware?). One of the reasons I am seeking this knowledge is
to sort the wheat from the chaff regarding whether or not there even should
be a CPU in a 802.11 MAC.

I can take it either way, however. I am still seeking an example of packet
framing at the lowest level of interface to a radio. Although the radio I am
contemplating is not exactly the same as currently perceived 802.11, it is
still similar in concept. Because of that, I am seeking an example, partial
or complete.

I am hoping that some of you may have some URL's with reference that can
help me understand how to put this all together.

Charles


"Eric Smith" <eric-no-spam-for-me@brouhaha.com> wrote in message
news:qh1xzfrvvs.fsf@ruckus.brouhaha.com...
> "cfk" <cfk_alter_ego@pacbell.net> writes:
> D Are there any examples of 802.11 verilog code available for appreciation
> > either partially or fully completed. I am looking mostly for examples
that I
> > can use to appreciate architecture designs, not looking for a complete
> > product. I have allready searched through opencores, just their ethernet
mac
> > is their. I am really looking for some additional knowledge on
> > implementation details of the 802.11 specific details such as the
various
> > services (authentification, association, MSDU delivery, SIFS/PIFS/DIFS
> > counters) and an example or two that I can study of their
implementation.
>
> A lot of that is normally done in firmware, not hardware.  The hardware
> typically only handles the lowest level of packet framing to interface to
> the radio.
>



Article: 55332
Subject: Re: cable length on homemade Parallel Cable III
From: Duane Clark <junkmail@junkmail.com>
Date: Sun, 04 May 2003 09:06:17 -0700
Links: << >>  << T >>  << A >>
Ben Jackson wrote:
> I just noticed that several of the commercially built Xilinx
> Parallel Cable III setups use long (eg 6'), poorly shielded
> cables on both the parallel and JTAG ends.
> 
> I was planning to lop off a few feet from an old parallel cable
> and use that, but if I can get away with using a RJ45 header
> and satin wire (or CAT5 gaining no particular TP advantage) or even
> a 6' shielded parallel cable then I'm all for it.  Some designs do
> this on the parallel side and use short flying leads, and some cram
> the circuit into the DB25 housing and use the RJ45 leads for the
> JTAG signals.
> 
> What can I get away with?  Most of the circuit looks like cruft
> accumulated in repeated attempts to fix signalling problems, so
> I'm wary of building an iffy programmer.
> 

I took the suggestion of someone here (sorry, I forget who) and added 
Schmidt trigger inputs (74HCT14) and a small RC filter (300ohm,68pF) on 
the CLK input. I have run it through several 6 foot parallel cables 
connected together, with absolutely no problems. I have never seen a bad 
load.

-- 
My real email is akamail.com@dclark (or something like that).


Article: 55333
Subject: Re: cable length on homemade Parallel Cable III
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 4 May 2003 18:13:06 +0200
Links: << >>  << T >>  << A >>
"Ben Jackson" <ben@ben.com> schrieb im Newsbeitrag
news:Y18ta.730234$F1.94332@sccrnsc04...
> I just noticed that several of the commercially built Xilinx
> Parallel Cable III setups use long (eg 6'), poorly shielded
> cables on both the parallel and JTAG ends.

> What can I get away with?  Most of the circuit looks like cruft
> accumulated in repeated attempts to fix signalling problems, so
> I'm wary of building an iffy programmer.

I suggest to put two schmitt-triggers (74HC14) in front of the TCK/CCLK and
TMS/PROGRAM line, and in front of them a RC-filter of lets say 330 Ohm/1nF.
This will get rid of bad signals. Works quite good with a 6 feet, aehhh 2m
cable ;-) The two schmitt-triggers are logically "invisible"

--
MfG
Falk





Article: 55334
Subject: Re: PLL chips
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Sun, 4 May 2003 18:14:51 +0200
Links: << >>  << T >>  << A >>
"Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag
news:vb8rj1h4742fe1@corp.supernews.com...

> Is there any obvious PLL chip to use with an FPGA?   I want to do
> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
> 100 MHz from 9.999999371 MHz)
>
> I did a quick search the other day and didn't see much.

Have a look at

www.analog.com

They have nice DDS chips.

--
MfG
Falk





Article: 55335
Subject: Re: use of DRAM as massive FIFO
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 04 May 2003 13:23:49 -0400
Links: << >>  << T >>  << A >>
ah wrote:
> 
> Hi
> Im currently working on a project which will have a camera data digitisted
> at 20MHz 16 bit data.
> Then  brought into FPGA  and converted to 32 bit data and then written into
> external SDRAM.
> The Data is then Read from the SDRAM back into FPGA and put onto USB Bus and
> then displayed screen.
> 
> I need the DRAM as I will need to hold up to 5 frames of Data
> 1 Frame will be 0.5Mb so 5 frames will be 2.5MB
> 
> Would anyone have experience of this type of project and if so any advice
> would be gratefully recieved.
> 
> Andy

I have done exactly this design before.  I built a similar device to
store data on RAID hard drives.  I used the four pages in SDRAM to
implement a four way buffer which worked well.  Separating the banks
made the controller design a touch easier, but it is no big deal once
you understand how SDRAMs work.  

I am not sure how well you will find USB to support a 320 Mbit/s data
throughput.  The max speed is 480 Mbit/s.  Have you done any testing to
see how fast you can get it to actually run?  Burst rate and sustained
throughput are two different things.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 55336
Subject: Re: cable length on homemade Parallel Cable III
From: "Laurent Gauch, Amontec" <laurent.gauch@amontec.com>
Date: Sun, 04 May 2003 19:37:14 +0200
Links: << >>  << T >>  << A >>
Ben Jackson wrote:
> I just noticed that several of the commercially built Xilinx
> Parallel Cable III setups use long (eg 6'), poorly shielded
> cables on both the parallel and JTAG ends.
> 
> I was planning to lop off a few feet from an old parallel cable
> and use that, but if I can get away with using a RJ45 header
> and satin wire (or CAT5 gaining no particular TP advantage) or even
> a 6' shielded parallel cable then I'm all for it.  Some designs do
> this on the parallel side and use short flying leads, and some cram
> the circuit into the DB25 housing and use the RJ45 leads for the
> JTAG signals.
> 
> What can I get away with?  Most of the circuit looks like cruft
> accumulated in repeated attempts to fix signalling problems, so
> I'm wary of building an iffy programmer.
> 
Our Chameleon POD has an onboard true 1284 transciever, we have do test 
with a 16 meters cable (parallel port to POD) without trouble :-)
www.amontec.com/chameleon.shtml

It can be use like a Xilinx Parallel Cable III, ByteBlaster, Wiggler, 
Raven, and many more JTAG configurations

Amontec Team


Article: 55337
Subject: LPM_ROM problem with Altera EP1K50 parts
From: "FPGA user" <nospam@aol.com>
Date: Sun, 04 May 2003 18:26:28 GMT
Links: << >>  << T >>  << A >>
Hi,

Has anyone used LPM_ROM megafunctions in an EP1K50?  They do NOT seem to
work in simulation.  However, an EP1K30 or an EP1K100 DOES work.

I'm using the latest version of MaxPlus II, and created a design with only
that megafunction, unclocked, with addr in/data out ports, and an
initialization file.  I organized the part as 64 16 bit words.

Compilling and changing nothing but the device shows up the problem.


Thanks!



Article: 55338
Subject: Microcode in FPGAs (was 802.11)
From: hmurray@suespammers.org (Hal Murray)
Date: Sun, 04 May 2003 18:54:10 -0000
Links: << >>  << T >>  << A >>
> One of the reasons I am seeking this knowledge is
> to sort the wheat from the chaff regarding whether or
> not there even should be a CPU in a 802.11 MAC.

Most of the time, it's seemed obvious to me.

I think the key idea is how many states do you have in your
state machine.  I'm talking major states.  You can have a
counter off to the side if you need to do something N times
or pause for N cycles.

When the number of states gets big enough, it seems simpler
to turn the problem into software and describe the logic as
a program.

It probably interacts somewhat with your implementation
technology.

This was discussed here a while ago.  Somebody mentioned
an old AMD book.  There may be recent app notes.  If not,
there should be.  It fits well with on-chip RAMs.


The technology that I'm familiar with was popular 20
years ago.  (Think TTL and DIPs.)  The basic element
is a big ROM to hold the instructions. There are
the obvious time/space tradeoffs in decoding instructions.
ROMs are dense so the instructions were usually quite wide.
One field was the next-instruction-address.  That is all
instructions jumped someplace.  There was no adder on the PC.

Branching can be done by having a MUX on the bottom bits of the
PC.  The mux is controled by a branch field in the instruction.
You can make the mux wider to do an N way dispatch.
This was usually the critical path.

Branching usually has pipeline delays.  You head will hurt
when you first try writing the software.  After a while you
get used to it.

If you need to do arithmetic, you can build an ALU
and registers and ... and make the instruction wider
to control it.  The AMD 2901 and 29116 were great for
this.

It takes a while to setup that type of environment.  You
have to write an assmebler/loader.  After you have done
it a few times you can just hack the previous one.
After you finally get everything in place, it's only a few
minutes to make a 2 instruction change.  (Unless your ROM is
full.)


-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 55339
Subject: Re: PLL chips
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Sun, 04 May 2003 19:13:51 GMT
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> Is there any obvious PLL chip to use with an FPGA?   I want to do
> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
> 100 MHz from 9.999999371 MHz)
> 
> I did a quick search the other day and didn't see much.
> 
> I found lots of clock generation/distribution chips, typically 0 delay
> buffers but sometimes including mul/div by 2 or 4.
> 
> There are a few chips that include mul/div registers, but they are
> small integers.  I want to put that logic in the FPGA so I can
> implement many low order bits.
> 
> Are there any good articles on this aspect of PLLs?  I'm expecting
> there are some tricks for filtering out the low frequency noise
> injected by the occasional steps when the low bits accumulate to
> a whole tick and a cycle gets inserted/dropped.
> 

Have a look at :

Analog Devices ADF4001 or similar.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 55340
Subject: materail needed on Dynamic Reconfiguration of IP core
From: paraagv@hotmail.com (paraag)
Date: 4 May 2003 12:17:19 -0700
Links: << >>  << T >>  << A >>
Hi

Can anyone tell me where I can find Material to read about dynamic
reconfigurabilty of Ip cores ( soft cores)

thanks
Paraag

Article: 55341
Subject: Re: 2.5V switching regulator for Spartan 2
From: "jerry1111" <No_this_fucking_spam_jerry1111@wp.pl>
Date: Sun, 4 May 2003 21:46:23 +0200
Links: << >>  << T >>  << A >>
>> Are you soldering down the power pad on the bottom of the part?  I

> I don't know what to tell you.  I am fairly sure the pad on the bottom
> is just for thermal dissipation.  But I do belive they talk about
> signal sensitivity of this pad, so it might not be a good idea to

I missed this thread. Solution is quite simple - place one via with >1mm hole
under this 'hidden' pad. Solder the part and, as the very last step, put some
solder through via - maybe not so much thermal contact, but at least it's possible
to assembly it by hand.

-- 
jerry

"The day Microsoft makes something that doesn't suck is probably
the day they start making vacuum cleaners." - Ernst Jan Plugge



Article: 55342
Subject: Re: PLL chips
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Sun, 04 May 2003 20:55:32 GMT
Links: << >>  << T >>  << A >>


Rene Tschaggelar wrote:
> Hal Murray wrote:
> 
>> Is there any obvious PLL chip to use with an FPGA?   I want to do
>> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
>> 100 MHz from 9.999999371 MHz)
>>
>> I did a quick search the other day and didn't see much.
>>
>> I found lots of clock generation/distribution chips, typically 0 delay
>> buffers but sometimes including mul/div by 2 or 4.
>>
>> There are a few chips that include mul/div registers, but they are
>> small integers.  I want to put that logic in the FPGA so I can
>> implement many low order bits.
>>
>> Are there any good articles on this aspect of PLLs?  I'm expecting
>> there are some tricks for filtering out the low frequency noise
>> injected by the occasional steps when the low bits accumulate to
>> a whole tick and a cycle gets inserted/dropped.
>>
> 
> Have a look at :
> 
> Analog Devices ADF4001 or similar.

I forgot to mention the resolution below 1kHz being unreal.
That means the mixer runs at that low frequency and the dividers
have rather high values. This leads to increased phase noise.
Beside that the reference has to be even more stable than that.

Analog Devices has a simulation program 'ADISim PLL' that favours
their chips but nevertheless give valuable insight into the
dependencies of values on parameters. Eg the influence of the
bias current of the loop amplifier to sidebands.
Recommended.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 55343
Subject: Re: PLL chips
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Mon, 05 May 2003 09:13:27 +1200
Links: << >>  << T >>  << A >>
Hal Murray wrote:
> 
> Is there any obvious PLL chip to use with an FPGA?   I want to do
> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
> 100 MHz from 9.999999371 MHz)
> 
> I did a quick search the other day and didn't see much.
> 
> I found lots of clock generation/distribution chips, typically 0 delay
> buffers but sometimes including mul/div by 2 or 4.
> 
> There are a few chips that include mul/div registers, but they are
> small integers.  I want to put that logic in the FPGA so I can
> implement many low order bits.
> 
> Are there any good articles on this aspect of PLLs?  I'm expecting
> there are some tricks for filtering out the low frequency noise
> injected by the occasional steps when the low bits accumulate to
> a whole tick and a cycle gets inserted/dropped.

 Step effects sounds more like Rate multipliers, or the accumulator
based 
direct frequency synthesisers ?

 In the pure form, a Phase Locked Loop is exactly that, it uses
an analog signal to control a VCO, and there are no jumps. 
 They do however, have noise sidebands, and there are many tricks in the
analog
domain, to give fast locking, then lower in-lock noise.

 The VCO also is important, and the narrower the lock-band, the higher
you can make the Q of the VCO. Helical resonators work well at higher
frequencies.

 I have seen notes on the GHz synthesisers for Phones/Bluetooth
mentioning Delta-Sigma & Fractional N PLLs, so these could give good
clues to ways to get fine steps sizes AND high loop bandwidths - these
designs will be working to keep as much of the 'work' in the 
digital domain as possible, so should be good for FPGA fabric.

-jg

Article: 55344
Subject: buffering
From: "Domagoj" <domagoj@engineer.com>
Date: Sun, 4 May 2003 23:21:22 +0200
Links: << >>  << T >>  << A >>
Hi

A project I'm working on requires in one stage to feed 64 13-bit values into
8 buffers (dynamic
shift registers) in <10 cycles. Input values can be seen as divided in 8
groups, and each group has
to be shifted into the buffer in some order in <10 cycles. Is there any
other trick to implement it, except
by using either three-state buses or 104  8x1 multiplexors (in 8 cycles) ?

Those 64 values are all computed concurrently every 10 cycles and stored
into registers, but other
storage could also be used (like select ram). 10 cycles limit is the lower
bound, but changing it
would require heavy redesign at the moment (and lower throughput, of
course).

thx,

--
        Domagoj Babic
domagoj (et) engineer.com



Article: 55345
Subject: Re: PLL chips
From: jakespambox@yahoo.com (Jake Janovetz)
Date: 4 May 2003 15:30:58 -0700
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message news:<vb8rj1h4742fe1@corp.supernews.com>...
> Is there any obvious PLL chip to use with an FPGA?   I want to do
> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
> 100 MHz from 9.999999371 MHz)
> 
> I did a quick search the other day and didn't see much.
> 
> I found lots of clock generation/distribution chips, typically 0 delay
> buffers but sometimes including mul/div by 2 or 4.
> 
> There are a few chips that include mul/div registers, but they are
> small integers.  I want to put that logic in the FPGA so I can
> implement many low order bits.
> 
> Are there any good articles on this aspect of PLLs?  I'm expecting
> there are some tricks for filtering out the low frequency noise
> injected by the occasional steps when the low bits accumulate to
> a whole tick and a cycle gets inserted/dropped.

For the kind of tuning you want, I think the best solution will be a
DDS chip like the Analog Devices AD9852.  It runs at a sample rate of
300 MSPS which will provide clock output (built-in comparator) just
above 100 MHz.  It also has a built-in PLL to mult the incoming clock
by up to 20.  (not quite enough for 10 MHz).

I have a board with both this DDS and a Cypress PLL (22150) on it for
clocking.  They are both really nice for clocking FPGAs, but the DDS
provides far better tuning ability than even a typical fractional PLL.

Now, if you want to do this in the FPGA, you could implement the DDS
using internal logic, then use a simple R-2R DAC on the output with a
comparator and feed the clock back into the FPGA.  The reference
clock, however, will probably need some multiplying to get up to the
speeds you're talking about.  Cost-wise, it's probably better to use a
DDS.

As another poster suggested, you'll need an OCXO or something to
assure the stability you imply.

   Cheers,
   Jake

Article: 55346
Subject: Re: Two RAMs in one slice
From: "Jason T. Wright" <ruminat@pacbell.net>
Date: Mon, 05 May 2003 06:35:14 GMT
Links: << >>  << T >>  << A >>
Yeah, the feedback cost has to be considered.  Sometimes it's worth it,
and sometimes it's not.

Jason

Gilad Cohen wrote:
> 
> Jhon,
> Maybe I didn't mention it , but I'm working with Virtex II.
> 
> In Virtex II slices, the D input to the lower LUT can also come from
> an input called "ALTDIG".
> 
> The reason for the
> That solves my problem with the MUXF5 control.
> 
> The reason for the one-slice packing is that the slice is of repicated
> hundreds/thousands of times. The packing is essential to my design.
> 
> Jason,
> I like your idea about the feedback. The problem is that an outside
> mux will cost me more slices. I would be better off putting only one
> RAM per slice.

Article: 55347
Subject: Ibis for Cyclone?
From: jonesky1@hotmail.com (Joona R)
Date: 5 May 2003 03:52:27 -0700
Links: << >>  << T >>  << A >>
Hi!

Ibis model for Cyclone is coming soon, promises Altera's web page.
Does anyone have a specific information of relase date or something?
Is there some compatible models available now, or some other way?

I should simulate PCB with Expedition PCB & Signal Vision/Analyzer.

Thanks,
 Joona

Article: 55348
Subject: PLL in fpga
From: "sudip saha" <sudip.saha@philips.com>
Date: Mon, 5 May 2003 04:01:27 -0700
Links: << >>  << T >>  << A >>
Hi All,
in Altera Apex20K we can use pll and generate higher clock. But the  minimum frequency for the clock input to the PLLs are 1.5 Mhz.
is there any way to use a slower clock like 1 mhz and generate a high speed clock?
In Xilinx Fpgas, is there any PLL options?
In a nutshell, I want to generate a high speed clk from a 1 mhz clk and both the clocks should be locked.
Your suggestions will be of great help.

Article: 55349
Subject: Re: PLL chips
From: Andras Tantos <andras_tantos@yahoo.com>
Date: Mon, 05 May 2003 06:05:41 -0700
Links: << >>  << T >>  << A >>
Hal Murray wrote:

> Is there any obvious PLL chip to use with an FPGA?   I want to do
> things like generate 100.0003001 MHz from 10 MHz.  (Or generate
> 100 MHz from 9.999999371 MHz)
> 
> I did a quick search the other day and didn't see much.
> 
> I found lots of clock generation/distribution chips, typically 0 delay
> buffers but sometimes including mul/div by 2 or 4.
> 
> There are a few chips that include mul/div registers, but they are
> small integers.  I want to put that logic in the FPGA so I can
> implement many low order bits.
> 
> Are there any good articles on this aspect of PLLs?  I'm expecting
> there are some tricks for filtering out the low frequency noise
> injected by the occasional steps when the low bits accumulate to
> a whole tick and a cycle gets inserted/dropped.
>

Take a look at the Cypress devices (www.cypress.com). I just started using
the CY22393 from them. I don't have any experiece yet except that this damn
thing comes with all output disabled (even the direct buffered clock
output). Have i2c programming interface, EEPROM to store configuration,
166MHz max output freq, and best of all, available in small quantities from
DigiKey (www.digikey.com).

Regards,
Andras Tantos



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