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"Austin Lesea" <Austin.Lesea@xilinx.com> schrieb im Newsbeitrag news:3EBC16D2.953822CF@xilinx.com... > Most lithium cells are rated at 15 years, abs min, with a suitable small > load. Since the memory is < 100 nA, that is (probably) less than the > leakage from the battery holder. How about a big (gold)cap + a recharge diode + photo cell (if there is any chanche that light fall onto the PCB) ?? I guess a thermonuklear battery for satallite apps is just a little overkill ;-)) > > Maybe stash the keys in flash and have the uP reload > > stealthily on some date related command. This sounds NOT like a good idea. AFAIK the trick is to hold the keys inside the FPGA in SRAM cells, so a hacking attack is EXTREMLY difficult to impossible. An external uC can easyly be cracked. -- MfG FalkArticle: 55501
JP Nicholls wrote: > > We want to use the encrypted bitstream option of a Xilinx FPGA in order > to protect IP. However we are having trouble sourcing a suitable battery. > > Our product needs to have a shelf life of 10 years plus. The customer might > stick the unit on a shelf in a cold dark warehouse and not use the product for > several years, but it must still work. If it fails on operation that has very > expensive consequences for our customers - and us. > > Has anybody found a suitable battery for this? > > Are there any alternative way to encrypt the FPGA bitstream? The bitstream and > any keys must not be accessible to any probes. Don't know about the encryption. Personally, I don't trust any encryption unless NSA is using it. Even then I fully expect the Government to be able to crack it, especially DES. As to the battery, I expect you will do ok on the 10 year lifespan as long as you can be assured of environmental controls. *ALL* batteries are little chemical plants and chemistry is strongly affected by temperature. Just like semiconductors, as you raise the temperature, the leakage current (self discharge rate) goes up very quickly. The standard CR type Lithium cells top out around 60C-70C according to the book and will suffer a greatly reduced shelf life if stored at temps above this. There is a BR type designed for better high temperature storage and operation. I would recommend this if your devices might be stored in a HOT warehouse. Cold should not be a problem unless it is at the poles (< -40). Damp can be a problem you have *any* condensation. But a sealed bag with a bit of desiccant should take care of that very easily. And of course proper cleaning of the board after manufacturing is essential. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55502
On Sat, 10 May 2003 08:33:16 -0700, rickman wrote: > JP Nicholls wrote: >> >> We want to use the encrypted bitstream option of a Xilinx FPGA in order >> to protect IP. However we are having trouble sourcing a suitable >> battery. >> >> Our product needs to have a shelf life of 10 years plus. The customer >> might stick the unit on a shelf in a cold dark warehouse and not use >> the product for several years, but it must still work. If it fails on >> operation that has very expensive consequences for our customers - and >> us. >> >> Has anybody found a suitable battery for this? >> >> Are there any alternative way to encrypt the FPGA bitstream? The >> bitstream and any keys must not be accessible to any probes. > > Don't know about the encryption. Personally, I don't trust any > encryption unless NSA is using it. Even then I fully expect the > Government to be able to crack it, especially DES. > > As to the battery, I expect you will do ok on the 10 year lifespan as > long as you can be assured of environmental controls. *ALL* batteries > are little chemical plants and chemistry is strongly affected by > temperature. Just like semiconductors, as you raise the temperature, > the leakage current (self discharge rate) goes up very quickly. The > standard CR type Lithium cells top out around 60C-70C according to the > book and will suffer a greatly reduced shelf life if stored at temps > above this. > > There is a BR type designed for better high temperature storage and > operation. I would recommend this if your devices might be stored in a > HOT warehouse. Cold should not be a problem unless it is at the poles > (< -40). Damp can be a problem you have *any* condensation. But a > sealed bag with a bit of desiccant should take care of that very easily. And remember that that bag better not be the black carbon filled variety or some of the metalized types - they can short out the Lithium cell! Best thing is to add some mechanical shield to the card so that the Lithium cell terminals plus any cell related component pins cannnot be inadvertantly shorted out by customer handling. Years ago we made Battery backed CMOS RAMDISKs and they were quite reliable, many still in service 10 years later. The one thing that would damage the information on the disk was customers inadvertantly shorting out the Lithium cell during handling... PCW > And of course proper cleaning of the board after manufacturing is > essential.Article: 55503
In article <3EBD0DAC.1FD2A810@yahoo.com>, rickman <spamgoeshere4@yahoo.com> wrote: >Don't know about the encryption. Personally, I don't trust any >encryption unless NSA is using it. Even then I fully expect the >Government to be able to crack it, especially DES. It's 3DES, which I'd trust. For block cyphers, trust AES first, but if you are dealing with an older project, you can trust 3DES. DES however is a joke these days. Attacks would probably not be directly on the cypher, but attacks on the key storage in the FPGA (by hitting with X-rays and then probing to get the probable bit states as a seed for decryption) or a power-based attack feeding in dummy data. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 55504
Hi, I have a lab assignment where students complete the design of a small FPGA (2 LE, 2 IO) that has a bitstream of 196 bits. Then, they have to manually map, place, and route a 2-bit counter in that FPGA and generate a bitstream. It is kind of recursive. A Xilinx FPGA is configured with the small FPGA design, and then the students load the small FPGA (implemented in the Xilinx FPGA) with their 196-bit bitstream. http://www.engr.sjsu.edu/~crabill/lab5.pdf There is no way you are going to get a "simple" exercise based on a commercial FPGA. This is an old part and even so, hardly simple: http://www.engr.sjsu.edu/~crabill/spartan.pdf The FPGA in the lab assignment is about as simple as you can probably get and still make a useful example out of it. Right now the lab is in schematic for 2.1i, but I'll be updating it in the Fall for verilog and 4.2i. Hope that helps, Eric Alex Gibson wrote: > > "Wolfgang Schmiesing" <wolfgang@byke.com> wrote in message > news:eb5a527f.0305090707.520af32@posting.google.com... > > I am planning to write a tutorial on FPGA-programming for students. > > As an excercise I would like the students to "program" a very simple > > logic function using an interactive representation of an FPGA. Due to > > limitited display size the graphical representation of the FPGA has to > > be very simple. > > > > Now I'm searching for detailed information about the interconnect > > structure of > > FPGAs using antifuses. How are the in-/output pins connected to the > > relating CLBs? I haven't found anything yet. Can anyone help me? > > have you looked at the info and links > on the xilinx xup(xilinx university program) site ? > > http://xup.msu.edu/ > > http://xup.msu.edu/students/tutorials.htm > http://xup.msu.edu/students/examples.htm > > http://www.xilinx.com/univ/index.htmArticle: 55505
"Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> ha scritto nel messaggio news:D6bua.99171$iy5.3041077@twister2.libero.it... > http://direct.xilinx.com/bvdocs/publications/ds123.pdf > > Do you know if these devices are already in production? If > not, when > will they be (hopefully :))? Thank you for the answers. Yes, I'm going of course to ask some informations to my distributor, but now I know that the devices already exist and are available, maybe I can have more success (my distributor is a bit lazy, unless of course I want to buy a lot of pieces; I wonder why ;-)). -- LorenzoArticle: 55506
It is true that there are dedicated routing paths for the input of the = DLL from these sources. However, it is possible (and legal) to route any = signal to the input of the DLL. This routing will not take a dedicated = routing path, and hence will have no guaranteed timing. If you attempt to do this, 'map' will generate an error, informing you = that you must set the XIL_MAP_ALLOW_ANY_DLL_INPUT environment variable. = Setting this variable will allow the map/par to complete. That being said, since there is no guaranteed timing for this path, = there aren't a whole lot of reasons why you would want to do this. For = example, trying to clock an IOB flop with this clock will have = unpredictable setup and hold time requirement... Avrum "Gilad Cohen" <gilad_coh@walla.co.il> wrote in message = news:ee7d5e3.0@WebX.sUN8CHnE... Hello Karthik,=20 The DLL input can be one of the following three:=20 1. BUFG - Internal global clock buffer=20 2. IBUFG - Global clock input buffer on the same edge of the device = (top or bottom)=20 3 - IO_LVDS_DLL - the pin adjacent to a global clock pin.=20 What you need to do is insert you signal from the internal logic to a = global clock buffer, and from there to the DLL CLKIN input.=20 Gilad.Article: 55507
Wow, ... That is so "way cool"!!! Great class. On Sat, 10 May 2003 08:27:17 -0700, Eric Crabill <eric.crabill@xilinx.com> wrote: >Hi, > >I have a lab assignment where students complete the design >of a small FPGA (2 LE, 2 IO) that has a bitstream of 196 >bits. > > ..... > >Hope that helps, >Eric Philip Freidin FliptronicsArticle: 55508
Hi, What is the software that actually supports this device? MaxPlus does not. Quartus II also doesn't know this device. Any help is welcome. Luis Cupido. (email, remove the kkk)Article: 55509
11-May-03 03:54 lc wrote: l> What is the software that actually supports this l> device? MaxPlus does not. l> Quartus II also doesn't know this device. MAX+II 9.25 full version has in device list: EPF8188AQC208-2,-3,-4 EPF8188AQI208-3,-4 EPF8188AQC240-2,-3,-4 EPF8188ARC240-2,-3,-4 EPF8188ARI240-4 EPF8188AGC232-2,-3,-4 wbr, -- /* Oleksandr Redchuk, Kyiv, Ukraine */ /* real '\x40' real '\x2E' kiev '\x2E' ua */Article: 55510
> > In case you didn't look, it was four XC2V4000 in BGA package, but they > needed to be reballed. I don't know how hard that is to do, but they didn't > sell with a starting bid of $995 > > How much should they cost new? > > -- glen Im not suprised they didnt sell. Who in thier right mind would shell out that kind of money for untested parts with no money back if they are faultyArticle: 55511
Hi all, I am interested to build a PacMan game with Xilinx FPGA. I am going to use Verilog. How many gates do you think is required for this project? What type of chip should I consider for this project? Thanks! HendraArticle: 55512
I'm sure you got your inspiration from http://www.fpgaarcade.com/ Some of the ongoing discussions can also be found at www.opencores.org mailing lists "Kyle Davis" <kyledavis@nowhere.com> wrote in message news:qKnva.709$Wy3.57@newssvr16.news.prodigy.com... > Hi all, > I am interested to build a PacMan game with Xilinx FPGA. I am going to use > Verilog. How many gates do you think is required for this project? What type > of chip should I consider for this project? > Thanks! > > Hendra > >Article: 55513
Pacman is a periodic final project for the Stanford intro to logic design class--most recently last quarter. We use the Xess XSA-100 boards: http://www.xess.com/prod026.php3. Most of the projects use between half and two thirds of the Spartan2 XC2S100 FPGA for the basics of game play and a few bells and whistles. As always, motivated and clever folks could add features utilizing the largest FPGAs available but you can certainly make a nice game with a XC2S100 size device. One group even implemented A-star search in gates for the ghost movement. Those ghosts were pretty hard to evade! :-) Paul Kyle Davis wrote: > > Hi all, > I am interested to build a PacMan game with Xilinx FPGA. I am going to use > Verilog. How many gates do you think is required for this project? What type > of chip should I consider for this project? > Thanks! > > HendraArticle: 55514
Anybody know where I can buy a single fg680? I cannot even get the price. Thanks. WeiArticle: 55515
"lc" <cupido@kkk.mail.ua.pt> wrote in message news:<1052621182.389816@newsfront2>... > Hi, > > What is the software that actually supports this > device? MaxPlus does not. > Quartus II also doesn't know this device. > > Any help is welcome. > > Luis Cupido. > (email, remove the kkk) Max+plus II 10.1 supports EPF81188AQC208, EPF81188AQC248 and EPF81188ARC240. However, I had the impression that the whole FLEX8000 family is obsolete for 6 or 7 years now. FLEX6000 devices are better for just about everything and they are near obsolete themselves. Did I miss something ?Article: 55516
Steve, Just a good low leakage 100uF cap is all that is needed with a resistor from the battery to the cap (so even if you short the battery, it doesn't discharge the cap immediately and lose the keys). The only difference between our solution and Dallas Semi is that they encapsulate the lithium battery in the package. Austin Steve Casselman wrote: > > Why not put two batteries on it. Then you can swap one out while the other > is still working. > > Steve > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3EBC2559.6BED3FBE@xilinx.com... > > I am more positive. > > Since the current drawn from the battery is essentially zero, you are > > only limited by its shelf life, and Lithium batteries are very good in > > that regard. Just make sure that your pc-board is clean and has no > > acidity left on the surface, causing leakage current. > > > > Also remember that you can exchange the battery ( but only while the > > device is powered up ) as often as you want. > > While Vcc is active, Vcc supports the key information, the battery does > nothing. > > > > Peter Alfke, Xilinx Applications > > ================= > > Mike Treseler wrote: > > > > > > JP Nicholls wrote: > > > > We want to use the encrypted bitstream option of a Xilinx FPGA in > order > > > > to protect IP. However we are having trouble sourcing a suitable > battery. > > > > Our product needs to have a shelf life of 10 years plus. > > > > > > I don't think there is such a battery. > > > > > > You need to at least provide some way for the customer to > > > reload the keys after replacing the battery. > > > > > > Maybe stash the keys in flash and have the uP reload > > > stealthily on some date related command. > > > > > > You also have to consider whether this level of security > > > is worth the bother to your customers. > > > > > > Remember that bitstream encryption has zero value for them. > > > > > > -- Mike TreselerArticle: 55517
Rick, Did you know that all banking is done by triple DES today? Don't trust banks, too? Austin rickman wrote: > > JP Nicholls wrote: > > > > We want to use the encrypted bitstream option of a Xilinx FPGA in order > > to protect IP. However we are having trouble sourcing a suitable battery. > > > > Our product needs to have a shelf life of 10 years plus. The customer might > > stick the unit on a shelf in a cold dark warehouse and not use the product for > > several years, but it must still work. If it fails on operation that has very > > expensive consequences for our customers - and us. > > > > Has anybody found a suitable battery for this? > > > > Are there any alternative way to encrypt the FPGA bitstream? The bitstream and > > any keys must not be accessible to any probes. > > Don't know about the encryption. Personally, I don't trust any > encryption unless NSA is using it. Even then I fully expect the > Government to be able to crack it, especially DES. > > As to the battery, I expect you will do ok on the 10 year lifespan as > long as you can be assured of environmental controls. *ALL* batteries > are little chemical plants and chemistry is strongly affected by > temperature. Just like semiconductors, as you raise the temperature, > the leakage current (self discharge rate) goes up very quickly. The > standard CR type Lithium cells top out around 60C-70C according to the > book and will suffer a greatly reduced shelf life if stored at temps > above this. > > There is a BR type designed for better high temperature storage and > operation. I would recommend this if your devices might be stored in a > HOT warehouse. Cold should not be a problem unless it is at the poles > (< -40). Damp can be a problem you have *any* condensation. But a > sealed bag with a bit of desiccant should take care of that very > easily. > > And of course proper cleaning of the board after manufacturing is > essential. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55518
"Simon Peacock" <nowhere@to.be.found> schrieb im Newsbeitrag news:3ebcff76@news.actrix.gen.nz... > There are of course secure micros, Dallas/Maxium make them, battery backed > and the entire code is stored in ram, and encrypted differently each time > you program it. The also do the one touch thing, with encrypted memory to > boot Sure, but that's not the point here. If the FPGA loses its battery voltage to keep the DES keys, you need to reload the unencryptes key over some IO-Pins of the micro into the FPGA. So no security here. -- MfG FalkArticle: 55519
On a sunny day (Fri, 9 May 2003 11:54:27 +0100) it happened "kryten_droid" <kryten_droid@ntlworld.com> wrote in <SQLua.908$4P3.333@newsfep3-gui.server.ntli.net>: > >This stack might remove the need for any kind of backplane in your rack. You >might just need the one base board to stuff data in and out. It looks like there wll be no backplane, but 64 pol AC connectors with wiring. Copper strips on some pins connected together for the big amps (with 10 cards and 5 on a card this would be quite a bit). >Your spec adds up to a count of 800k x 50 per rack. Have been doing some reading , and also in XCell, now I think I am becoming a Virtex or at least Spartan III fan.... >The BurchEd has a 300E part, so you would need 134 such boards split among a >dozen or so racks. Yes I have been to that site, and almost ordered one. The Aussie dollars confused me a bit though. >FPGA's dedicated to one specific task like yours have been used to search >DNA sequences for genome mapping projects. Literally hundreds of times >faster than GHz desktops! You might have a look to see if you can >buy/borrow/rent such machines from people who manufacture them. Well, I was thinking of making my own, for sure someone will be wanting to brute force something. With an extra card in the rack with a processor to dynamically configure the FPGAs (so no serial EEPROM) and a power supply module, you could stack these racks to increase power. I have made designs with 20 double height racks (no FPGA in that) many years ago that actually needed a gas cooler to keep it cool (10 kW). In those systems I also used no backplane, but 64 pol AC and special connectors (for HV output). I had the boards made for these, they offered me a good deal on the backplanes, but wiring it all up was only a couple of days with 2 engineers. >On the other hand, those people market their machines as some kind of >miracle, and probably price them to match. The quintessence is just pumping >the search sequence shift registers and xor-gates to detect shorter >fragments. Yes but timing is a problem, at least now for me, see my other post. I like the idea in that picture with the FPGA on a board above the other chips, usually there is some space in that direction. Regards JanArticle: 55520
OK, so I have DES working at 100 MHz clock, wanted to go to 200 MHz, and use the 4 phase clock from the clock doubler. This is the 4 x multiplier as in the synthesis templates in the webpack. Now it did not work anymore, had a look at the timing analyzer: Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ CLKIN |CLK0 | 4.628| CLKIN |CLK180 | 4.647| CLKIN |CLK270 | 4.299| CLKIN |CLK2X | 8.436| CLKIN |CLK4X | 8.445| CLKIN |CLK90 | 4.307| ---------------+---------------+---------+ Now if I understand this right, CLK90 comes before CLK0, CLK270 comes before CLK90, then CLK0 and finally CLK180? Also the delays between the clock phases are all different. CLK270, CLK90, CKL0, CLK180 This is all with 50MHz clock on a Spartan II. Makes no sense, so what is the matter here? Simply too fast? Also how can you view those nice timing *waveforms* WITHOUT having to buy a ++++$ piece of extra soft? JanArticle: 55521
Hey I'm new on this group and especialy in using CPLD products. What I want to do is to create buffer betwen ISA bus and my devices and I was wondering if it is possible by using XC9536 ? Does anybody know if this chip chas 3-state gates ? Secound my question is : Could anybody tell me how to start programing this chips. What kind of soft and spec I need to create some simple programs for this chips and finally how to upload this programs to the chip ? thank for any advices ! GorgoArticle: 55522
I'm looking at the XSA100 for a project, but there's one thing I can't seem to find in the literature. What's the speed grade of the XC2S100 part on the board? "Paul Hartke" <phartke@Stanford.EDU> wrote in message news:3EBE10BC.22087B6E@Stanford.EDU... > Pacman is a periodic final project for the Stanford intro to logic > design class--most recently last quarter. We use the Xess XSA-100 > boards: http://www.xess.com/prod026.php3. Most of the projects use > between half and two thirds of the Spartan2 XC2S100 FPGA for the basics > of game play and a few bells and whistles. As always, motivated and > clever folks could add features utilizing the largest FPGAs available > but you can certainly make a nice game with a XC2S100 size device. > > One group even implemented A-star search in gates for the ghost > movement. Those ghosts were pretty hard to evade! :-) > > Paul > > Kyle Davis wrote: > > > > Hi all, > > I am interested to build a PacMan game with Xilinx FPGA. I am going to use > > Verilog. How many gates do you think is required for this project? What type > > of chip should I consider for this project? > > Thanks! > > > > HendraArticle: 55523
Gorgo wrote: > I'm new on this group and especialy in using CPLD products. > What I want to do is to create buffer betwen ISA bus and my devices > and I was wondering if it is possible by using XC9536 ? It is certainly possible. You should also consider the XC9536XL which is cheaper but requires a Vcc = 3.3V. It has 5V-tolerant inputs, so it also works directly with the ISA bus and other TTL-level stuff. > Does anybody know if this chip chas 3-state gates ? Each pin is controlled by a macrocell, and it can be permanently tristated (pin is input), permanently enabled (pin is output), or output buffer enable can be controlled by a product term or two global output enable signals (GTS1/GTS2). Check figure 10 (I/O Block and Output Enable Capability) in the XC9500 family datasheet: http://direct.xilinx.com/bvdocs/publications/9500.pdf > Secound my question is : > > Could anybody tell me how to start programing this chips. What kind > of soft and spec I need to create some simple programs for this chips > and finally how to upload this programs to the chip ? For the design I use VHDL which I learned from Kevin Skahill's book "VHDL for Programmable Logic". Others use Verilog. You can create XC9500 designs in both VHDL and Verilog with Xilinx's free WebPack software. You can either program the CPLD in a stand-alone programmer before mounting it on the PCB, like an EPROM, or you can program it in-system using a JTAG cable. The first method is only really interesting for high-volume production. Xilinx makes the "Xilinx Parallel Cable IV" box which connects to your PC's parallel port. I believe you can also build your own cable -- the "Parallel Cable III" box only contains a 74HCT chip and a few passive parts. Karl OlsenArticle: 55524
Thanks Michael, Interesting ! ... I'm running max+PlusII 10.2 and never occurred to me to try out 10.1. I will do... It is just that I have about 16 devices of those, and it is for a non-professional application where I would made the experiment for 'free' If I get serious about it I will probably make it in an up-to-date device. Luis Cupido. "Michael S" <already5chosen@yahoo.com> wrote in message news:f881b862.0305110648.32a77322@posting.google.com... > "lc" <cupido@kkk.mail.ua.pt> wrote in message news:<1052621182.389816@newsfront2>... > > Hi, > > > > What is the software that actually supports this > > device? MaxPlus does not. > > Quartus II also doesn't know this device. > > > > Any help is welcome. > > > > Luis Cupido. > > (email, remove the kkk) > > Max+plus II 10.1 supports EPF81188AQC208, EPF81188AQC248 and > EPF81188ARC240. > > However, I had the impression that the whole FLEX8000 family is > obsolete for 6 or 7 years now. FLEX6000 devices are better for just > about everything and they are near obsolete themselves. Did I miss > something ?
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