Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Avrum wrote:
>
> You are right - it can be done with 2 levels of logic and some F5MUXes
> (which will be faster than the three levels of logic I propsed above).
>
> Referring to my earlier implementation, you will still need the function
> digit_mod, and you will also need an equivalent 5 bit function, lets call it
> five_bit_mod - it will be a 5 bit input, 2 bit output case table like
> digit_mod (which just lists the mod3 of all 32 5 bit combinations). This
> SHOULD be implemented as 2*(2*LUT4+F5MUX), if the synthesis tool does its
> job. The digit_mod should be implemented as 2*LUT4
>
> wire [1:0] m0, m1;
>
> m0 = five_bit_mod(in[4:0]);
> m1 = five_bit_mod(in[9:5]);
>
> out = digit_mod({m1,m0});
>
> This will (oddly) take two more LUTs, but should be faster.
Two more LUTs than what? You originally proposed 13 LUTs, I suggested
10 and I think you are agreeing with me that it will take 10. The
outputs of the five_bit_mod are only two bits each. Are you thinking
that it will be more? Each of the five_bit_mod functions require four
LUTs and two F5MUX elements for a total of eight. To combine the two
pairs of outputs takes two more LUTs for a total of 10.
Am I missing something here with the LUT count?
BTW, your two five_bit_mod functions *can* be the same if you account
for it in the digit_mod function. Think of the combination of even bits
as counting +1 elements and the odd bits as counting -1 (-1 mod 3 = 2)
elements. In reality this is just another arbitrary truth table.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 55001Kris, Hard macro should be treated as black box like coregen comps, so you don't need to add it to library. Regards, Wei kris wrote: > I have generated a hard macro of a small module with FPGA editor. (xilinx > ISE) > But I'm having problems with declaration of the hardmacro in my toplevel > design. My toplevel design does not know the macro. > > Can I add it to a library or how do can do this? > > Thanks!Article: 55002
My original solution (which is based on only LUT4) actually requires only 8
LUTs total, if you want to hand optimize it...
m00 = digit_mod(in[3:0]); // 2 LUTS
m01 = digit_mod(in[7:4]); // 2 LUTS
m10 = digit_mod({m00,m01}); // 2 LUTs
out = digit_mod({m10,in[10:9]}); // 2 LUTs
Thus 8 LUTs in 3 levels.
The solution using the F5MUX (and your variation) requires 10 LUTs, 2
F5MUXes (which are free), and only 2 (and a bit) levels of logic.
Avrum
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3EA703A1.D5887176@yahoo.com...
> Avrum wrote:
> >
> > You are right - it can be done with 2 levels of logic and some F5MUXes
> > (which will be faster than the three levels of logic I propsed above).
> >
> > Referring to my earlier implementation, you will still need the function
> > digit_mod, and you will also need an equivalent 5 bit function, lets
call it
> > five_bit_mod - it will be a 5 bit input, 2 bit output case table like
> > digit_mod (which just lists the mod3 of all 32 5 bit combinations). This
> > SHOULD be implemented as 2*(2*LUT4+F5MUX), if the synthesis tool does
its
> > job. The digit_mod should be implemented as 2*LUT4
> >
> > wire [1:0] m0, m1;
> >
> > m0 = five_bit_mod(in[4:0]);
> > m1 = five_bit_mod(in[9:5]);
> >
> > out = digit_mod({m1,m0});
> >
> > This will (oddly) take two more LUTs, but should be faster.
>
> Two more LUTs than what? You originally proposed 13 LUTs, I suggested
> 10 and I think you are agreeing with me that it will take 10. The
> outputs of the five_bit_mod are only two bits each. Are you thinking
> that it will be more? Each of the five_bit_mod functions require four
> LUTs and two F5MUX elements for a total of eight. To combine the two
> pairs of outputs takes two more LUTs for a total of 10.
>
> Am I missing something here with the LUT count?
>
> BTW, your two five_bit_mod functions *can* be the same if you account
> for it in the digit_mod function. Think of the combination of even bits
> as counting +1 elements and the odd bits as counting -1 (-1 mod 3 = 2)
> elements. In reality this is just another arbitrary truth table.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 55003
I think you can not get a way to finished this div operation in 5ns.
As I remember Xilinx need finished it in M(+N)+3 cycles, Altera's Div IP
Cores need 50~60ns.
(M, N is bit number of the div operation object)
--
Best Regards,
Joshua Yin
2003.04.23
"RISC taker" <RISC_taker@alpenjodel.de> wrote in message
news:18c289aa.0304230854.6897fb3b@posting.google.com...
> Hey, I need to calculate (n mod 3) in a Virtex-II design. n is a
> 10-bit unsigned number and 3 is a constant. This has to be done in the
> same cycle (combinatorial!). Now what's a good way to implement that?
>
> I thought of a lookup table (distributed RAM) but this takes quite a
> lot of space. Any better ideas? (Ray, the arithmetic guru? :-)
>
> Do you think I can perform this operation at 200 MHz in a Virtex-II?
>
> Thanks!
> RISC_taker
Article: 55004>The SP3 datasheet states that 1.26 volts is acceptable. Or (making an >educated guess) you could probably run your processor 5% low - which >would get you to 1.2V. > >Or perhaps the best of both worlds: you could just split the >difference and run that rail at 1.23 Volts. Then each part would be >only ~2.5% from the spec'ed mid-point voltage, giving you some margin >on both sides. Beware. This area gets complicated. [Care to guess what I've been checking up on recently? :) ] Assume you find a nominal voltage that looks good. What's the regulation of your supply over temp, load, time, initial calibration... Got remote sense? At both chips? What's the ripple from your supply? [DVMs don't bother to remind you about this.] Subtract 1/2 that off from the bottom and add the other half to the top. Are you still within specs? Is the code on the CPU going to run in bursts? Will your FPGA be running in bursts? If so, what's the dynamic response of your supply? [You can often get a good idea by watching what happens when things come out of reset.] DC-DC "bricks" are often bad in this area. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55005
In comp.lang.vhdl vikas <vikas_akalwadi@indiatimes.com> wrote: I have been working quite a lot with viterbi, but feel somewhat inadequate to answer to your questions. I have always felt that the only things truly affecting the overall area consumption are the number of softbits and and the chosen traceback depth. Things beyond those are merely bits and pieces. Anyhow, my intention was to tell you that I have access to those ieee papers, so if you drop me a mail I can send them to you in return. I don't really know how legal it is to do so, but it can never be too illegal to share knowledge (yes I am a researcher :) )... regards, juza : 3. After survival data equal to trace back deapth has been stored, we : start trace back. If we are to start the traceback with lowest partial : path metric, how do we determine that state if we do "localised : normalisation" : 4. What are the different techniques for trace back operation ? : Since i am implementing it on hardware, functionality, area and timing : all are very important. : expecting reply, : regards, : Vikas -- JuzaArticle: 55006
> You must be talking about the TI C6711C or C6713. Check the Close: TI but only C5502 :) > tolerances. I bet you can pick one voltage that will suit both. It is > not like the voltage is *that* critical to these chips. If it is 50 mV > too high the chip won't *blow*. It will use about 8% more power by my > estimation. Yes, I could find a nominal voltage which is in ideal case acceptable for both devices, but I am affraid of problems described by Hal. Margins get very narrow here. > > The match in power voltage is one reason I would like to use the Spartan > 3. But I can't wait for 9 months. Beside, this design is not for a > single board. We plan to use other DSP chips which will not have the > low 1.26 volt power. Fortunately they *do* make LDOs that will drop the > 1.5 volt power to 1.26 volts! Think about it. That is 84% efficiency. > Not bad for an LDO. You can do a bit better by adding yet another > switcher to your design, but is it worth it? Well, the info about LDOs sounds interesting. I thought that with LDO I will be forced to use 3.3V which doesn't give that efficiency of course. I will definitely consider this option. > -- Robert PudlikArticle: 55007
hmurray@suespammers.org (Hal Murray) wrote in message news:<vaenis8839p083@corp.supernews.com>... > >The SP3 datasheet states that 1.26 volts is acceptable. Or (making an > >educated guess) you could probably run your processor 5% low - which > >would get you to 1.2V. > > > >Or perhaps the best of both worlds: you could just split the > >difference and run that rail at 1.23 Volts. Then each part would be > >only ~2.5% from the spec'ed mid-point voltage, giving you some margin > >on both sides. > > Beware. This area gets complicated. [Care to guess what I've been > checking up on recently? :) ] > > Assume you find a nominal voltage that looks good. > > What's the regulation of your supply over temp, load, time, > initial calibration... > > Got remote sense? At both chips? > > What's the ripple from your supply? [DVMs don't bother to remind you > about this.] Subtract 1/2 that off from the bottom and add the other > half to the top. Are you still within specs? > > Is the code on the CPU going to run in bursts? Will your FPGA be > running in bursts? If so, what's the dynamic response of your supply? > [You can often get a good idea by watching what happens when things > come out of reset.] DC-DC "bricks" are often bad in this area. LDO's tend to handle all these issues pretty well as long as the input side (DC/DC or AC/DC) of the regulator can keep the voltage above Vout+Vdrop while suppling the required current during these peaks. And as Rick pointed out in another post, unless you are in a battery operated environment, the heat generated by the LDO isn't all that bad if you can run it from a low voltage source like 1.8 Volts. Of course, also as Rick pointed out, a bigger problem for the OP than voltages is getting ahold of an SP3. Have fun, MarcArticle: 55008
Goran, Nios is configurable to use either a 16-bit or a 32-bit datapath. The version Jim has created has a 32-bit datapath. You seem to be confusing datapath width with instruction encoding length. Using 32-bit instructions instead of 16-bit gives you more space to encode more instructions, but costs you cache efficiency, and decode logic area. The extra op-code space also doesn't gain you much if you don't have the need for the extra instructions, or the room to build more function units that would execute the stranger opcodes (likely the case in a soft processor). Whether 32-bit vs. 16-bit instruction encoding is best is a tough question in embedded processors, and there is no general rule -- SH-RISC is 16-bit, ARM-thumb is 16, while ARM regular is 32, PowerPC is 32 and so on. I'd say it's an even more open question in soft processors, given the relatively higher cost of logic in FPGAs vs. that of embedded processors built using standard cells or even custom layout. If a longer instruction length was simply better, we'd all be using 64-bit instruction encodings, but nobody is. Which processor gets more work done in a given clock period is of course a complex function of the cache / memory subsystem, processor pipeline, and instruction set. The only way to measure what system gets more work done per unit time is to use real benchmark programs. As for clock speed, it's hard to compare unless you have exactly the same system. I know that the NIOS 32-bit core runs above 125 MHz in a Stratix, -5 speed grade (got it right in front of me). De-rating for the -6 speed grade Jim is using would let him run at 114 MHz or so that in speed grade. So the critical path Jim is seeing is outside the core somewhere. If it's in the "custom logic interfaces" Jim built, there's no real way to compare speeds without building the exact same system in another chip, and to do that you'd need Jim's design. Vaughn Betz Goran Bilski <Goran.Bilski@Xilinx.com> wrote in message news:<3EA5EACB.318D5B85@Xilinx.com>... > Hi Jim, > > I tried to create something similar using MicroBlaze and V2Pro > The design has > - MicroBlaze > - 8Kb of onchip memory > - Two External memories like flash and sram > - lcd, led and button interface > - One Uart > - Two 32-bit timers > - One Ethernet MAC > > My computer is a P3-900 Mhz with 512 MB of memory. > > The target device is a xc2vp4, package fg256, speed -6 > I put a constraint on the clock for 120 MHz. > It took the place and route tool (par) 8 min to get to that speed. > Since MicroBlaze has 32-bit instructions (NIOS has 16-bit) and can therefore do more for each > instruction, the actual performance should be higher even if the clock frequency is the same. > > Göran > > "Jim M." wrote: > > > Well, I've finished up a couple NIOS designs and here's the Fmax > > values I obtained for a couple configurations: > > > > SETUP 1 -- 90 MHz (1S10-C6ES), slack +500ps > > 32-bit NIOS CPU without instruction/data cache and with button input, > > led output, lcd output, sram, flash, ethernet, 1 uart, 1 dma, and some > > custom logic interfaces. This design had a positive slack time of > > nearly 500 ps suggesting that 95 MHz is probably possible. I tried > > 100 MHz and had a negative slack time of nearly 500 ps. > > > > SETUP 2 -- 90 MHz (1S10-C6ES), slack +50ps > > Same as #1 with addition of SDRAM controller. > > > > No LogicLock regions used in design. > > > > In addition, I still experience a repeated fast fit during compilation > > in Quartus. I'm not sure why this happens, but it occurs after any > > change to the design. The first compile after a change results in a > > database build, logic synthesis (using previous fitter results from > > database), then a repeated fast-fit. I let one of these fast-fit > > sessions run itself out and it took about 11 hours. It built up > > 100-200 entries in the database. I received some pretty nice results > > due to the 11 hour build. > > > > Now when I see the repeated fast-fit occurring, I stop the build after > > the first fit then re-build. The rebuild skips the database builder > > and logic synthesizer (since smart compile is enabled) and performs a > > final fit (not fast-fit). > > > > I thought I'd post my final results. > > > > jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304141222.15bf1ca8@posting.google.com>... > > > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > > > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > > > Core. (For those poor souls interested, I've included some comments > > > at the end of this post... feel free to provide feedback.) > > > > > > However, here's my question: > > > > > > What's the maximum clock frequency anyone has achieved using the NIOS > > > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > > > Ethernet, PIO, UART, etc. as in the Reference Design provided by > > > Altera)? > > > > > > I've tried isolating the various components into LogicLock regions. > > > I've tried different fitter/netlist optimizations. The maximum Fmax I > > > have achieved to date is 80 MHz. This is after letting Quartus "fit" > > > for 10 hours... it actually didn't stop, I had to abort the fitting > > > and refit to finially get an interim result (see other misc comments > > > below). > > > > > > Altera advertises 125 MHz for the Stratix Device and NIOS 3.0... > > > However a reference design that builds at that clock rate is not > > > provided. It appears that Altera gives you just enough to get your > > > feet wet... anything above and beyond that is Intellectual Property > > > that you need to buy. > > > > > > Other Observations/Comments: > > > > > > 1. The Quartus II SP1 software is extremely flakey. I've generated > > > numerous faults when deleting/modifying child LogicLock Regions. It > > > also takes forever to fit my Stratix design which is only 6000 LEs. > > > If I select the "limit fitting attempts to 1" option, Quartus > > > sometimes fits many times (like forever...) why?!?!? Also, after a > > > design is finished building, the software sits around for up to 5 > > > minutes before it generates a "finished" dialog box. I'm not sure > > > what's going on between the Quartus Application thread and the Quartus > > > Compiler thread, but it's fustrating enough just waiting for the > > > design to build, let alone waiting for Quartus to figure out the build > > > is done. I could go on and on, and that's only the result of 4 weeks > > > of effort with a small design. I feel sorry for those folks working > > > on a 100,000+ gate design. I guess modularity is the key there. > > > > > > 2. I can't simulate designs with virtual pins. I get warning during > > > the analysis of the simulation and then receive results with all input > > > pins a zero and output pins undefined. In addition, I can generate > > > hold time warnings during simulation for a design that didn't compile > > > with any hold time warnings. I'm not talking about hold time warnings > > > on my input signals, I'm talking about hold time warnings on internal > > > registers in my verilog code. Registers that I've taken care to hold > > > for 1 or more clock cycles before using in other parts of the design. > > > Again, the compilation of the design did not generate hold time > > > warnings... only the simulation of the design. > > > > > > 3. PLLs generate different timing analysis results. THIS IS VERY > > > ANNOYING! When I build up a "black-bock" design with virtual pins I > > > obtain a Fmax calculation from the timing analysis routine. I then > > > LogicLock the design and export it. When I import the design into a > > > new project and clock it using a PLL it generates negative slack time > > > warnings! If I remove the PLL and replace it with a clock pin, I get > > > the Fmax result that I obtained during the "black box" design. I beat > > > myself up for a week trying to debug a design that wasn't broken > > > because of this goofy behavior in Quartus. I'm still not sure if the > > > slack time warning it legit and wether I should be concerned about it. > > > > > > 4. SOPC Builder will lock itself up if you double-click components > > > before selecting them. Give it a try... double click a component line > > > in your NIOS design before selecting the line item. After a couple > > > times the SOPC builder application creeps to a halt. > > > > > > 5. Documentation on the various megafunctions is lacking. A good > > > example is the altsyncram megafunction. It doesn't state any timing > > > requirements on the input registers, enable, and clock signals. Do I > > > hold the data 1 cycle before flipping the write enable? How about > > > holding the write enable before de-activating it? Why is the > > > addressing based upon the data bit-width? Trying to tie a 32-bit > > > altsyncram block to a NIOS CPU is difficult because you need to > > > specify the address space of the peripheral and the address space of > > > the altsyncram block is based upon the bit width (not the number of > > > bytes). > > > > > > 6. I have yet to get a Leonaro-Spectrum synthesized Verilog file to > > > build in Quartus. I can used Spectrum generated .edf files but not > > > verilog. I get LCELL parameter errors. Unfortunately, Altera can't > > > seem to duplicate this... anyone else see this behavior? I'm not sure > > > if Spectrum synthesizes Verilog better that Quartus, but it definitely > > > does it faster. > > > > > > Feedback is welcome... even if it's the "you're an idiot and here's > > > why" variety...Article: 55009
Jim, Can you send me a quartus archive of the problem compile that you say is hitting repeated fast fitting? If you do I can take a look at it and see what's going on. I'm not quite sure what repeated fast fitting means, but you definitely shouldn't see long compiles for a Nios design like this. What fitting / netist optimization settings do you have selected? If you have the "Use fitter timing info" option selected, you will see the device fitted twice -- once to get timing estimates for re-synthesis, and once to create the final fit. That drives compile time up by ~2x, but that still shouldn't lead to the kind of compile times you're seeing though. Vaughn Betz jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304220920.7c68ff2b@posting.google.com>... > Well, I've finished up a couple NIOS designs and here's the Fmax > values I obtained for a couple configurations: > > SETUP 1 -- 90 MHz (1S10-C6ES), slack +500ps > 32-bit NIOS CPU without instruction/data cache and with button input, > led output, lcd output, sram, flash, ethernet, 1 uart, 1 dma, and some > custom logic interfaces. This design had a positive slack time of > nearly 500 ps suggesting that 95 MHz is probably possible. I tried > 100 MHz and had a negative slack time of nearly 500 ps. > > SETUP 2 -- 90 MHz (1S10-C6ES), slack +50ps > Same as #1 with addition of SDRAM controller. > > No LogicLock regions used in design. > > In addition, I still experience a repeated fast fit during compilation > in Quartus. I'm not sure why this happens, but it occurs after any > change to the design. The first compile after a change results in a > database build, logic synthesis (using previous fitter results from > database), then a repeated fast-fit. I let one of these fast-fit > sessions run itself out and it took about 11 hours. It built up > 100-200 entries in the database. I received some pretty nice results > due to the 11 hour build. > > Now when I see the repeated fast-fit occurring, I stop the build after > the first fit then re-build. The rebuild skips the database builder > and logic synthesizer (since smart compile is enabled) and performs a > final fit (not fast-fit). > > I thought I'd post my final results. > > jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304141222.15bf1ca8@posting.google.com>... > > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > > Core. (For those poor souls interested, I've included some comments > > at the end of this post... feel free to provide feedback.) > > > > However, here's my question: > > > > What's the maximum clock frequency anyone has achieved using the NIOS > > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > > Ethernet, PIO, UART, etc. as in the Reference Design provided by > > Altera)? > > > > I've tried isolating the various components into LogicLock regions. > > I've tried different fitter/netlist optimizations. The maximum Fmax I > > have achieved to date is 80 MHz. This is after letting Quartus "fit" > > for 10 hours... it actually didn't stop, I had to abort the fitting > > and refit to finially get an interim result (see other misc comments > > below). > > > > Altera advertises 125 MHz for the Stratix Device and NIOS 3.0... > > However a reference design that builds at that clock rate is not > > provided. It appears that Altera gives you just enough to get your > > feet wet... anything above and beyond that is Intellectual Property > > that you need to buy. > > > > Other Observations/Comments: > > > > 1. The Quartus II SP1 software is extremely flakey. I've generated > > numerous faults when deleting/modifying child LogicLock Regions. It > > also takes forever to fit my Stratix design which is only 6000 LEs. > > If I select the "limit fitting attempts to 1" option, Quartus > > sometimes fits many times (like forever...) why?!?!? Also, after a > > design is finished building, the software sits around for up to 5 > > minutes before it generates a "finished" dialog box. I'm not sure > > what's going on between the Quartus Application thread and the Quartus > > Compiler thread, but it's fustrating enough just waiting for the > > design to build, let alone waiting for Quartus to figure out the build > > is done. I could go on and on, and that's only the result of 4 weeks > > of effort with a small design. I feel sorry for those folks working > > on a 100,000+ gate design. I guess modularity is the key there. > > > > 2. I can't simulate designs with virtual pins. I get warning during > > the analysis of the simulation and then receive results with all input > > pins a zero and output pins undefined. In addition, I can generate > > hold time warnings during simulation for a design that didn't compile > > with any hold time warnings. I'm not talking about hold time warnings > > on my input signals, I'm talking about hold time warnings on internal > > registers in my verilog code. Registers that I've taken care to hold > > for 1 or more clock cycles before using in other parts of the design. > > Again, the compilation of the design did not generate hold time > > warnings... only the simulation of the design. > > > > 3. PLLs generate different timing analysis results. THIS IS VERY > > ANNOYING! When I build up a "black-bock" design with virtual pins I > > obtain a Fmax calculation from the timing analysis routine. I then > > LogicLock the design and export it. When I import the design into a > > new project and clock it using a PLL it generates negative slack time > > warnings! If I remove the PLL and replace it with a clock pin, I get > > the Fmax result that I obtained during the "black box" design. I beat > > myself up for a week trying to debug a design that wasn't broken > > because of this goofy behavior in Quartus. I'm still not sure if the > > slack time warning it legit and wether I should be concerned about it. > > > > 4. SOPC Builder will lock itself up if you double-click components > > before selecting them. Give it a try... double click a component line > > in your NIOS design before selecting the line item. After a couple > > times the SOPC builder application creeps to a halt. > > > > 5. Documentation on the various megafunctions is lacking. A good > > example is the altsyncram megafunction. It doesn't state any timing > > requirements on the input registers, enable, and clock signals. Do I > > hold the data 1 cycle before flipping the write enable? How about > > holding the write enable before de-activating it? Why is the > > addressing based upon the data bit-width? Trying to tie a 32-bit > > altsyncram block to a NIOS CPU is difficult because you need to > > specify the address space of the peripheral and the address space of > > the altsyncram block is based upon the bit width (not the number of > > bytes). > > > > 6. I have yet to get a Leonaro-Spectrum synthesized Verilog file to > > build in Quartus. I can used Spectrum generated .edf files but not > > verilog. I get LCELL parameter errors. Unfortunately, Altera can't > > seem to duplicate this... anyone else see this behavior? I'm not sure > > if Spectrum synthesizes Verilog better that Quartus, but it definitely > > does it faster. > > > > Feedback is welcome... even if it's the "you're an idiot and here's > > why" variety...Article: 55010
Hi, Has anyone knowledge of existing library devices of Xilinx Virtex-E FPGAs and Xilinx PROMs for the Eagle PCB layout program? More specifically I am looking for symbols for the XCV300E (FPGA) and XC18V02 (PROM). The Xilinx libraries on www.cadsoft.com don't seem to contain those devices. Thanks in advance. Stefan TillichArticle: 55011
Stefan Tillich <stefanti@sbox.tugraz.at> wrote: : Hi, : Has anyone knowledge of existing library devices of Xilinx Virtex-E : FPGAs and Xilinx PROMs for the Eagle PCB layout program? : More specifically I am looking for symbols for the XCV300E (FPGA) and : XC18V02 (PROM). The Xilinx libraries on www.cadsoft.com don't seem to : contain those devices. Nearly every package for the XCV300E will result in a seperate device in eagle. As there are different numbers of supply and I/O pins, the eagle package concept doesn't allow you to interchange the packages. Also there are different ways to draw the symbol for such a device. You can have a block for the whole device, for every output bank or so. All ways have their pros and cons. I prefer to have a symbol for every I/O pin. That way I can swap the IO pins. I can send you my xilinx.lbr and a sample drawing on request. I probably boils down that you will have to define the device yourself, according to your needs. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55012
The Programmer's Reference Manual only references underflow (irq 1) and overflow (irq 2), but not irq's 3-15. Any way to track those down. The IRQ1 makes sense since I was using the PLUGS library, and had my NIOS core set up for 15 levels of subroutines with CWM disabled. I still left CWM disabled, but bumped the subroutine levels up to 31 (512 window size vs. 256 window size). Thanks for excellent information and prompt feedback. kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0304230905.22e125a0@posting.google.com>... > IRQs 1-15 are 'reserved' for system-level exceptions - check out the > Nios Programmer's Reference Manual (PDF) file. IRQ 1 is for register > window underflow... something that would happen if you return (ret > instruction) from a subroutine call, but without entering (call > instruction) the subroutine. > > Are you doing anything fancy during the boot-up process with your own > startup code? If you're doing something such as compiling a > traditional C program (with main(), and a bunch of subroutines), built > with nios-build, then we will link in code that sets up interrupts, > the register window, etc. and prevents this sort of thing. > > - Jesse > > > > > jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304230440.35a703d9@posting.google.com>... > > The error message prints in hex huh? Well that's probably worth > > knowing. > > > > That explains IRQ 17 and 19 (timer and lan respectively) > > > > Is it possible to receive a spurious interrupt for an IRQ not assigned > > in SOPC Builder. I recall having a spurious IRQ #1, although I may > > have been mistaken. > > > > You mention that IRQs 16-64 are for user exceptions. What about IRQs > > 1-15 ? > > > >Article: 55013
I need help putting together the following scenerio: An analog input(sine wave) will be brought in through an ADC to memory. Then the FPGA will pull the data from the memory and perform the FFT. The FFT output will be put back into memory and finally outputted to a x-y plot. I already have the FFT part working in vhdl. I really need help in setting up the input part, both with hardware and software (vhdl). I was told that Xilinx has a core generator that I would be able to use to build a memory module, but I do not have any experience in using the core generator. Is there anyone out there willing to shed some light on my dilema?Article: 55014
Hello all. Does anyone know a good online source that can teach me how to manually convert Verilog to VHDL. I don't know much verilog but do know VHDL. Any help would be greatly appreciated. thanks.Article: 55015
Hi All; Has anyone had luck getting ise4.2 to work under wine using a stock RH7.3 system? I've gone throught the steps outlined in the xilinx faqs but no luck. PatArticle: 55016
Robert wrote: > > > You must be talking about the TI C6711C or C6713. Check the > > Close: TI but only C5502 :) > > > tolerances. I bet you can pick one voltage that will suit both. It is > > not like the voltage is *that* critical to these chips. If it is 50 mV > > too high the chip won't *blow*. It will use about 8% more power by my > > estimation. > > Yes, I could find a nominal voltage which is in ideal case acceptable > for both devices, but I am affraid of problems described by Hal. Margins > get very narrow here. My point is that I am certain that you can run both units from a voltage that is the higher of the two. There is only 60 mV of difference. Do you really think running the 1.2 volt chip at 1.2 + 60 mV will do any damage. I con't care what the data sheet says about 1.2x volts being the absolute maximum. Chips are just not that sensitive to Vdd being a touch high. The low end is where you need to worry. Run a little low and you can affect timing performance. > > The match in power voltage is one reason I would like to use the Spartan > > 3. But I can't wait for 9 months. Beside, this design is not for a > > single board. We plan to use other DSP chips which will not have the > > low 1.26 volt power. Fortunately they *do* make LDOs that will drop the > > 1.5 volt power to 1.26 volts! Think about it. That is 84% efficiency. > > Not bad for an LDO. You can do a bit better by adding yet another > > switcher to your design, but is it worth it? > > Well, the info about LDOs sounds interesting. I thought that with LDO I > will be forced to use 3.3V which doesn't give that efficiency of course. > I will definitely consider this option. I don't have a part number handy, but the parts I am thinking about are from Maxim (as least they are being advertised) and use one input for the power source and a second input to bias the amps and such. The bias supply has to be closer to 3 or 5 volts. But the power supply can go down to 1.5 volts IIRC. I made a mistake with this though. I was thinking about a design I was looking at where the FPGA would be powered from 1.5 volts and the DSP from the LDO. Your FPGA runs on 1.2 volts. On the other hand, have you looked at the Cyclone parts? They run on 1.5 volts and are available *now*. Or the Spartan IIE runs on 1.8 volts, not a lot worse efficiency in the LDO. Which DSP are you using? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55017
"John" <jt3214@juno.com> schrieb im Newsbeitrag news:b4503d93.0304240658.45245e0d@posting.google.com... > I need help putting together the following scenerio: > > An analog input(sine wave) will be brought in through an ADC to > memory. Then the FPGA will pull the data from the memory and perform > the FFT. The FFT output will be put back into memory and finally > outputted to a x-y plot. I already have the FFT part working in vhdl. > I really need help in setting up the input part, both with hardware > and software (vhdl). I was told that Xilinx has a core generator that Its a little bit hard to believe that someone who managed to design a FFT in a FPGA doest know how to transfer data to/from a memory. Anyway. 1st, what memory do you want to use? FPGA internal or external? Which device are you using? Speed requirements? Using core generator to build a memory from the FPGA internal blocks is easy. Just a few clicks. Self explainary. -- MfG FalkArticle: 55018
Altera anounces the combination of Cyclone and Nios as a Low-Cost SOPC
Solution. But for me SOPC means CPU, logic and memory in one chip.
CPU is (as you know in this group) no problem, but current FPGAs still lack
in the memory area. Internal RAM is too small for larger programs and there
is no Flash in the FPGA.
The new board compensates this with an external three stage memory hirarchy:
fast asynchron memory as main memory
(conventional) Flash for coniguration data and application
(big) NAND Flash for solide state disc
The board is a module compatible to Jopcore. An expansion board with
Ethernet connection (Basio) is also available for both boards.
The Facts:
Altera Cyclone EP1C6Q240C6 FPGA
step down voltage regulator (1V5)
crystal clock (20 MHz)
512KB Flash (for FPGA configuration and program)
up to 1MB fast async Ram
up to 128MB NAND Flash
ByteBlaster port
Watchdog with led
EPM7064 PLD to configure Cyclone from flash (on watchdog reset)
serial interface (MAX3232)
56 general IO pins
The RAM consists of two independent 16 Bit banks (with own address and
control lines). Both RAM chips are on the back side of the PCB direct under
the FPGA pins. The traces are very short (below 10 mm) so it is ossible to
use the RAMs at full speed without reflection problems. The two banks can be
combined to form 32 Bit RAM or support two independent CPU cores (A dual
processor system in a FPGA :-).
When Altera ships the EP1C12 the same board will also be availabe with it.
Further information: http://www.jopdesign.com/cyclone/index.jsp
Kind regards
Martin Schoeberl
martin.schoeberl@chello.at
Article: 55019Pat Ford wrote: > Hi All; > Has anyone had luck getting ise4.2 to work under wine using a stock RH7.3 > system? I've gone throught the steps outlined in the xilinx faqs but no > luck. > Pat This question has been asked a lot. Someone should put together a ready- to-run WINE configuration (including config files and pre-installed disk image) that works. At least for WebPACK. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 55020
Yes this is very well done! Thank You Laurent! Rick Schwarz http://www.associatedpro.com FPGA Engineering Tools "Laurent Gauch, Amontec" <laurent.gauch@amontec.com> wrote in message news:<3ea42b1f$1@news2.vsnet.ch>... > The fast way explaining all VHDL keywords ... > > http://www.amontec.com/fix/vhdl_memo/index.htmlArticle: 55021
I need to make a bus between an FPGA (Cyclone) and a microcontroller. The bus will operate as fast as 48 MHz. It will need to be bidirectional. What I am worried about is accidentally having both sides driving the bus at the same time (during prototyping). I think I can insure that my designs don't do that, but this is a development board, and I don't know what code other people might put on it. Should I make the bus open drain? Or put resistors in the lines to prevent burnouts? Or just be very careful... Thanks MattArticle: 55022
Is it possible to declare variables at a specific memory location in
C-Code when using the GNUPro toolchain for NIOS?
For example: to declare an array at memory 0x01000000, a cosmic
compiler I once used had the following syntax:
char cArray[ARRAY_SIZE] @ 0x01000000;
I found the __attribute__ keyword in the GNUPro Compiler Manual,
something along the lines of:
char cArray[ARRAY_SIZE] __attribute__ ((section("SECTION_NAME"))) =
{0};
Where SECTION_NAME is assigned to location 0x01000000, but that would
force me to create a linker script and a makefile in order to define
SECTION_NAME. Right now it's very nice just to use the nios_build
utility.
I know I can create a pointer and assign the pointer to a memory
location, but that forces me to manually manage the partitioning of
memory.
Any ideas?
Jim
Article: 55023Pat Ford wrote: > Hi All; > Has anyone had luck getting ise4.2 to work under wine using a stock RH7.3 > system? I've gone throught the steps outlined in the xilinx faqs but no > luck. > Pat Give a little more info about where you are having problems. I ran ISE4.2 under Wine/RH7.3 for quite awhile, though I have since updated to ISE 5.1. In general, I would recommend that you use a current CVS version of Wine rather than the Wine that came with RH7.3. Be sure to uninstall the RH Wine before installing the CVS version. In particular, this will fix some ISE GUI bugs. -- My real email is akamail.com@dclark (or something like that).Article: 55024
The critical path in my design is reg-to-reg in the external bus interface for accessing SRAM, LAN91C111, and Flash. The next most critical path is reg-to-reg in the SDRAM controller. The critical path for the external bus interface is worsened from SETUP 1 to SETUP 2 by the addition of the SDRAM interface. It's interesting how the fitter compensates between the different modules. I suspect the 114 MHz design you mention below does not have any peripherals, just a CPU core without peripherals. Sort of like an SOPC Build with just 1 line item... the CPU. Is that true? If so, did you use virtual pins to build a design with just a CPU? The only custom logic I have in the CPU clock domain is a couple Avalon Bus Masters. BUT... I agree with your statements below on comparing designs. vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0304240518.5e0be5cd@posting.google.com>... > Goran, > > Nios is configurable to use either a 16-bit or a 32-bit datapath. The > version Jim has created has a 32-bit datapath. > > You seem to be confusing datapath width with instruction encoding > length. Using 32-bit instructions instead of 16-bit gives you more > space to encode more instructions, but costs you cache efficiency, and > decode logic area. The extra op-code space also doesn't gain you much > if you don't have the need for the extra instructions, or the room to > build more function units that would execute the stranger opcodes > (likely the case in a soft processor). Whether 32-bit vs. 16-bit > instruction encoding is best is a tough question in embedded > processors, and there is no general rule -- SH-RISC is 16-bit, > ARM-thumb is 16, while ARM regular is 32, PowerPC is 32 and so on. > I'd say it's an even more open question in soft processors, given the > relatively higher cost of logic in FPGAs vs. that of embedded > processors built using standard cells or even custom layout. > > If a longer instruction length was simply better, we'd all be using > 64-bit instruction encodings, but nobody is. > > Which processor gets more work done in a given clock period is of > course a complex function of the cache / memory subsystem, processor > pipeline, and instruction set. The only way to measure what system > gets more work done per unit time is to use real benchmark programs. > > As for clock speed, it's hard to compare unless you have exactly the > same system. I know that the NIOS 32-bit core runs above 125 MHz in a > Stratix, -5 speed grade (got it right in front of me). De-rating for > the -6 speed grade Jim is using would let him run at 114 MHz or so > that in speed grade. So the critical path Jim is seeing is outside > the core somewhere. If it's in the "custom logic interfaces" Jim > built, there's no real way to compare speeds without building the > exact same system in another chip, and to do that you'd need Jim's > design. > > Vaughn Betz > > > Goran Bilski <Goran.Bilski@Xilinx.com> wrote in message news:<3EA5EACB.318D5B85@Xilinx.com>... > > Hi Jim, > > > > I tried to create something similar using MicroBlaze and V2Pro > > The design has > > - MicroBlaze > > - 8Kb of onchip memory > > - Two External memories like flash and sram > > - lcd, led and button interface > > - One Uart > > - Two 32-bit timers > > - One Ethernet MAC > > > > My computer is a P3-900 Mhz with 512 MB of memory. > > > > The target device is a xc2vp4, package fg256, speed -6 > > I put a constraint on the clock for 120 MHz. > > It took the place and route tool (par) 8 min to get to that speed. > > Since MicroBlaze has 32-bit instructions (NIOS has 16-bit) and can therefore do more for each > > instruction, the actual performance should be higher even if the clock frequency is the same. > > > > Göran > > > > "Jim M." wrote: > > > > > Well, I've finished up a couple NIOS designs and here's the Fmax > > > values I obtained for a couple configurations: > > > > > > SETUP 1 -- 90 MHz (1S10-C6ES), slack +500ps > > > 32-bit NIOS CPU without instruction/data cache and with button input, > > > led output, lcd output, sram, flash, ethernet, 1 uart, 1 dma, and some > > > custom logic interfaces. This design had a positive slack time of > > > nearly 500 ps suggesting that 95 MHz is probably possible. I tried > > > 100 MHz and had a negative slack time of nearly 500 ps. > > > > > > SETUP 2 -- 90 MHz (1S10-C6ES), slack +50ps > > > Same as #1 with addition of SDRAM controller. > > > > > > No LogicLock regions used in design. > > > > > > In addition, I still experience a repeated fast fit during compilation > > > in Quartus. I'm not sure why this happens, but it occurs after any > > > change to the design. The first compile after a change results in a > > > database build, logic synthesis (using previous fitter results from > > > database), then a repeated fast-fit. I let one of these fast-fit > > > sessions run itself out and it took about 11 hours. It built up > > > 100-200 entries in the database. I received some pretty nice results > > > due to the 11 hour build. > > > > > > Now when I see the repeated fast-fit occurring, I stop the build after > > > the first fit then re-build. The rebuild skips the database builder > > > and logic synthesizer (since smart compile is enabled) and performs a > > > final fit (not fast-fit). > > > > > > I thought I'd post my final results. > > > > > > jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304141222.15bf1ca8@posting.google.com>... > > > > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > > > > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > > > > Core. (For those poor souls interested, I've included some comments > > > > at the end of this post... feel free to provide feedback.) > > > > > > > > However, here's my question: > > > > > > > > What's the maximum clock frequency anyone has achieved using the NIOS > > > > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > > > > Ethernet, PIO, UART, etc. as in the Reference Design provided by > > > > Altera)? > > > > > > > > I've tried isolating the various components into LogicLock regions. > > > > I've tried different fitter/netlist optimizations. The maximum Fmax I > > > > have achieved to date is 80 MHz. This is after letting Quartus "fit" > > > > for 10 hours... it actually didn't stop, I had to abort the fitting > > > > and refit to finially get an interim result (see other misc comments > > > > below). > > > > > > > > Altera advertises 125 MHz for the Stratix Device and NIOS 3.0... > > > > However a reference design that builds at that clock rate is not > > > > provided. It appears that Altera gives you just enough to get your > > > > feet wet... anything above and beyond that is Intellectual Property > > > > that you need to buy. > > > > > > > > Other Observations/Comments: > > > > > > > > 1. The Quartus II SP1 software is extremely flakey. I've generated > > > > numerous faults when deleting/modifying child LogicLock Regions. It > > > > also takes forever to fit my Stratix design which is only 6000 LEs. > > > > If I select the "limit fitting attempts to 1" option, Quartus > > > > sometimes fits many times (like forever...) why?!?!? Also, after a > > > > design is finished building, the software sits around for up to 5 > > > > minutes before it generates a "finished" dialog box. I'm not sure > > > > what's going on between the Quartus Application thread and the Quartus > > > > Compiler thread, but it's fustrating enough just waiting for the > > > > design to build, let alone waiting for Quartus to figure out the build > > > > is done. I could go on and on, and that's only the result of 4 weeks > > > > of effort with a small design. I feel sorry for those folks working > > > > on a 100,000+ gate design. I guess modularity is the key there. > > > > > > > > 2. I can't simulate designs with virtual pins. I get warning during > > > > the analysis of the simulation and then receive results with all input > > > > pins a zero and output pins undefined. In addition, I can generate > > > > hold time warnings during simulation for a design that didn't compile > > > > with any hold time warnings. I'm not talking about hold time warnings > > > > on my input signals, I'm talking about hold time warnings on internal > > > > registers in my verilog code. Registers that I've taken care to hold > > > > for 1 or more clock cycles before using in other parts of the design. > > > > Again, the compilation of the design did not generate hold time > > > > warnings... only the simulation of the design. > > > > > > > > 3. PLLs generate different timing analysis results. THIS IS VERY > > > > ANNOYING! When I build up a "black-bock" design with virtual pins I > > > > obtain a Fmax calculation from the timing analysis routine. I then > > > > LogicLock the design and export it. When I import the design into a > > > > new project and clock it using a PLL it generates negative slack time > > > > warnings! If I remove the PLL and replace it with a clock pin, I get > > > > the Fmax result that I obtained during the "black box" design. I beat > > > > myself up for a week trying to debug a design that wasn't broken > > > > because of this goofy behavior in Quartus. I'm still not sure if the > > > > slack time warning it legit and wether I should be concerned about it. > > > > > > > > 4. SOPC Builder will lock itself up if you double-click components > > > > before selecting them. Give it a try... double click a component line > > > > in your NIOS design before selecting the line item. After a couple > > > > times the SOPC builder application creeps to a halt. > > > > > > > > 5. Documentation on the various megafunctions is lacking. A good > > > > example is the altsyncram megafunction. It doesn't state any timing > > > > requirements on the input registers, enable, and clock signals. Do I > > > > hold the data 1 cycle before flipping the write enable? How about > > > > holding the write enable before de-activating it? Why is the > > > > addressing based upon the data bit-width? Trying to tie a 32-bit > > > > altsyncram block to a NIOS CPU is difficult because you need to > > > > specify the address space of the peripheral and the address space of > > > > the altsyncram block is based upon the bit width (not the number of > > > > bytes). > > > > > > > > 6. I have yet to get a Leonaro-Spectrum synthesized Verilog file to > > > > build in Quartus. I can used Spectrum generated .edf files but not > > > > verilog. I get LCELL parameter errors. Unfortunately, Altera can't > > > > seem to duplicate this... anyone else see this behavior? I'm not sure > > > > if Spectrum synthesizes Verilog better that Quartus, but it definitely > > > > does it faster. > > > > > > > > Feedback is welcome... even if it's the "you're an idiot and here's > > > > why" variety...
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z