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rickman <spamgoeshere4@yahoo.com> wrote in message news:<3EA1F215.5A554440@yahoo.com>...
> eric - Mtl wrote:
> >
> > Bill Hanna wrote:
> > > I have been designing a Digital Signal Processor using the XC2V4000
> > > chip.
> > > Software errors in ISE 4.2 and 5.1 have caused long hours of delay in
> > > developing the design:
> > >
> > > Software bugs in SystemAce causes erase problems in the MPM.
> > > Deleting signal wires in ECS causes Fatal errors that crash the
> > > system.
> > > A large design exceeds the 2GB memory limit and generates a fatal
> > > memory error.
> > >
> > > I have designed Altera chips for over 6 years and never had a
> > > problem.
> > >
> > > All digital designers should stop designing new projects with
> > > Xilinx ICs until Xilinx corrects all software problems with ISE.
> > >
> > > Bill Hanna
> >
> > Hi,
> >
> > I'm not going to boycott Xilinx, since the good with them
> > really outweighs the bad, but as an ECS (Schematic capture)
> > user, I must admit that this tool often drives me crazy ...
> >
> > Xilinx's great silicon chips really deserve better tools !
> >
> > I know the usual debate about schematic vs HDL, but if I'm to
> > ever switch to HDL I'd like it to be for what they have to
> > offer, not because the Schematic capture software is so badly
> > designed and buggy that I can't take it anymore.
> >
> > Even when using HDL for blocks, I really think that schematic
> > diagram is great for the top level of a design, because of it's
> > inherently parallel representation, opposed to the visually
> > sequential nature of text based HDL representations, but that's
> > not the point here ...
>
> I was a die hard schematic user too. I felt that I had better control
> over my design with schematic. But then I worked with VHDL for awhile
> and I realized the power. It can be a bit of a PITA to really optimize
> the hardware, but using schematic does not really assure you of getting
> what you put on the page. The tools optimize things sometimes since
> they know more than you do :)
>
> But the transition was really confirmed for me when I started writing
> test benches to verify my design. I can generate a model of a bus or an
> ADC or any other logic external to my design that I need to test it.
> With the waveform editor I had to *plan* my simulation very
> laboriously. If anything changed, I would often have to redo large
> parts. With an HDL test bench the test bench interacts with your design
> the same way the real board does.
>
>
> > If I had to rank quality and code stability for ECS, it would
> > be very close to the bottom.
>
> ...snip...
>
> > I don't know how many Xilinx users actually use ECS and if peoples from
> > the ECS development team ever read those NG posts, but I'm pretty sure
> > other users too experience these inconveniences on a daily basis and would
> > appreciate to see them addressed as much as I do.
>
> I am sure your many bug reports are valid and hopefully someone will
> address them. I did not read the details. Did you report many of
> these? If they are not reported, they can't be fixed. I know this
> takes time, but at this point if you are vested in the tool, it will be
> up to you to report the bugs.
>
> I don't know how many ECS users there still are, but I can tell they
> must be real die hards. I realized that HDL was the way to go when Ray
> Andraka switched. He designs hierarchical, blocked out, highly
> floorplanned designs. In the past he had built up a large library of
> schematic elements that allowed him to build large DSP designs very
> quickly complete with schematic specified floorplanning. I know from
> experience that this took a lot of effort to implement. But once he was
> forced by a contract to work with an HDL, he realized the labor savings
> from working with code and once he started converting his symbol library
> to a code library, I don't think he ever looked back. Perhaps I should
> not put words in his mouth, but this is what I have gotten from reading
> his posts.
>
>
> > Also, since most new users start with schematics, pissing them off from
> > day one with such a buggy software is probably not a wise thing to do.
>
> That may have been true in times past, but I think newbies now start
> with an HDL. When I went to school, Fortran was still the only required
> language in EE. Now I don't think you can earn a BSEE without knowing
> some HDL. I have met HDL designers who work in HDL without even drawing
> a block diagram of what they want. This is very alien to me but it
> seems to be the norm now. I think the time of schematic has passed.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
I reported all errors to Xilinx. There are a large number of cases
reported.
I used schematics instead of VHDL because VHDL is inefficent
compared to schematics.
I benchmarked 3 different designs: 10 stage PN code generator, 27
stage PN code generator and a 32X32 multiplexer.
The VHDL designs required 40% more gates than the schematic
designs. The schematic design is converted to VHDL primitives by XST.
I have a 12 channel signal processor design that uses 17,000
slices. If implement in VHDL it would take 24,000 slices. The added
cost of the higher density device (XC2V6000) would increase the RE
cost by $3.5K per system.
Thanks for your advice and for taking the time to respond.
Bill Hanna
Article: 54851
Hi all,
OK, call me stupid - I must have missed something in the WebPACK docs.
I searched for a long time for signed multipliers in Verilog, and these
can be spec'ed in Verilog 2001 by adding the 'signed' keyword or '$signed()'
operation. I started playing around with IDaSS generated WebPACK code and
tried to compile the following with WebPACK 5.2:
module MULT (a,b,y);
input signed [7 :0] a ; // Normal IDaSS input
input [7 :0] b ; // Normal IDaSS input
output signed [15 :0] y ; // Normal IDaSS output
reg [15 :0] y ; // Procedural output drive channel
always @ (a or b)
begin
// Original IDaSS source code:
//
// | y := a * b
// Only a single function here...
y =
a *
b;
end
endmodule // MULT
The 'signed' is not recognised as a keyword in the editor, so my hopes were
not that high. But it synthesized without a hitch. When I opened the 'view RTL
schematic' process and clicked deeper into the hierarchy, I found to my *absolute
astonishment* that WebPACK had generated a 9 by 8 bits *SIGNED* multiplier (or at
least claimed to have done so), with bit 8 of the 9 bits wide input tied to 1'b0
make that input 'unsigned'.
Strange thing is that $signed() is not allowed, and also that it is not possible
to use the 'signed' on inputs and outputs of a Verilog task (there, they are
ignored and I got an unsigned multiplier).
It's a bit late out here, so I'll download the result in an FPGA tomorrow and play
with dipswitches and leds until I'm certain this is not a late April Foolsday joke ;-)
Has anyone seen this before, or did I work with WebPACK all these years with my
eyes closed? Note that I'm sythesizing for a Spartan-II (which does not have
hardware 18x18 bits signed multiply blocks).
Greetings from Holland,
Ad Verschueren
http://www.xs4all.nl/~averschu/idass
Article: 54852Hi - On Sun, 20 Apr 2003 14:20:21 -0400, eric - Mtl <notervme@sympatico.ca> wrote: <stuff snipped> >Forcing the switch to HDL by making the schematic tool barely usable >is a bit like poisoning water supply to increase bottled water sales. Some days it may seem like Xilinx is trying to move people to HDL by sabotaging their own schematic capture tool, but I find it hard to believe that's actually the case. The reality is a bit more banal: companies spend dollars where the customers are, or where they think the customers will be. And when customers started voting for HDL with their dollars, Xilinx's development dollars followed. I'll give you a for-instance that has nothing to do with HDL-vs-schematics: many years ago I worked for a company that used Sun-based Cadence Concept for its board-level schematic capture tool. Concept was actually quite a good program, but I made the mistake of thinking that if we used it for board-level stuff, it would also make sense to use it for FPGA design. I mean, why in the world would you ask all your designers to learn both Concept and, say, Viewdraw, when they could use Concept for everything? It turns out that there was a very good reason: the Concept-to-Xilinx netlist path didn't work worth a damn. It was bug-ridden and about half a year behind the Viewlogic package in supporting new parts. And the path from Xilinx schematics to Verilog simulation netlists was equally broken. All in all, it was a disaster. The reason for the problem became obvious sometime later, after I'd ordered a copy of Viewdraw and the accompanying netlister for use on a set of FPGA designs. The CAE manager forwarded me an invoice for maintenance on both the Cadence-to-Xilinx and Viewdraw-to-Xilinx interfaces, and here's what I saw: the serial number for the Viewdraw netlister was around 1500; the serial number for the Cadence netlister was 12. If there are 1500 seats of one tool out there and 12 of another, which is getting the greater share of mind and dollars when a bug crops up? From that time on, I've always paid attention not only to whether a tool seemed suitable to my needs, but also to whether a significant number of other designers were using it. There may be a justification for being one of the few and the proud who use a special tool, but it'd better be good. If there's a problem with one of the tools I'm using, I want a lot of other people to be screaming bloody murder along with me. If some of those people work at Cisco, even better. How many people out there are using the Xilinx schematic capture tool on designs meant to generate revenue? How does that compare to the number using HDL? If you're using Xilinx's schematic capture tool, the answer should matter to you. I'm not thrilled with all this. Someday, maybe soon, I'll be forced to migrate from Verilog to something like SystemC not because it offers me some technical advantage, but because that's where the design crowd has migrated. Such is the universe we inhabit. Bob Perlman Cambrian Design WorksArticle: 54853
Ian Hickey <ihickey@ieee.org> wrote: > Does any manufacturer make a very small programmable logic device (with > FLASH storage) is say a SOIC-8 or similar. > > It's for a small home project that only has one output and only one input > (plus CLK) Now that some programmable logic is cheaper than odd TTL parts, a (OTP?) PLD with 14-24 pins would be very nice. Plug it into the programmer, type 74als526, remove device and insert in circuit. -- http://inquisitor.i.am/ | mailto:inquisitor@i.am | Ian Stirling. ---------------------------+-------------------------+-------------------------- Get off a shot FAST, this upsets him long enough to let you make your second shot perfect. -- Robert A Heinlein.Article: 54854
On Sun, 20 Apr 2003 19:26:23 GMT, Spam Hater <> wrote: Hello S.H, Thanks for the prompt reply. > >The ATF750 is made by Atmel, not Altera. Kind of important. > Ooops ;-) I did know that, I guess my brain was elsewhere ! >It's an interesting part (The AFT750), but sole-sourced, and has poor >software support. Last time I checked, it was expensive too. > >Get yourself a copy of Warp. A decent introduction to HDL design, and >it has the synthesizer and simulator for standard PAL parts. > >Start with the 16V8 / 22V10 and work your way up. > Thanks for the advice, I will look into it Regards, -WArticle: 54855
Why not a dedicated pair of wires for transmitt, and a dedicated pair of wires for receive? TX in node A to RX in node B, TX in node B to RX in node A. A full-duplex connection. TC "Joona R" <jonesky1@hotmail.com> wrote in message news:2f3990c3.0304200441.5626b7b7@posting.google.com... > Hello! > > Can I use bidirectional mode with differential LVDS? Target device > will be Altera Cyclone. > I know there are two kinds of resistor connection for transmiter and > receiver (Altera application note 254, figure 3 on page 5 > http://www.altera.com/literature/an/an254.pdf ). > But I need a transreceiver. Should I use same connection as with > transmitter or something else? Or is only way to have transmitter and > receiver pins & resistors and then connect them to together? > > Thank you for your help! > > - JRArticle: 54856
Yes there are many small 8-pin micros out there which are very cheap sub $1. The project does have some medium speed requirement but probably could be achieved with PIC12C508 or MSP430F1101A. My main reason for looking for a CPLD or similar was I have years of micro work and was looking for a challenge. Is no one aware of a third tier manufacturer specialising in medium speed 10MHz to 30MHz logic with small pin count? The device does need to be small for the project to work. Thanks "Ian Hickey" <ihickey@ieee.org> wrote in message news:3ea276da$1@clear.net.nz... > Does any manufacturer make a very small programmable logic device (with > FLASH storage) is say a SOIC-8 or similar. > > It's for a small home project that only has one output and only one input > (plus CLK) > > Thanks in advance. > > Ian > >Article: 54857
On Sun, 20 Apr 2003 22:30:57 +1200, "Ian Hickey" <ihickey@ieee.org> wrote: >Does any manufacturer make a very small programmable logic device (with >FLASH storage) is say a SOIC-8 or similar. > >It's for a small home project that only has one output and only one input >(plus CLK) > >Thanks in advance. > >Ian > Your subject line was "FPGA" ... then the answer is nope. Your message inquiry was " very small flash PLD in SOIC-8 or similar " .. then the answer is maybe ... depending upon your requirements.. An simple example would be Atmel ATF16v8 in a 16 pin TSSOP which isn't much bigger than a SOIC-8 ... but only 8 flops doesn't give much logic power. I have used these on boards as a address decoder where I have no space available. A bit more exotic in a very tiny package would be a Xilinx CPLD Coolrunner II XC2C32 or 64 in a chip scale package ONLY 6 by 6 mm !! and that has 32 or 64 flops ... ( but the package prolly would not be easily manageable as a home project ) KBArticle: 54858
Ravi Bhat <Ravi.Bhat@xilinx.com> wrote in message news:<3EA079F4.BE6A47C@xilinx.com>... > test html > > -- last test :()Article: 54859
"Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:<RCDoa.304635$Zo.60919@sccrnsc03>...
> "Yang-Tzu" <d8728141@knight.fcu.edu.tw> wrote in message
> news:85c3c777.0304201025.73ad6bf9@posting.google.com...
> > Hello,
> > Is there any information about Xilinx bitstream file format?
> > I would like to download bitstream using my own program, but I have no
> > idea how the bitstream download to Xilinx chip.
> > Is it read 8-bit per clock to the download cable or ..?
>
> There is plenty of information on how to download a bitstream. There is
> very little on how to create a bitstream from a logic configuration.
>
> Last I knew you could do it in serial, or 8 bit parallel. Parallel loading
> clocked at about 1/8th the serial speed, but is useful if you use an 8 bit
> wide EPROM, or for loading from another processor.
>
> -- glen
Thanks for your help.
I have woldering that if the way to download FPGA is the same
between XC4000 and Virtex, or between Virtex and Spartan series FPGA.
We can download the bitstream to XC4000 series FPGA by using XChecker.
Unfortunately, the new version of ISE is not support XChecker. While
Virtex and XC4000 support Boundary Scan port, can we download
bitstream by Boundary Scan port?
That means if I know the way to download FPGA, I don't have to know
the bitstream file format. Is that right?
thanks.
Fan.
Article: 54860Loi Tran wrote: > > In article <b7ssbr$5jk$2@hercules.btinternet.com>, "Leon Heller" <leon_heller@hotmail.com> wrote: > > > >"Loi Tran" <leotran@att.net> wrote in message > >news:Rehoa.35691$cO3.2680296@bgtnsc04-news.ops.worldnet.att.net... > >> Hi, > >> > >> Has anyone had any success with Webpack 5.2 installation on Windows 98? I > >> get to the point where it asks me to check off on approval of their (we > >own > >> yours ass!) license, but the check box is greyed out. So I can't proceed > >any > >> further. > >> > > > >5.2 only works with Win2000 or XP. > > > >Leon > > Thanks to everyone who replied. Crap! If I'd known this I wouldn't have paid > for the CD to be shipped to me from Xilinx in the first place. It is only *supported* under 2000 and XP. I don't know that they disable it under any other Windows OS. If they did, this would be a silly way to show it! I bet there is something else going on!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54861
Falk Brunner wrote: > > "Ian Hickey" <ihickey@ieee.org> schrieb im Newsbeitrag > news:3ea276da$1@clear.net.nz... > > Does any manufacturer make a very small programmable logic device (with > > FLASH storage) is say a SOIC-8 or similar. > > > > It's for a small home project that only has one output and only one input > > (plus CLK) > > AFAIK no. The smallest pincount for CPLDs/FPGAs is somewhere at 44 pins. If > you need such a small logic device, and the speed requirements are not too > high, you may use a microcontroller. They are available in such small > packages, e.g. ATMEL offers them (AVR devices) I know a way to convert a 44 pin QFP into a much lower pin count device. You will still need the power, ground and config signals, but I can cut the IO down to the two the OP needs.... where are my pliers? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54862
Bill Hanna wrote: > > I reported all errors to Xilinx. There are a large number of cases > reported. > > I used schematics instead of VHDL because VHDL is inefficent > compared to schematics. > I benchmarked 3 different designs: 10 stage PN code generator, 27 > stage PN code generator and a 32X32 multiplexer. > > The VHDL designs required 40% more gates than the schematic > designs. The schematic design is converted to VHDL primitives by XST. > > I have a 12 channel signal processor design that uses 17,000 > slices. If implement in VHDL it would take 24,000 slices. The added > cost of the higher density device (XC2V6000) would increase the RE > cost by $3.5K per system. > > Thanks for your advice and for taking the time to respond. > Bill Hanna I can't dispute your benchmarks, but I can tell you that you can work around them. Just as the schematic design was translated into instantiated VHDL, you can always code the same way. But I seriously doubt that there really is such an overhead. The designs I have done have ended up with very little loss of efficiency if that was what I needed. A lot of it is coding style. I know I can infer very nearly the same gates I draw in a block diagram. Most of the time if my design is larger than my estimate it is because my estimate is wrong. A good person to discuss this with is Ray Andraka. He left his schematic library behind once he learned to use VHDL effectively. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54863
Khim Bittle wrote: > > On Sun, 20 Apr 2003 22:30:57 +1200, "Ian Hickey" <ihickey@ieee.org> > wrote: > > >Does any manufacturer make a very small programmable logic device (with > >FLASH storage) is say a SOIC-8 or similar. > > > >It's for a small home project that only has one output and only one input > >(plus CLK) > > > >Thanks in advance. > > > >Ian > > > > Your subject line was "FPGA" ... then the answer is nope. > > Your message inquiry was " very small flash PLD in SOIC-8 or similar > " .. then the answer is maybe ... depending upon your requirements.. > > An simple example would be Atmel ATF16v8 in a 16 pin TSSOP which isn't > much bigger than a SOIC-8 ... but only 8 flops doesn't give much logic > power. I have used these on boards as a address decoder where I have > no space available. > > A bit more exotic in a very tiny package would be a Xilinx CPLD > Coolrunner II XC2C32 or 64 in a chip scale package ONLY 6 by 6 mm !! > and that has 32 or 64 flops ... ( but the package prolly would not be > easily manageable as a home project ) > > KB Khim, you beat me to it! I have been looking hard at some of the smaller packages on the Coolrunner (I) chips. The XCR3032XL (3.3 volt Vdd and 5 volt tolerant) comes in the 7 x 7 mm CS48 package and is pin compatible with the XCR3064XL. Best of all the XCR3032XL is only $2! How much logic do you need? CPLDs are very powerfull in their own way since they can combine *huge* AND terms. The Coolrunner parts are very low power as well, typically drawing less current than a similar TTL function! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54864
I have generated a hard macro of a small module with FPGA editor. (xilinx ISE) But I'm having problems with declaration of the hardmacro in my toplevel design. My toplevel design does not know the macro. Can I add it to a library or how do can do this? Thanks!Article: 54866
I recently discovered that the AT94K FPSLIC by Atmel has 5 volt tolerant IO. This makes it a viable candidate for a design that I was planning to use a Coolrunner and an ARM for. To use the AT94K I would need to add a configuration EEPROM, a small ADC and perhaps a couple other simple analog parts. Also, I would need to get this part in a small package with high pin count such as the 256 pin BGA. I see on some distributor web sites that this package is available. But I don't see it in the data sheet, so I have no idea of the IO pin count. Anyone know if this package is *really* available? How many external FPGA IOs does it have? I have also seen a listing for a 352 pin BGA as well as an AT94K20 device. Any of this real? The other problem is price. The CPLD/ARM solution would cost about $25 to $30 total. The AT94K10 alone is in the $25 range and I can't tell if it will have enough IO. The AT94K40 is around $50 and it still might not have enough IO. Are these prices real? They seem so high compared to other solutions. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54867
Hi - I would like to implement a 256 tap complex FIR filter. It should run at 30MHz and latency should be lower than 200ns... Moreover, the coefficients should be updatable 'live', ie, without interrupting the filtering process... Seems to be quite a hard task ! Does anyone have an idea of FPGA implementation ? What kind of circuit should be used ? How many CLB/LE would it take ? Thanks in advance ArthurArticle: 54868
An update on my previous post: Yes - this does indeed generate a fully functional (and reasonably fast) signed multiplier with WebPACK - even in the Spartan-II without hardware multiply block. Tried it in WebPACK 4.2 I had lying around - there it does NOT work: 'signed' is not recognised as keyword but treated as an identifier (with predictable errors ;-)). I don't know what will happen in WebPACK 5.1 - had to de-install that one when installing 5.2... In WebPACK 5.2, the following also turns out to work just fine when declared inside a module: reg signed [7 :0] d2vSGNMULT8_8lhs ; reg signed [7 :0] d2vSGNMULT8_8rhs ; wire signed [15 :0] d2vSGNMULT8_8res = d2vSGNMULT8_8lhs * d2vSGNMULT8_8rhs ; With these, you can set '=' the values you want to the 'lhs' and 'rhs' regs inside an 'always' construct, take the result from the 'rhs' wire. Nice - now I have to figure out a way to generate this automatically from the '+*+', '+*' and '*+' IDaSS operators ;-) Greetings from Holland, Ad Ad Verschueren wrote: > Hi all, > > OK, call me stupid - I must have missed something in the WebPACK docs. > I searched for a long time for signed multipliers in Verilog, and these > can be spec'ed in Verilog 2001 by adding the 'signed' keyword or '$signed()' > operation. I started playing around with IDaSS generated WebPACK code and > tried to compile the following with WebPACK 5.2: > > module MULT (a,b,y); > > input signed [7 :0] a ; // Normal IDaSS input > input [7 :0] b ; // Normal IDaSS input > output signed [15 :0] y ; // Normal IDaSS output > > reg [15 :0] y ; // Procedural output drive channel > > always @ (a or b) > begin > > // Original IDaSS source code: > // > // | y := a * b > > // Only a single function here... > > y = > a * > b; > end > endmodule // MULT > > The 'signed' is not recognised as a keyword in the editor, so my hopes were > not that high. But it synthesized without a hitch. When I opened the 'view RTL > schematic' process and clicked deeper into the hierarchy, I found to my *absolute > astonishment* that WebPACK had generated a 9 by 8 bits *SIGNED* multiplier (or at > least claimed to have done so), with bit 8 of the 9 bits wide input tied to 1'b0 > make that input 'unsigned'. > > Strange thing is that $signed() is not allowed, and also that it is not possible > to use the 'signed' on inputs and outputs of a Verilog task (there, they are > ignored and I got an unsigned multiplier). > > It's a bit late out here, so I'll download the result in an FPGA tomorrow and play > with dipswitches and leds until I'm certain this is not a late April Foolsday joke ;-) > > Has anyone seen this before, or did I work with WebPACK all these years with my > eyes closed? Note that I'm sythesizing for a Spartan-II (which does not have > hardware 18x18 bits signed multiply blocks). > > Greetings from Holland, > > Ad Verschueren > > http://www.xs4all.nl/~averschu/idass >Article: 54869
Christopher Fairbairn <ckf13@student.canterbury.ac.nz> wrote: > Hi, > > Uwe Bonnes wrote: >> :> A recent well configured wine with the prerequisited for Installshield <snip> > Finally got some time to look at this again and it's working like a charm! > Thank for all the great advice. <snip> > 1) I had no luck with the version of wine that I was using (sorry can't > remember what it was now) so I upgraded to Wine 20030408 and things > immediatly started to look better. I've configured WINE as a "fake windows" > rather than telling it where my real windows installation is. Done this, with the same version. <snip> No problems up to here. > > 4) set the XILINX environment variable to the installation directory for > Webpack (in my case C:\xilinx). This should allow you to execute most of > the executables, all located in $XILINX\bin\nt\. For example "wine > C:\xilinx\bin\nt\par.exe", or ise.exe. However you will most likly get > errors with respect to msvcirt.dll. I've downloaded a copy of MSVCIRT.dll, though I'm not sure it's the right version. Par.exe reveals a command-line helpscreen. ise.exe bombs, after missing MFC42.dll Did you copy any other DLLs? Looking through the documentation left me confused as to enviroment variables. Where is XILINX set? > > 5) I copied msvcirt.dll over from my Win2k machine and placed it in > ~/c/windows/system32 <snip> Thanks. -- http://inquisitor.i.am/ | mailto:inquisitor@i.am | Ian Stirling. ---------------------------+-------------------------+-------------------------- Two parrots sitting on a perch. One asks the other, "Can you smell fish?"Article: 54870
> Anyone know if this package is *really* available? Yes, it is, I bought some for a prototype I'm working on. > How many external FPGA IOs does it have? 162 for AT94S40 > I have also seen a listing for a 352 pin BGA as well as an > AT94K20 device. AFAIK this is false information. > The AT94K10 alone is in the $25 range and I can't tell if it will > have enough IO. AT94K10 in PQFP-208 package -> 116 FPGA I/Os MarcArticle: 54871
Lost, All FPGAs don't have this problem. For example, Virtex II, Virtex II Pro, and Spartan III don't have this problem. "This problem" was something that had to be fixed by IC design, and avoided. So it is not a natural result of an SRAM based FPGA. Austin LostSignal wrote: > > Does Altera officially recognize the Power On Surge problem ? > > I didn't find any references to this problem in Altera's datasheets or > > App. notes. Their datasheets don't specify start up current as well. > > One of our designs sometimes has strange power-up problems at the low > > temperature. We never attributed this problems to the FPGA. Actually I > > didn't hear about this problem before (thank you, Martin). Now I'm > > starting to suspect that the problem is related to FPGA. The design is > > based on ACEX 1K100 device. Where can I find Power On Current profile > > for this device ? > > Apparently ALL SRAM based FPGAs experience this problem to some > degree. At the startup the configuration SRAM is in unknown state and > that causes large current surge that must be satisfied in order for > FPGA to configure properly. AFAIK the differences between Xilinx and > Altera in this regard are: > 1. Xilinx publicly acknowleged this problem some time ago has several > articles on it. I have not seen much from Altera (correct me if I am > wrong). > 2. The rumor is Altera has a somewhat smaller surge and people have > less trouble with it. Dunno how true it is though. I've heard from an > Altera guy that a really large Altera part can draw 2.5 A. The maximum > current specified for Xilinx is 2 A at low temperature. Go figure.. > > Lost SignalArticle: 54872
Bob Perlman wrote: > Hi - > > On Sun, 20 Apr 2003 14:20:21 -0400, eric - Mtl <notervme@sympatico.ca> > wrote: > > <stuff snipped> > >>Forcing the switch to HDL by making the schematic tool barely usable >>is a bit like poisoning water supply to increase bottled water sales. > > > Some days it may seem like Xilinx is trying to move people to HDL by > sabotaging their own schematic capture tool, but I find it hard to > believe that's actually the case. The reality is a bit more banal: > companies spend dollars where the customers are, or where they think > the customers will be. And when customers started voting for HDL with > their dollars, Xilinx's development dollars followed. > Well, "poisoning water" certainly was an overstatement ... what about not changing the filters and just not fixing the filtration plant until those brave enough to drink it do it at their own risks ... > I'll give you a for-instance that has nothing to do with > HDL-vs-schematics: many years ago I worked for a company that used > Sun-based Cadence Concept for its board-level schematic capture tool. > Concept was actually quite a good program, but I made the mistake of > thinking that if we used it for board-level stuff, it would also make > sense to use it for FPGA design. I mean, why in the world would you > ask all your designers to learn both Concept and, say, Viewdraw, when > they could use Concept for everything? > > It turns out that there was a very good reason: the Concept-to-Xilinx > netlist path didn't work worth a damn. It was bug-ridden and about > half a year behind the Viewlogic package in supporting new parts. And > the path from Xilinx schematics to Verilog simulation netlists was > equally broken. All in all, it was a disaster. > > The reason for the problem became obvious sometime later, after I'd > ordered a copy of Viewdraw and the accompanying netlister for use on a > set of FPGA designs. The CAE manager forwarded me an invoice for > maintenance on both the Cadence-to-Xilinx and Viewdraw-to-Xilinx > interfaces, and here's what I saw: the serial number for the Viewdraw > netlister was around 1500; the serial number for the Cadence netlister > was 12. If there are 1500 seats of one tool out there and 12 of > another, which is getting the greater share of mind and dollars when a > bug crops up? > > From that time on, I've always paid attention not only to whether a > tool seemed suitable to my needs, but also to whether a significant > number of other designers were using it. There may be a justification > for being one of the few and the proud who use a special tool, but > it'd better be good. If there's a problem with one of the tools I'm > using, I want a lot of other people to be screaming bloody murder > along with me. If some of those people work at Cisco, even better. > > How many people out there are using the Xilinx schematic capture tool > on designs meant to generate revenue? How does that compare to the > number using HDL? If you're using Xilinx's schematic capture tool, > the answer should matter to you. > > I'm not thrilled with all this. Someday, maybe soon, I'll be forced > to migrate from Verilog to something like SystemC not because it > offers me some technical advantage, but because that's where the > design crowd has migrated. Such is the universe we inhabit. > > Bob Perlman > Cambrian Design Works > > I understand the problem with using a "marginal" tool, but I really don't think schematics user are so few. Many peoples in this newsgroup are at or near the leading edge regarding FPGA design. They are early adopters, and for peoples whose job is to fill up a XC2V8000 in no time ;-) , HDLs certainly are the only way to go. But that's not the whole story ... We don't all use FPGAs to encode video, do massively parallel DSP, create wire speed TCP/IP routers, wireless relays or ASIC prototypes. Most peoples, including me, don't do "rocket science" multi million gates designs. The design I'm working on now fills about 70% of an spartan II XC2S100 with SIO & async interfaces, Delta Sigma converters, a memory interface & MMU, dynamic bus sizer, processor interface, LCD controller, timers, interrupt controller, IO debouncers, infrared RC5 decoder ... For me, the FPGA is just a part of the design (a part that's getting bigger these days). Electronics designers are a conservative bunch ... give them a tool they can grasp immediately and you'll get their business. Tell them that they first need to learn a completely new and somewhat complex language and you lost them, or at least significantly delayed adoption. This is even more the case for CPLD and CoolRunner users. For them, I really can't see a break even point where the time spend learning HDL would be compensated by more convenient design entry. Also note that for CPLDs, the few extra gates a HDL based design will infer (compared to a schematic based design) can force them to use the next bigger part, thus adding a significant cost. Many applications could benefit immensely from using FPGAs, and still don't do. Creating a new entry barrier by deprecating the most "natural" design entry option doesn't seem like a wise move, especially when all that is required is to debug and fix the existing tool ... my 0.02 ... Eric.Article: 54874
rickman wrote: > Loi Tran wrote: > >>In article <b7ssbr$5jk$2@hercules.btinternet.com>, "Leon Heller" <leon_heller@hotmail.com> wrote: >> >>>"Loi Tran" <leotran@att.net> wrote in message >>>news:Rehoa.35691$cO3.2680296@bgtnsc04-news.ops.worldnet.att.net... >>> >>>>Hi, >>>> >>>>Has anyone had any success with Webpack 5.2 installation on Windows 98? I >>>>get to the point where it asks me to check off on approval of their (we >>> >>>own >>> >>>>yours ass!) license, but the check box is greyed out. So I can't proceed >>> >>>any >>> >>>>further. >>>> >>> >>>5.2 only works with Win2000 or XP. >>> >>>Leon >> >>Thanks to everyone who replied. Crap! If I'd known this I wouldn't have paid >>for the CD to be shipped to me from Xilinx in the first place. > > > It is only *supported* under 2000 and XP. I don't know that they > disable it under any other Windows OS. If they did, this would be a > silly way to show it! I bet there is something else going on!!! I'd like to point out again that this policy is seriously broken. I feel it is an arbitrary decision on the part of Xilinx that will bite them in the ass, much like their half-hearted support of schematic capture in early versions of webpack. I'll keep running Foundation 3.1 with Win98 and legacy devices and start evaluating other vendors products for new designs.
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