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On Thu, 17 Apr 2003 23:13:38 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >So the Xilinx parts have one size, the XC2S150E, that gives a >significant price advantage over the Cyclone parts. But then this is >based on "list" prices and means nothing once you start wheeling and >dealing with your disti. > > > Xilinx LUT+FF pairs Altera LEs >* XC2S50E 1,536 $ 16.61 >* XC2S100E 2,400 $ 24.47 EP1C3 2,910 $16.60 (T144) >* XC2S150E 3,456 $ 26.84 EP1C4 4,000 $??? >* XC2S200E 4,704 $ 31.29 >* XC2S300E 6,144 $ 48.01 EP1C6 5,980 $33.20 >* XC2S400E 9,600 $ 91.52 EP1C12 12,060 $87.00 > >* XC2S600E 13,824 $152.90 EP1C20 20,060 $222.00 > (FG456) (FT400) > rickman ... i would not disagree with the above ... however some preliminary benchmarking has shown that the cyclone "8" grade parts are definitely faster than the xilinx "-6" parts which you have priced above ... to make an apples to apples comparison if you use the xilinx "-7" grade parts the cyclone pricing even looks better ... for example the XC2S200E-7FT256 goes from $31 to $36 ... and now is more expensive than the EP1C6 with more capability at $33 >For a minute I thought you had made a mistake on the logic cell count >until I remembered that the Xilinx data sheet got "creative" on what >they call a logic cell. Someone in marketing should be shot for that >one. Gate counts are pure myth. But I always thought I knew what a >logic cell was. > > >> The six Spartan-IIE devices in the 256-ball BGA package range in price >> from US$16.61 to $91.52 in 24-99 quantity, depending on speed grade >> (SOURCE: www.avnetmarshall.com). Pricing in the U.S. is also available >> via www.insight.com and http://www.nuhorizons.com. Nearly all >> device/package combinations are in stock at the distributor. The wider >> range of densities provides finer granularity on logic vs. I/O. If your >> design is primarily I/O, then prices start as little as $16.61. >> >> Compare this to only two Cyclone devices in this package, ranging in >> price from US$33.20 to $174 in 24-99 quantity, depending on speed grade >> (SOURCE: www.arrow.com). All devices show 6 weeks lead-time. > >Maybe only two in *that* package. But Altera's approach is to use >packages with a compatible footprint. So you can buy the 1C6 and the >1C12 in the F256 package and move up to the 1C20 in the F324 or F400 >package in a compatible footprint. Design this in up front and you >won't have to redo your PCB. I haven't looked at this, are you saying a 1C6 in a F256 package will work on a board with an F324 footprint ?? Or you can move *down* to the 1C4 in the >F324 or F400 package and get up to 301 IOs! The 1C4 is most interesting to those folks who need a small logic part with a lot of I/O for switching wide busses or something .... but that's not me ... I need a couple of 16 bit buses plus controls and a lot of signal processing power at a low cost ... CBArticle: 54801
Steve, I'm not in the marketing/sales org., so I do not have access to pricing information to rebut your cost claims, but I will respond to some big technical inaccuracies in your post. 1) A 4:1 multiplexor takes 2 LEs in Stratix/Cyclone. A 16:1 takes 10 LEs. And your levels of logic are somewhat bogus -- you guys go through an extra built-in mux for a 4:1 with 2/LEs, we use a cascade chain. We can argue until we're blue in the face, but the bottom line is users should push the button on both tools to see performance. Cyclone is much faster than Spartan IIE. 2) LE counts. You claim 15% advantage. Where's the data? We have a public white paper on Stratix vs. Virtex II LE counts across 87 designs. Stratix uses on average 9% fewer LEs. As can be seen by the chart, there are some designs that Virtex II wins big on. There are also designs Stratix wins big on. The same analysis should apply to Spartan IIE vs. Cyclone, as they have similar CLB/LAB structures. This is real engineering data, not marketing fluff -- no circuits were removed, Xilinx tools were not crippled. http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf 3) Shift registers/FIFOs. As you point out, you're only using flops if doing a shift register. Cyclone was architected to tolerate high amounts of register packing. Quartus is very good at packing registers with unrelated LUTs without hurting performance. Also, shift registers can instead be implemented in RAMs (handled for you with the ALTSHIFT_TAPS). This is handy if (a) you don't need the RAM or (b) you have wide shift registers -- it takes 1 RAM for 1 16-bit shift register as you say -- but still only 1 RAM for 18 16-bit shift registers if they have the same control logic, such as a FIFO. 4) You say 25% die size advantage due to the shrink factor (0.13/0.15)^2. Cyclone is not the same architecture as Spartan IIE. There are architectural advantages (due to reduced routing, targeted resizing of transistors to optimize area, etc.) that can make that bigger -- but I can't say for sure, since I don't have the two chips and a ruler :) In the end, users really just care about cost and performance, and the underlying technology doesn't matter too much. 5) 300mm is not necessarily cheaper than 200mm. 300 mm machinery and fabs are newer, haven't been tweaked as well, etc. so defect densities can be higher at first. Obviously, over the long term 300 mm will be cheaper than 200 mm, just as 200 mm was cheaper than 150 mm. Looking at the industry as a whole, 2003 looks like the year of transition. You guys (from your press releases) feel that you get better overall costs out of 300mm now. We (from our press releases) feel that transitioning mid- to late-year will be best. Same goes for 90nm -- of course it will be cheaper at some point, but will that be 2003, 2004, .... I forgot IIE was 0.15u -- thanks for clarifying that. Regards, Paul Leventis Altera Corp. "Steve Knapp" <steve.knapp@xilinx.com> wrote in message news:3E9F4FC5.C3C3B027@xilinx.com... > Sorry, but I feel the need to clean up a few common misconceptions. > > Only Spartan-II FPGA (non-E) family, announced January 2000, is 0.18u. > > Spartan-IIE is 0.15u and has been in volume production for over 18 > months now. Still, Cyclone at 0.13u potentially has a 25% area > advantage (potentially a ~25% cost advantage) at comparable densities > (1-((0.13^2)/(0.15^2)))=25%. However, Spartan-IIE is manufactured on > 300 mm wafers, which delivers about a 30% cost reduction over 200 mm > production. Cyclone, I understand, is not yet on 300 mm wafers but will > be about the same time that the 90 nm Spartan-3 devices start > production. In production, Spartan-3 will be at 90 nm on 300 mm, > offering a double cost benefit. > > Another posting under this same thread shows that cost is more than just > LEs. Spartan-IIE solutions at 180+ pins start at just US$16.61 while > Cyclone starts at $33.20. Some applications need more LEs at this I/O > range, some don't. > > Also, the claim about Cyclone being cheaper per LE is a bit spurious. > The claim is only true assuming that you never use any of the following > logic structures. > > -- Multiplexers larger than 2:1 > -- Internal bussing structures > -- Small FIFOs > -- Delay buffers or serial-in/serial-out shift registers > -- Multipliers > > Take a simple 4:1 multiplexer. How many LEs are required to implement > this feature in both architectures? Let's define an LE as a LUT+FF pair > inside the Altera LAB or Xilinx CLB. > > Spartan-IIE: 2 LEs, one level of logic > Cyclone: 3 LEs, two levels of logic > > In this simple example, Cyclone uses 50% more LEs and an additional > layer of logic. > > Now expand it to an 8:1 multiplexer. > > Spartan-IIE: 4 LEs, one level of logic > Cyclone: 8 LEs, three levels of logic > > Again, Cyclone uses 50% more LEs and an additional layers of logic.. > > Now, let's look at an example where we have eight byte-wide functions > connected to a common bus. How much logic is required to create the > bi-directional bus? > > Spartan-IIE: 0 LEs (the architecture has internal three-state > functionality) > Cyclone: Requires eight 8:1 multiplexers at 6 per instance, or 48 > LEs. > > Now, let's look at a serial-in/serial-out shift register. > > Four-deep shift register: > > Spartan-IIE: 1 LE (the architecture has distributed RAM/serial shift > functionality) > Cyclone: 4 LEs (okay, in reality, it's only the flip-flops that are > used) > > Sixteen-deep shift register: > > Spartan-IIE: 1 LE (the architecture has distributed RAM/serial shift > functionality) > Cyclone: 16 LEs (okay, in reality, it's only the flip-flops that are > used) > > In this example, 1 Spartan-IIE LE equals 16 Cyclone LEs or in some > cases, one Cyclone block RAM. > > In real applications, Spartan-IIE uses roughly 15% fewer LUT+FF pairs > than Cyclone. Use Spartan-IIE for any small buffering or DSP > applications and Spartan-IIE offers even greater advantages. > > Many of the Cyclone architectural limitations vs. Spartan-IIE are > outlined in one of Altera's own application notes. > > AN 255: Guidelines to Migrating Spartan Designs to Cyclone Designs > http://www.altera.com/literature/an/an255.pdf > > The question is now "How many LEs do I get per dollar?" The question is > "How much logic can I implement per dollar?" > > These opinion are obviously my own and may not reflect those of my > employer. > > -- > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3 > E-mail: steve.knapp@xilinx.com > ---------------------------------Article: 54802
Hi, for exhaustive testing of FPGA'S v make use of LFSR's. and to generate the maximun number of output states v have to feedback the xnor output of the cetain flipflop outputs to the input of the first flipflop. and it is associated with the maximum polynomial. i would like to know how to find out the maximum polynomial. i have gone through the xilinx date sheets and they gave just the number of the flip flops whose ouput should b given to the xnor gate input. thanking you naveenArticle: 54803
Good qustion. I did not know what is was so I hacked a little. It is the comand line for the fpga_editor. IT can be run from the dos command line or a batch file. Type fpga_edline -h on the command line. Steve "Steve Harlow" <sharlow1@san.rr.com> wrote in message news:4uBna.5850$2x2.3081330@dca1-nnrp1.news.algx.net... > Anybody know what fpga_edline.exe is? > What it is useful for? > How to use it? > > >Article: 54804
naveen <cvmnk@yahoo.com> wrote: > i have gone through the xilinx date sheets and they gave just the > number of the flip flops whose ouput should b given to the xnor gate > input. Maybe the tool at: <http://www.logiccell.com/~jean/LFSR/> could help you. WD --Article: 54805
Just a guess but it sounds like a way to make an adder that uses the hardwired add circuitry in a FPGA. If you use just gates the mapper will use Look Up Tables (LUTs) instead of the hardwired resources... Steve "Kang Liat Chuan" <kanglc@starhub.net.sg> wrote in message news:3e9eeccc@news.starhub.net.sg... > Hi comp.arch.fpga, > > I came across a component in Orcad named ADD_BITSLICE, and am thinking what > it does. > > It seems it is not a lower level schematic, neither is it a > logiblox/coregen. The ports are: > > BIT_PREV : in std_logic; > BIT_NEW : in std_logic; > BYTE0 : in std_logic; > BIT0 : in std_logic; > CE : in std_logic; > CLK : in std_logic; > ACC_NEW : out std_logic; > > I know this may sound silly, but it seems pretty simple to construct this > component using AND, XOR and a FF. So why is it a primitive/macro component? > > I've search many places, but don't seem to find this component. Anyone who > can help, thanks! > > Regards, > LC > >Article: 54806
CB wrote: > > On Thu, 17 Apr 2003 23:13:38 -0400, rickman <spamgoeshere4@yahoo.com> > wrote: > >So the Xilinx parts have one size, the XC2S150E, that gives a > >significant price advantage over the Cyclone parts. But then this is > >based on "list" prices and means nothing once you start wheeling and > >dealing with your disti. > > > > > > Xilinx LUT+FF pairs Altera LEs > >* XC2S50E 1,536 $ 16.61 > >* XC2S100E 2,400 $ 24.47 EP1C3 2,910 $16.60 (T144) > >* XC2S150E 3,456 $ 26.84 EP1C4 4,000 $??? > >* XC2S200E 4,704 $ 31.29 > >* XC2S300E 6,144 $ 48.01 EP1C6 5,980 $33.20 > >* XC2S400E 9,600 $ 91.52 EP1C12 12,060 $87.00 > > > >* XC2S600E 13,824 $152.90 EP1C20 20,060 $222.00 > > (FG456) (FT400) > > > > rickman ... i would not disagree with the above ... however some > preliminary benchmarking has shown that the cyclone "8" grade parts > are definitely faster than the xilinx "-6" parts which you have priced > above ... to make an apples to apples comparison if you use the xilinx > "-7" grade parts the cyclone pricing even looks better ... for example > the XC2S200E-7FT256 goes from $31 to $36 ... and now is more expensive > than the EP1C6 with more capability at $33 Perhaps that is useful if you *need* the speed of the -7 parts. Just like users who *need* the 182 IO of the XC2S50E in the FT256 package while the bigger EP1C3 at the same price does not have the same IO. There are a lot of gaps in each line around the edges and in the corners. But the real point is that the price is what ever you can negotiate with the vendor, not the list price on the web. Buying chips is not too much different from buying cars. You need to let them know you *have* options and can take your business elsewhere. > >Maybe only two in *that* package. But Altera's approach is to use > >packages with a compatible footprint. So you can buy the 1C6 and the > >1C12 in the F256 package and move up to the 1C20 in the F324 or F400 > >package in a compatible footprint. Design this in up front and you > >won't have to redo your PCB. > > I haven't looked at this, are you saying a 1C6 in a F256 package will > work on a board with an F324 footprint ?? Altera calls this SameFrame pinout and it is documented in app note 90 for the (at this time) older part lines. The means they all have a solid BGA foot print without a hole in the center. So this will be the hardest to route. But the core of the larger packages matches the footprint of the smaller BGAs. And of course they keep the same pinout between the different chips as well. > Or you can move *down* to the 1C4 in the > >F324 or F400 package and get up to 301 IOs! > > The 1C4 is most interesting to those folks who need a small logic part > with a lot of I/O for switching wide busses or something .... but > that's not me ... I need a couple of 16 bit buses plus controls and a > lot of signal processing power at a low cost ... No, it is *me*. It is not so much switching busses. I have two busses that need to be interfaced and multiple IO devices. I could probably put this design in a 50 kgate part (real gates not counting the memory), but a 150 kgate part (with memory) is still very cost effective. We will see where the EP1C4 comes in the price range. IOs cost on the die and at test time. So it may be as expensive as the EP1C6 which has more LEs, but less IO. Heck, you can't even get them in the same package. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54807
Steve, FPGA_Edline is a command line version of FPGA Editor. You can run scripts with this tool. It's commonly used for designers who has a ready made script that adds probes, etc... You can save the scripts in FPGA Editor. FPGA_Edline will run commands that's listed in the FPGA Editor help menu. Regards, Wei Steve Harlow wrote: > Anybody know what fpga_edline.exe is? > What it is useful for? > How to use it?Article: 54808
Hi all, Please can you tell me which version of megawizard do I need to use to get the right VHDL when I create a LPM_DP_RAM? With the Quartus 2.2, I need to write myself the LPM_TYPE string Generic to avoid error during the P&R with Quartus 2.2 (after synthesis with Leonardo or Precision) ? Why/When/How to get the right VHDL with the right generics when we run a lpm_dp_ram megawizard? thanks, happy easter damienArticle: 54809
Hi Jim, I've made a couple avalon masters for various projects and while I haven't seen the exact behavior you're seeing, I have a couple ideas - you might have given these a try already... First off, a rather silly one: Sounds like the addressing is coming along fine, but what about the other control signal(s) (read, write, etc.)? Are they synchronous with the address bus on the 'avalon domain'? Really, as long as read or write is asserted before the 'avalon domain' cycle where the address is presented, then you're fine. The same applies to the writedata bus. It would also be prudent (in the case of rd/write/data coming from your other clock domain) to see that the control signals & data are being held long enough - until the next avalon domain clock edge after waitrequest goes low. > > However, I'm still stuck with an occasional failed memory write. > Through the same software debugging, it appears that the data was > never written to the RAM (at the desired address or otherwise). This > makes sense since the address calculation is performed in it the same > clock domain one cycle before the initiation of the actual write > sequence. In addition, I check that the 'waitrequest' line is low > (inactive) before releasing the write_n line. > > By design, if the write sequence does not execute within 30-35 clock > cycles from the receipt of the handshake, it will be aborted. I'm > assuming that a Avalon Bus Master write sequence to memory, even with > the occasional 'waitrequest', should execute within a few clock > cycles. > The other thing that comes to mind is this timeout logic. For a simple on-chip memory (as opposed to something like SDRAM where refreshes occasionally happen) there won't be much delay in getting waitrequest to go low, even if contention exists with another master (another silly one: do you have a high arbitration priority setup for any other masters talking to the memory?)... To rule out this as a possibility, I would try signal tap, or just code a single read register (CPU-readable avalon slave) which is loaded by the maximum # of clocks waitrequest is seen high during attempted write transaction on the master. Jesse Kempa Altera Corp. jkempa @ altera dot com (nospam: remove the spaces)Article: 54810
If you search the Xilinx website for app notes on LFSRs, they have one that lists the polynomials for maximal lengths. -Kevin "naveen" <cvmnk@yahoo.com> wrote in message news:b7f5eb6a.0304180733.1a1b773@posting.google.com... > Hi, > for exhaustive testing of FPGA'S v make use of LFSR's. and to > generate the maximun number of output states v have to feedback the > xnor output of the cetain flipflop outputs to the input of the first > flipflop. and it is associated with the maximum polynomial. > i would like to know how to find out the maximum polynomial. > > i have gone through the xilinx date sheets and they gave just the > number of the flip flops whose ouput should b given to the xnor gate > input. > > thanking you > naveenArticle: 54811
russelmann@hotmail.com (Rudolf Usselmann) wrote in message news:<d44097f5.0304180445.155370f8@posting.google.com>...
> billh40@aol.com (Bill Hanna) wrote in message news:<97d137ce.0304171001.5ec5461d@posting.google.com>...
> > I have been designing a Digital Signal Processor using the XC2V4000
> > chip.
> > Software errors in ISE 4.2 and 5.1 have caused long hours of delay in
> > developing the design:
> >
> > Software bugs in SystemAce causes erase problems in the MPM.
> > Deleting signal wires in ECS causes Fatal errors that crash the
> > system.
> > A large design exceeds the 2GB memory limit and generates a fatal
> > memory error.
> >
> > I have designed Altera chips for over 6 years and never had a
> > problem.
> >
> > All digital designers should stop designing new projects with
> > Xilinx ICs until Xilinx corrects all software problems with ISE.
> >
> > Bill Hanna
>
>
> In that case I think we need to boycott both Xilinx
> and Altera ;*)
>
> I had so many problems with both of them ... (actually
> in my case, I had more problems with Quartus than ISE).
>
> But really what we need to look at is the root of the
> problem: The OS you are running the tools on. Let me
> guess, you are using some version of Windoze, aren't
> you ? I have stopped upgrading ISE since Version 4.2
> and will not upgrade until they have a linux version.
> It supports all parts I need and will most likely need
> for the long future. Spartan 3 sounds very interesting,
> when that becomes widely available I have to reevaluate
> my decision.
>
> In my entire office, we have only ONE Laptop with
> Windows NT JUST for Xilinx ISE. Over 50 PCs with Linux,
> running all kinds of software to make ASICs. This has
> been our setup for about 3 years now - absolutely no
> complains.
>
> And while we at it, lets boycott Phillips until they
> make more reliable fluorescent (Ecotone) light bulbs
> that last more than 4 months, when the box claims
> they supposed to last 6 years (may be 4 months in
> Netherlands are equivalent to 6 years elsewhere, I
> have to check with their Government). They charge
> about $10 for the 20W one, but no dealer so far would
> replace them and uphold this warranty claim even
> though I have all receipts ... what a rip-off !
>
> rudi
> ------------------------------------------------
> www.asics.ws - Solutions for your ASIC needs -
> FREE IP Cores --> http://www.asics.ws/ <---
The OS is Windows XP PRO:
2GHz P4
1GB DDR RAM
3.5GB VM
40GB Hard Drive
We should have a method to rate these vendors listing the number of
software errors or bugs in their CAD tools and truth in number of
gates used.
Bill Hanna
Article: 54812Hi , I am using Xilinx ISE 4.2 I was able to synthesis (using XST) my designs in Virtex E architecture targeting xcv300e-8pq240 , everything was ok with it and functioning correctly, then i wanted to try thr same design in different device xcv200e-8pq240 , it gave me MAP errors and now when i try it again in the original xcv300e -8pq240 i am getting errors in the Translate process the foolowing error i get for all my output pins "ERROR:NgdBuild:467 - output pad net 'xxxxxx_OBUF' has an illegal buffer" I made sure all the synthesis and implement properties matched with those in my snapshot but i am still stuck with this problem. Any suggestions? VivekArticle: 54813
Hi Im tring to layout a mac fir filter in ISE 5.1 generated from core generator. Im having problems in synthezing the Xilincorelib library as it has textio and records in the vhdl files--- itried in Leonardo and also ISE 5.1. anyone tell me exactly how to go about the process of core genration and laying it out. thanks ParaagArticle: 54814
Find the app note on http://www.xilinx.com/apps/xappsumm.htm#xapp052 It does list the XNORed taps for max length sequences for LFSRs up to 140 bit length. But it does not give the mathematical background and the formula to develop these tap positions. Also note that the positions are not unique, there is usually more than one way to achieve max sequence length. I wrote this app note based on information generated by Wayne Stahnke while he worked in my applications group at Fairchild in 1970, and I credited him for this, as one always should. Search for LFSR at google.com for additional sources (good, bad, and bogus...) Peter Alfke ========================== Kevin Neilson wrote: > > If you search the Xilinx website for app notes on LFSRs, they have one that > lists the polynomials for maximal lengths. > -Kevin > >Article: 54815
test htmlArticle: 54816
Hi Damian, > Please can you tell me which version of megawizard do I need to use to > get the right VHDL when I create a LPM_DP_RAM? > With the Quartus 2.2, I need to write myself the LPM_TYPE string > Generic to avoid error during the P&R with Quartus 2.2 (after > synthesis with Leonardo or Precision) ? > Why/When/How to get the right VHDL with the right generics when we run > a lpm_dp_ram megawizard? As far as I can tell, unforunately none of the MegaWizards write the LPM_TYPE generic. The idea is to leave the component black-boxed and let Quartus synthesize the instantiation of the component you created with the MegaWizard. I have suggested including this parameter in the output of the Megawizard but it so far got nixed. Given that you work for Mantor, you may want to talk to one of the interoperability guys in the Precision team to see if they can put more force behind this. Many users would be thankful. Best regards, BenArticle: 54817
Out of curiosity, does anyone know the reason Xess discontinued its Virtex prototyping XSV boards and now offers only the SpartanII XSA ones? No demand? Too expensive?Article: 54818
Hi Im tring to layout a mac fir filter in ISE 5.1 generated from core generator. Im having problems in synthezing the Xilincorelib library as it has textio and records in the vhdl files--- itried in Leonardo and also ISE 5.1. anyone tell me exactly how to go about the process of core genration and laying it out. thanks ParaagArticle: 54819
> Does Altera officially recognize the Power On Surge problem ? > I didn't find any references to this problem in Altera's datasheets or > App. notes. Their datasheets don't specify start up current as well. > One of our designs sometimes has strange power-up problems at the low > temperature. We never attributed this problems to the FPGA. Actually I > didn't hear about this problem before (thank you, Martin). Now I'm > starting to suspect that the problem is related to FPGA. The design is > based on ACEX 1K100 device. Where can I find Power On Current profile > for this device ? Apparently ALL SRAM based FPGAs experience this problem to some degree. At the startup the configuration SRAM is in unknown state and that causes large current surge that must be satisfied in order for FPGA to configure properly. AFAIK the differences between Xilinx and Altera in this regard are: 1. Xilinx publicly acknowleged this problem some time ago has several articles on it. I have not seen much from Altera (correct me if I am wrong). 2. The rumor is Altera has a somewhat smaller surge and people have less trouble with it. Dunno how true it is though. I've heard from an Altera guy that a really large Altera part can draw 2.5 A. The maximum current specified for Xilinx is 2 A at low temperature. Go figure.. Lost SignalArticle: 54820
Altera have released an errata acknowledging the problem came for a batch of devices and is not indicative of the entire family. It should be less than or equal to 500mA at power up but a few weeks worth of EP1C6 had 1.2 Amps. http://www.altera.com/literature/ds/es_cycfpga.pdf Simon "LostSignal" <LostSignal@hotmail.com> wrote in message news:8babece3.0304181817.2f167d4f@posting.google.com... > > Does Altera officially recognize the Power On Surge problem ? > > I didn't find any references to this problem in Altera's datasheets or > > App. notes. Their datasheets don't specify start up current as well. > > One of our designs sometimes has strange power-up problems at the low > > temperature. We never attributed this problems to the FPGA. Actually I > > didn't hear about this problem before (thank you, Martin). Now I'm > > starting to suspect that the problem is related to FPGA. The design is > > based on ACEX 1K100 device. Where can I find Power On Current profile > > for this device ? > > Apparently ALL SRAM based FPGAs experience this problem to some > degree. At the startup the configuration SRAM is in unknown state and > that causes large current surge that must be satisfied in order for > FPGA to configure properly. AFAIK the differences between Xilinx and > Altera in this regard are: > 1. Xilinx publicly acknowleged this problem some time ago has several > articles on it. I have not seen much from Altera (correct me if I am > wrong). > 2. The rumor is Altera has a somewhat smaller surge and people have > less trouble with it. Dunno how true it is though. I've heard from an > Altera guy that a really large Altera part can draw 2.5 A. The maximum > current specified for Xilinx is 2 A at low temperature. Go figure.. > > Lost SignalArticle: 54821
No. Actel, Atmel, others... You deal with it. Yes. See major Mfg web sites. Look for "configuration". On Fri, 18 Apr 2003 03:16:03 GMT, "Kyle Davis" <kyledavis@nowhere.com> wrote: >Does all FPGA lost its configuration once you turn off the power? If that is >the case, how can you make a consumer product using an FPGA? Does the device >comes with its own download mechanism that will automatically download and >configure itself when the device is turned on? > >Article: 54822
Hello sir, Some doubts in PCI I will be greatful if you can clear it 1.why bus parking done only for AD,C/BE and PAR?why other signal donot need parking 2.Any idea about Prefetching???? for example Master initiate a read (burst read ,prefetech buffer 4 double word) at location 30000000 ,so data from 30000000 to 30000010 is fetched ? IS this true ? next address is whether 30000004 or 30000014? If it is 30000004 then data from 3000004 to 30000014 is fetched?Is this true? IF target side prefetch is disabled?what will happen? only one data is passed to the initiator side?Is this true? 3.what is the role of MAX_LAT in the configuration register? it is said that it specifies how often the device needs to gain access to the PCI Bus ?i didnot understand how often means what? can please give me example? 4.what is use of signal being of sustained tristate type? 5. How is cardbus specification related to PCI specification? 6. What do mean by "PCI device is embedded on the PCI bus "? 7. Why are 4 interrupt lines are provided one is enough whether it is because priority based i mean INTA has highest priority followed by INTB then INTC and INTD? 8. RST is a input in master who win reset the master? 9.what is this specific register-level programming interface in class code part of the configuration register? waiting for ur reply praveenArticle: 54823
Spam Hater wrote: > On Fri, 18 Apr 2003 03:16:03 GMT, "Kyle Davis" > <kyledavis@nowhere.com> wrote: > >>Does all FPGA lost its configuration once you turn off the power? >>If that is the case, how can you make a consumer product using an >>FPGA? Does the device comes with its own download mechanism that >>will automatically download and configure itself when the device is >>turned on? > No. Actel, Atmel, others... > You deal with it. > Yes. See major Mfg web sites. Look for "configuration". Don't forget Quicklogic, Mission Research Corporation, and Lattice. UTMC is also working on one (rebuild of Quicklogic for space applications). Of course, for initializing the FPGA, there are the device called the PROM, EEPROM, etc. -- rk, Citizen, Noooo Yawk "Sometimes when you connect the dots you get a picture. Other times you just have a bunch of dots." -- rk, January 23, 2003Article: 54824
Bill Hanna wrote: > I have been designing a Digital Signal Processor using the XC2V4000 > chip. > Software errors in ISE 4.2 and 5.1 have caused long hours of delay in > developing the design: > > Software bugs in SystemAce causes erase problems in the MPM. > Deleting signal wires in ECS causes Fatal errors that crash the > system. > A large design exceeds the 2GB memory limit and generates a fatal > memory error. > > I have designed Altera chips for over 6 years and never had a > problem. > > All digital designers should stop designing new projects with > Xilinx ICs until Xilinx corrects all software problems with ISE. > > Bill Hanna Hi, I'm not going to boycott Xilinx, since the good with them really outweighs the bad, but as an ECS (Schematic capture) user, I must admit that this tool often drives me crazy ... Xilinx's great silicon chips really deserve better tools ! I know the usual debate about schematic vs HDL, but if I'm to ever switch to HDL I'd like it to be for what they have to offer, not because the Schematic capture software is so badly designed and buggy that I can't take it anymore. Even when using HDL for blocks, I really think that schematic diagram is great for the top level of a design, because of it's inherently parallel representation, opposed to the visually sequential nature of text based HDL representations, but that's not the point here ... If I had to rank quality and code stability for ECS, it would be very close to the bottom. It regularly (3 - 10x per day) crashes (nothing to do with Windows), the best known error being the infamous "WinApp c:570:$Revision - This application has discovered an exceptional condition from which it cannot recover. Process will terminate." that still exist in the 4.2 version I use and that happens in a seemingly random pattern when moving objects around or deleting wires. Also, after moving things around, I often end up with invisible "orphean" signals that don't show up in the editor but prevent synthetisis from completing. The only way I found to recover is to go in the ".sch" file with a text editor and manually do the cleanup. Beside these gross errors (and a couple others) that should never happen (a few minutes of testing would have uncovered them), the whole editor interface is poorly designed. I could give a long list of complete examples but just a few would prove the point: - When moving / rotating / mirroring a symbol, it should not connect (glue itself like an insect trapped in a spider's net) to the lines it encounters until it's deselected. - Default option when deleting a wire should not be to delete the entire net or (optionally) segment per segment, but to delete all segments between the previous & next node (deleting the whole clock net is rarely what you want to do). - When a named net is split (eg. to add a buffer) it looks like there is no way to change the name of one of the halves without the other also being assigned the new name. The "smallest" half have to be deleted and redrawn completely. Trying to change a connection from one named net to another will rename the first one with the name of the second instead (and you won't be able to complete it anyways). Call that primitive ... - Navigation is definitely not user friendly, and a few thing could help save a lot of time, such as having more keyboard shortcuts (Numeric pad "+" & "-" to zoom in / out, a single key to pan so that the cursor position (on the editing area) becomes the center, PgUp PgDn to navigate between sheets), auto scroll when the mouse is close to an edge of the edition area (instead of being forced to do it with the scroll bars), Net name increment or decrement, should be doable using the "I" and "D" keys, etc ... Object rotation should be done using the geometric enter of the symbol, not a corner of it ! Pressing a key (such as [Alt] or [Ctrl]) while moving the mouse could scroll the schematic. Pressing the mouse left button while on an unused area should scroll the schematic diagram too. Keyboard aided net drawing would also increase productivity a lot. Example : Position the cursor where you want to start the net, press a single key (can be the "W" letter), move the mouse to the net's end position, press the same key again. This looks like a detail, but it's much faster than the current way to do it. - Taps from a named bus drawn while in net name auto increment/decrement should be automatically named from the bus it derives as they are created, instead of being given auto generated "xlxn_" names that always need to be manually renamed later. - two unrelated nets should never be allowed to merge as the result of a block move (either one of the net needs to be rerouted, or the new position should be denied) - Branch points included in an area that's being moved should be moved even if the net they belong to is not completely included in the selected block. This would prevent maze like wire shapes that must be manually edited to correct for this problem. - Editing text should be done right in the editing area. It should be possible to edit net names (instead of deleting / adding net name) - Passing the mouse over a symbol or net should display it's name in the status bar (or a "tooltip") - When printing, color should be turned to solid black, to prevent dashed lines on laser printers. - Position tolerance when connecting a net (the 4 red circles symbol) should be much bigger (except when closer connections exist) to allow faster drawing. - Etc ... ********* For the symbol library, a very welcome addition would be variable width symbols. As I see it, these symbols would be vertical duplicates of the base symbol with their non shared IOs either drawn as individual wires of buses. Example: The library defines the following symbols : - bufe - bufe4 - bufe8 - bufe16 I would see them replaced with a "bufe" symbol containing a "width" property that allows me to create a 14 bits width buffer if that's what I require (now, a bufe8 + a bufe4 + 2 bufe must be used, since using a bufe16 will result in a "bus width mismatch" error). a boolean "bus" property could be added too (to switch between multiple individual pins and bus representation). For more complex cases (Ex: a shift register), normally hidden connections could be added at the top & bottom of the symbol. When creating a dynamic width symbol, the lines that have matching "X" coordinate (when vertically stacking the individual symblol) would be connected. For the shift register example, the CLK & CLR lines would be verticals, thus connecting from base symbol to base symbol, while the D input would start from the top of the symbol, and the Q output would go to the bottom of it (with the same "X" coordinate as the "D" input on the top) thus creating a connection when they are stacked. Maybe some of these issues are solved in the new 5.2 version, and I would use it, if it was not for the risk of having many regression bugs in the middle of my current design. Such regressions when upgrading versions should be the exception, not the general rule ... I don't know how many Xilinx users actually use ECS and if peoples from the ECS development team ever read those NG posts, but I'm pretty sure other users too experience these inconveniences on a daily basis and would appreciate to see them addressed as much as I do. Also, since most new users start with schematics, pissing them off from day one with such a buggy software is probably not a wise thing to do. Hope this helps ... Eric. PS : for real email address, remove "not" & "me" ...
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