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hi, did it work?! where do you set it ? I have try to set the same thing (don't use) in the GUI constraint editor for the FPGA express, but when the design is optimze , it is map to a BUFGP. than when Translate will warning and map with error. mypin loc constraint is set in the *.ucf file. I will try it again, any other special thing that you did? Thanks *******************8here is the map report******************* Xilinx Mapping Report File for Design 'ntyGrabCompressSave' Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. Design Information ------------------ Command Line : map -p xcv1000-4-bg560 -o map.ncd grabsave.ngd grabsave.pcf Target Device : xv1000 Target Package : bg560 Target Speed : -4 Mapper Version : virtex -- C.19 Mapped Date : Fri Mar 24 18:00:49 2000 Design Summary -------------- Number of errors : 1 Number of warnings : 0 Section 1 - Errors ------------------ ERROR:xvkmm:3 - Illegal LOC on symbol "pHSync.PAD" (pad signal=pHSync) or BUFGP symbol "C2080" (output signal=pHSync_BUFGPed), IPAD-IBUFG should only be LOCed to GCLKIOB site. Section 2 - Warnings -------------------- ******************************************************** thanks spyng In article <38DF14A0.F5389447@sigma.krakow.pl>, Jaroslaw Kubica <jkubica@sigma.krakow.pl> wrote: > I had similar problem with FPGA Express and Foundation series. I've set in > Express's constraints editor Ports/Global Buffer/DONT USE for this signal. > Maybe it helps you. > Regards > Jarek > > spyng@my-deja.com wrote: > > > I am using virtex xcv 1000 from Xilinx, and foundation series for > > development. > > > > thanks > > spyng > > > > In article <38DC9ED1.61E4EBFA@sigma.krakow.pl>, > > Jaroslaw Kubica <jkubica@sigma.krakow.pl> wrote: > > > What is the type of your FPGA device and what tools do you use? > > > Regards, > > > Jarek > > > > > > spyng@my-deja.com wrote: > > > > > > > hi, > > > > > > > > other than GCK0-3, is there anyway to have a clock signal without > > > > using dedicate Pin? > > > > > > > > I need to input two external clock to my FPGA board, but > > unfortunately > > > > the board is design such that only one external clock is possible. > > > > So, i am trying to inject the second external clock to a I/O, but > > the > > > > design refuse to map. > > > > > > > > skew of the second clock is not important to me, I just want a clock > > > > in a normal I/O pin! > > > > > > > > thanks > > > > spyng > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > Before you buy. > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21651
Ray Andraka <randraka@ids.net> writes: > Rickman wrote: > > > But I think my point is still valid. I doubt that anyone would expect > > Xilinx to provide such support. It would be a far reach of the mind for > > a user to expect anyone to support the operation of tools that they did > > not provide. Again, the analogy would be like asking Intel to support > > the GNU tools. > > > > Not really, there's a fundamental difference. When you buy an intel processor, you > know exactly what it's function is and you know the chip works. With an FPGA, you > have a hardware design in there too, which from what I have seen is more often than > not a poor fit to the FPGA. That invariably generates the "you say the chips run at > XX MHz, but I can't get my design to run even at XX/10 or 20" calls. When I buy a microcontroller, its function is not determined. It can be turned to a washing machine controller or a television remote control or a talking Barbie doll or a pocket calculator or whatever. It depends on the exact bit pattern stored in its program memory. Very much like an FPGA chip, which can be turned into all sorts of things by varying the bit pattern in its program memory. The operation of a microcontroller might be more pre-defined than that of an FPGA but it is not fundamentally different. It's a piece of HW which can be turned, by means of some code, into a function-specific unit. The code or bitstream is usually derived from a higher level description of the needed functionality using CAE tools in both cases. The difference is that microcontroller vendors are quite open about the "bitstream" format. Thus, you can handcraft bitstreams if you like and you also have a choice of tools. FPGA vendors chose to lock all the doors and limit your choice of tools and ways when determining the final function of their chips. I think it is more of a cultural issue than a technical one. FPGAs are descendants of ASICs where closed doors are normal, so are expensive tools, support engineers at your site and so on. FPGAs were born with an infrastructure, that is, the tools and the computers that run them were already in existence. It started that way and it remained that way. The CPU world was born without the infrastructure, there were no computers on every engineer's desk for there were no processors to build them from and thus the vendor *had* to give away all the info to make it possible for the customer to hand-assemble the code and burn it into those HUGE 2KB PROMs. It just became the norm that with a CPU you get the instruction encoding info together with anything else that may or may not be relevant to your design. It become also customary that you get the tools wherever you want to, the vendor delivers you chips. If they offer you a compiler then it is just a courtesy act. On the other hand, they don't support you if you have software problems, and that's the way it should be, IMHO. They guarantee that the silicon does whatever they said it would, how do you create the bitstream is out of their domain. FPGA vendors apparently say that they must support everything on Earth that can generate a bitstream for their chips and thus it is just economical to keep the number of such things on the absolute minimum. That's their decision, it is not a law of nature in my opinion. They differ from the processor bunch because they want to differ and not because they are inherently different. If Intel says that "The Pentium XYZ can do a 3D mapping in software in less than N us" and you write some surface mapping using the "Graphics algoritms for dummies" textbook, compile with a compiler you rolled yourself, and it's just dog slow, would you go to Intel screaming ? No. If the FPGA databook says that the chip is capable of 250MHz 16 bit sync counting and you create a bitstream with some home made tools compiling your counter from "The idiot's guide to logic design" e4xamples section and your counter can't do more than 10MHz, I'd say you have no more ground to call the FPGA support than you had to call Intel. With some exageration, instead of saying that you can call them if you have problems with *their* FPGA tools, they act generously and say that you can call them if you have any problem with any FPGA tool. Of course, they first make sure that there could not possibly be any other tool ... Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 21652
Hi,
I have the following problem: when I choose Trim
unconected logic in Xilinx alliance 1.5i it trims one of 8
registers off. When I unselect Trim unc.log. I get the
following error:
FATAL_ERROR:x4kma:x4kmaiob.c:696:1.117 - Illegal parallel
signal configuration detected in iobfillin() for signal
[565] and IOB [1309] Process will terminate. Please call
Xilinx support.
Here'a also the code:
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity reg_32x4 is
port (clock :in std_logic;
reset :in std_logic;
RF_re1 :in std_logic;
RF_re2 :in std_logic;
RF_we :in std_logic;
RF_addr1 :in std_logic_vector(1 downto 0);
RF_addr2 :in std_logic_vector(1 downto 0);
RF_dest :in std_logic_vector(1 downto 0);
RF_in :in std_logic_vector(31 downto 0);
RF_out1 :out std_logic_vector(31 downto 0);
RF_out2 :out std_logic_vector(31 downto 0));
end reg_32x4;
architecture RTL of reg_32x4 is
component reg_32
port (clock :in std_logic;
reset :in std_logic;
REG_we :in std_logic;
REG_in :in std_logic_vector(31 downto 0);
REG_out :out std_logic_vector(31 downto 0));
end component;
type control_we is array (3 downto 0) of std_logic;
signal regs_we:control_we;
type reg_file is array (3 downto 0) of std_logic_vector(31 downto 0);
signal data_A,data_B:reg_file;
begin
-- this register file uses double register configuration, so two operands
-- can be fetched in one clock cycle. so for every register there are
-- acctually two registers implemented. output ports are tri stated
GREGA:for i in 3 downto 0 generate
REG_A:reg_32 port map(clock,reset,regs_we(i),RF_in,data_A(i));
end generate GREGA;
GREGB:for i in 3 downto 0 generate
REG_B:reg_32 port map(clock,reset,regs_we(i),RF_in,data_B(i));
end generate GREGB;
RF_out1<=data_A(0) when RF_re1='0' and RF_addr1="00" else
data_A(1) when RF_re1='0' and RF_addr1="01" else
data_A(2) when RF_re1='0' and RF_addr1="10" else
data_A(3) when RF_re1='0' and RF_addr1="11" else
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
RF_out2<=data_B(0) when RF_re2='0' and RF_addr2="00" else
data_B(1) when RF_re2='0' and RF_addr2="01" else
data_B(2) when RF_re2='0' and RF_addr2="10" else
data_B(3) when RF_re2='0' and RF_addr2="11" else
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
--if write enable = 1 and the right address, write to the register
regs_we(0)<='1' when RF_dest="00" and RF_we='1' else '0';
regs_we(1)<='1' when RF_dest="01" and RF_we='1' else '0';
regs_we(2)<='1' when RF_dest="10" and RF_we='1' else '0';
regs_we(3)<='1' when RF_dest="11" and RF_we='1' else '0';
end RTL;
---------------------------------------------------------------------------
Can anyone help?
Thanks.
-------------------------------------------
- Domagoj -
- Domagoj@engineer.com -
-------------------------------------------
Article: 21653
Ray Andraka wrote:
> Kate,
>
> The configuration 'SRAM' in SRAM based FPGAs is not what you would normally
> consider an SRAM cell, rather it is a D register that is considerably more
> robust than the D registers in your design and orders of magnitude more robust
> than the SRAM hanging off the microprocessor. The readback capability can be
> exploited to effect a continuous non-invasive health monitoring so that a reload
> can be done when the configuration does get upset. I've got a current Virtex
> design that will be going into space in a year or two.
Some general babble, responding to some comments in a variety of posts.
Here's some data, from Los Alamos National Labs, presented at MAPLD 1999, for Virtex
devices:
LETth Saturated X-Sec
MeV-cm^2/mg cm^2/bit
CLB 5.0 6.5 x 10^-8
LUT 1.8 21.0 x 10^-8
BRAM 1.2 16.0 x 10^-8
The data for the XQR4000XL series (Lockheed-Martin took the data) is not that
different from that above. Looking at the curve, it appears that the Virtex has a
smaller cross-section per bit.
For these parameters (for those not familiar with them) a high LET threshold is
desirable. All of these values are considered low and make the devices susceptible
to upsets by protons, a threat in low earth orbits. The saturated cross-sections
are relatively low per bit for a commercial/military grade device (good); note that
one must multiply this by the number of bits to get the device cross-section. Of
course, similar to the analysis of processors, upsets in some bits may simply be a
don't care or be of no significance to either function or reliability; estimating
that accurately is difficult but these numbers could serve as an upper bound. Upset
rates would be dependent on where one is flying and the space weather. In general,
for a device in this class of hardness and size, it would be assumed that upsets
would be a rather common occurrence and one of the variety of methods for dealing
with this would be used. The suitability of a particular method would be dependent
on the application, the system design, and various reliability requirements. These
vary all over the place so no general statement could be made.
----------------------------------------------------------------------
rk History will remember the twentieth
stellar engineering, ltd. century for two technological
stellare@erols.com.NOSPAM developments: atomic energy and
Hi-Rel Digital Systems Design space flight. -- Neil Armstrong, 1994
Article: 21654Greg Neff wrote: > I'm not an expert in this area, but I do have some experience. Mission > critical fly-by-wire avionics systems that I have been involved with > are triplicated (i.e. three identical systems), with 2 out of 3 voting > at the actuator level. > > In my experience, single redundancy is not generally considered to be > acceptable, since you get into a situation where you don't know which > of the two systems to trust. Also, you have to do a thorough FMEA > (failure modes and effects analysis) to understand what can happen, and > you have to identify and eliminate latent failure modes. > > Again, my experience is with transportation and avionics, and not with > space systems. I can imagine that the size, weight, and power > restrictions could make redundant systems impractical. However, if > your spec says that you have to tolerate any one single point of > failure, then you may not have a choice. Perhaps a bit of trivia, perhaps a bit interesting: For the Saturn V rocket, much of the logic was TMR and voted; there was also logic in place to see if there was any disagreement to aid in the detection of the faulty hardware prior to launch. The memories were dual-redundant, however, with parity. If there was an error, then the backup memory's data was used, the erroneous data re-written, and the backup memory switched to be the prime unit. This was cheaper then TMR and still provided error-free, continuous operation, a requirement for that application. rkArticle: 21655
Has any one started asking Reconfigurable Computer Company want-a-bees how they generate their bitstreams ? http://www.starbridgesystems.com/ So, Star Bridge Systems, did you sign a NDA to make your Viva software generate bitstreams for the current XLA 4062-8 and future Xilinx Virtex E 440000 ? Ray Andraka wrote: > > Rickman wrote: > > > > One area that Atmel may be very interested in supporting open source > > tools in is finding ways to design partial configuration... > You might look at Mike Wirthlin's (BYU) Dynamic Instruction Set and other Open Source FPGA tool discussions on Comp.Arch.FPGA -- real people - remove my First and Last name (Mike- -Ferr) off of the ends of my amateur call sign (n2kra)Article: 21656
Greg Neff wrote: > > how do you make sure that the voting circuits for 2 out 3 > > work 100% of the time? > (snip) > BTW, diversity has not been used in systems that I have seen. The > argument for diversity is that it compensates for latent failure modes, > such as software bugs. The argument against diversity is that it is > more practical to design and thoroughly V&V one system, than to design > and V&V three diverse systems that have to work together in a redundant > configuration. The one example of a system with diversity that I am aware of is the Space Shuttle's main computer system. It consists of 5 computers, with identical hardware. The software, however, is identical on the 4 computers that actually do the work. A fifth computer, running but not controlling the vehicle unless commanded to, runs software developed by a completely independent team. Anyone else know of any other examples? Have a good evening, rkArticle: 21657
Kate Atkins wrote: > surely you wouldn't use SRAM based FPGA on space equipment? SEU in the > configuration RAM could completely change the operation of the design, > an input buffer could turn into an output buffer! > > You could consider having two FPGAs, just one powered at any one time. > Open collector buffers on outputs (eg LS05 powered off/on with associated > FPGA), series resistors on inputs to limit current seen by input protection > diodes of the powered off FPGA. > > If you also have to consider SEU Synplicity has an application note on "safe > statemachines" and one on using Actels rad hard FPGAs. > > I believe Actel have one or two of the RT54SX family due with SEU hardened > registers. I believe those devices will end in an 'S' suffix and also feature cold-sparing, amongst other features, if I remember correctly. Those LS05's sure eat up power. And the FPGA union will get after you for using a discrete logic element! For low-speed signals, don't forget the CD4049UB and the CD4050B, as long as we're talking about antique logic families. It'll be interesting to see how the hardened registers work out. Seriously, there are some more modern alternatives now, cold-sparing buffers, for space. UTMC makes them and I believe so does Allied-Signal. Cheers, rkArticle: 21658
rk wrote: > I believe those devices will end in an 'S' suffix and also feature cold-sparing, > amongst other features, if I remember correctly. Those LS05's sure eat up > power. And the FPGA union will get after you for using a discrete logic > element! For low-speed signals, don't forget the CD4049UB and the CD4050B, as > long as we're talking about antique logic families. It'll be interesting to see > how the hardened registers work out. > A few years back I remember reading on a logic family - a few gates and registers that used a modified transistor schmit trigger logic to give about 5 volts of margin on switching levels, when run from 12 volts. Being bipolar you did not have the cmos latch up problem. This was not a low power logic as it was ment for industrial sites, with a lot of noise. I think it was used in 747's. Ben. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." The Lagging edge of technology: http://www.jetnet.ab.ca/users/bfranchuk/woodelf/index.htmlArticle: 21659
In Xilinx booth in DAC, you guys didn't give any demo for those who work for competing company. Should I say shame on you, Xilinx? HT - not an Atmel employee Peter Alfke wrote: > > From my computer here at Xilinx, I can access all sorts of > semiconductor websites. > It's a joy. > I have Intel, AMD, National, Altera, Quicklogic, Actel, Cyprus at my > fingertips. > But not Atmel. > I get: > > Forbidden > > You don't have permission to access / on this server. > > Apache/1.3.9 Server at www.atmel.com Port 80 > > Shame on you, Atmel ! What are you afraid of ? > > Peter AlfkeArticle: 21660
hi, I didn't do anything more. 1st disable "Skip constraint entry" in "Create Implementation" window in FPGA Express, 2nd create implementation 3rd edit constraint - disable Global Buffer for pHSync 4th optimize chip and export netlist 5th load netlist into Xilinx Design Menager and implement using your .ucf file for pins assignment and timing optimization Its all. Regards, Jarek spyng@my-deja.com wrote: > hi, > did it work?! where do you set it ? > > I have try to set the same thing (don't use) in the GUI constraint > editor for the FPGA express, but when the design is optimze , it is map > to a BUFGP. > than when Translate will warning and map with error. > mypin loc constraint is set in the *.ucf file. > > I will try it again, any other special thing that you did? Thanks > > *******************8here is the map report******************* > > Xilinx Mapping Report File for Design 'ntyGrabCompressSave' > Copyright (c) 1995-1999 Xilinx, Inc. All rights reserved. > > Design Information > ------------------ > Command Line : map -p xcv1000-4-bg560 -o map.ncd grabsave.ngd > grabsave.pcf > Target Device : xv1000 > Target Package : bg560 > Target Speed : -4 > Mapper Version : virtex -- C.19 > Mapped Date : Fri Mar 24 18:00:49 2000 > > Design Summary > -------------- > Number of errors : 1 > Number of warnings : 0 > > Section 1 - Errors > ------------------ > ERROR:xvkmm:3 - Illegal LOC on symbol "pHSync.PAD" (pad signal=pHSync) > or BUFGP > symbol "C2080" (output signal=pHSync_BUFGPed), IPAD-IBUFG should only > be > LOCed to GCLKIOB site. > > Section 2 - Warnings > -------------------- > > ******************************************************** > > thanks > spyng > > In article <38DF14A0.F5389447@sigma.krakow.pl>, > Jaroslaw Kubica <jkubica@sigma.krakow.pl> wrote: > > I had similar problem with FPGA Express and Foundation series. I've > set in > > Express's constraints editor Ports/Global Buffer/DONT USE for this > signal. > > Maybe it helps you. > > Regards > > Jarek > > > > spyng@my-deja.com wrote: > > > > > I am using virtex xcv 1000 from Xilinx, and foundation series for > > > development. > > > > > > thanks > > > spyng > > > > > > In article <38DC9ED1.61E4EBFA@sigma.krakow.pl>, > > > Jaroslaw Kubica <jkubica@sigma.krakow.pl> wrote: > > > > What is the type of your FPGA device and what tools do you use? > > > > Regards, > > > > Jarek > > > > > > > > spyng@my-deja.com wrote: > > > > > > > > > hi, > > > > > > > > > > other than GCK0-3, is there anyway to have a clock signal > without > > > > > using dedicate Pin? > > > > > > > > > > I need to input two external clock to my FPGA board, but > > > unfortunately > > > > > the board is design such that only one external clock is > possible. > > > > > So, i am trying to inject the second external clock to a I/O, > but > > > the > > > > > design refuse to map. > > > > > > > > > > skew of the second clock is not important to me, I just want a > clock > > > > > in a normal I/O pin! > > > > > > > > > > thanks > > > > > spyng > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > > > Before you buy. > > > > > > > > > > > > > > Sent via Deja.com http://www.deja.com/ > > > Before you buy. > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 21661
Anyone have any good sugestions on a good book/internet site on information on Digital filter design?? Thanks, Stan Ramsden Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21662
Hi Jamie: You might try using xdl. This is a tool that converts NCD files to and from XDL (an ASCII) format. You should be able to find it in $XILINX/userware/bin/<platform>. If not, send e-mail to xdl_support@xilinx.com. As a matter of fact, you may want to send e-mail anyways because a new version was released recently. Good luck, Joe Jamie Sanderson <jamie@nortelnetworks.com> wrote in message news:8bg1mu$8j8$1@bcarh8ab.ca.nortel.com... > Greetings; > > There are a few things I'd like to do with Xilinx FPGA's (xc4000 or xcv/e). > However, I think they could both be implemented in similar ways. > > First of all, I'd like to have a version/revision value within the FPGA > which would automatically track the one used in the Design Manager. > > The second thing I want is to generate multiple bit files from a single one, > each of those files containing a unique identifier. > > JBits seems like a potential candidate, but it's not particularly available. > Another possibility is the FPGA editor, but I don't believe you can run it > non-interactively. > > Any ideas? For the first case, what I'd envision would be a black box which > could be instantiated into your code. It would have version and revision > outputs which match what is given in Design Manager. I wouldn't expect it to > simulate properly, but that's a minor issue. In the second case, the same > black box could be manipulated by an executable which you run on your bit > file, and which you provide the identifiers you require. > > Thanks for reading this! > > Cheers, > Jamie > >Article: 21663
I just wanted to thank everyone for the helpful suggestions. What I'm
hearing doesn't particularly fill me with hope, but they are good solutions
nonetheless. My next move will be to contact Xilinx and see whether or not
they wouldn't be willing to give the problem to one of their people. I'll be
sure to post my progress here.
Best regards,
Jamie
<eml@riverside-machines.com.NOSPAM> wrote in message
news:38dc9056.269070770@news.dial.pipex.com...
> I'd like to do this as well, so it would be interesting to hear how
> you get on. I can't see that you'll get the GUI version/revision info
> though, since this is just private to the GUI. Why don't you just
> maintain a revision register in your device? Your problem then is just
> identifying this register, or the serial number register, in the
> bitfile.
>
> I haven't looked at Jbits but, if it doesn't do the job, this
> procedure might work. Have a 16-bit revision number implemented as a
> CLB ROM element, and locate this ROM at a known CLB location. Generate
> an 'll' file from Bitgen ('-l' option). Search the ll file for lines
> containing your known CLB location (the ll format is documented in the
> file). This will give you the bit number, frame number, and frame
> offset for all 16 bits in your ID. The trick now is to identify these
> bits in your bitfile; see xapps 138 and/or 151.
>
> As an aside, this is what I do to get around the Xilinx GUI
> revision/version structure. My rebuild makefile always builds in a
> fixed directory (xproj/current in my setup), and you rely on a source
> control system to retrieve the important files (only) from previous
> builds. You then don't need multiple directories to keep a huge amount
> of redundant information.
>
> Evan
>
Article: 21664Does anyone know how to add the DLL properties (eg. CLKDV_DIVIDE, STARTUP_WAIT, etc) to the Xilinx CLKDLL primitives in VHDL, Verilog & Foundation schematics or does it have to be done in the UCF file? thanks in advance, Mark.Article: 21665
Stan, For the theory, try www.bores.com and www.dspguru.com. Once you figure out what how the filter works, you might look at the distributed artihmetic page on my webstie if you are planning to implement it in an FPGA. sramsden@my-deja.com wrote: > Anyone have any good sugestions on a good > book/internet site on information on Digital > filter design?? > Thanks, > Stan Ramsden > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21666
In article <M_4E4.29715$pn3.359479@news.infostrada.it>, "Mark Harvey" <mark.harvey@iol.it> wrote: > Does anyone know how to add the DLL properties (eg. CLKDV_DIVIDE, > STARTUP_WAIT, etc) to the Xilinx CLKDLL primitives in VHDL, Verilog & > Foundation schematics or does it have to be done in the UCF file? > > thanks in advance, > > Mark. > > Look in the unisim_VITAL.vhd file for the clkdll entity. They show the properties as generics. This is for your VHDL implementation. You will notice that the STARTUP_WAIT property is not listed there. Xilinx has yet to implement that feature in their model. I spoke with them about it, and they realize that it needs to be added. Until then, you'll have to monitor the LOCK signal and use it to trigger releasing of GSR in your simulation. I believe you will find all the other properties though. Hope this helps. chad Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21667
I am not familar with the Spartan devices, but I can tell you that the JTAG approach is not new. The Xilinx devices have been JTAG configurable for several years now. As far as complexity goes, the JTAG method of programming is more complicated than the serial slave, from the controller's point of view. But, it is a much more general approach, which can be used for lots of different vendors. If you have a single controller that will be reused in future designs, and you are using or planning on using various devices (xilinx, vantis, altera, ...) then the better long-term solution for you may be the JTAG method. But for the short-term, the easiest way to program the controller to load the part would be the serial slave mode. chad In article <puvC4.33771$pA.109618@typhoon.mbnet.mb.ca>, "Steve" <reply.through.newsgroup@paranoid.com> wrote: > Given a system with an embedded processor to do the work, what > are the pros and cons of the classic Xilinx Slave serial mode vs the > newer JTAG approach. Do the SpartanXL (and the SpartanII) > parts support both approaches equally well? > > Steve > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21668
In article <38E01B5D.9EBC46FD@nospam.erols.com>, rk <stellare@nospam.erols.com> writes: |> Here's some data, from Los Alamos National Labs, presented at MAPLD 1999, for Virtex |> devices: |> LETth Saturated X-Sec |> MeV-cm^2/mg cm^2/bit |> CLB 5.0 6.5 x 10^-8 |> LUT 1.8 21.0 x 10^-8 |> BRAM 1.2 16.0 x 10^-8 Thanks for posting this data. Were there any threshold LET values for latchup presented? Latchup can be a more severe threat in the sense that it can complicate the board-level and power supply design issues. Of course, you can't use TMR within a single FPGA to avoid latchup, either...but I suspect that you know this already. Can you give me a bit more of a reference for this paper so I can try to get ahold of a copy? Thanks, Joe -- --------------------------------------------------------------------------- == K. Joseph Hass == Microelectronics Research Center == == http://www.mrc.unm.edu/~jhass == 801 University Blvd SE, Suite 206 == == (505) 272-7055 == Albuquerque, NM 87106-4340 USA ==Article: 21669
Test: Please ignore...Article: 21670
The paper's at http://www.xilinx.com/appnotes/VtxTest.pdf (link found on http://www.xilinx.com/products/hirel_qml.htm#Radiation_Hardened ) regards, tom Joe Hass wrote: > > Can you give me a bit more of a reference for this paper so I can try > to get ahold of a copy? > > Thanks, > Joe Tom Burgess -- Digital Engineer National Research Council of Canada P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.caArticle: 21671
I have recently tried coregen for the first time, and keep getting java errors and internal errors. I tried on 2 NT SP6 machines and one Windows 2000 machine. I've just been told that there might be a problem with SP6. Has anyone else seen this? SteveArticle: 21672
Joe Hass wrote:
> In article <38E01B5D.9EBC46FD@nospam.erols.com>,
> rk <stellare@nospam.erols.com> writes:
> |> Here's some data, from Los Alamos National Labs, presented at MAPLD 1999, for Virtex
> |> devices:
> |> LETth Saturated X-Sec
> |> MeV-cm^2/mg cm^2/bit
> |> CLB 5.0 6.5 x 10^-8
> |> LUT 1.8 21.0 x 10^-8
> |> BRAM 1.2 16.0 x 10^-8
>
> Thanks for posting this data. Were there any threshold LET values for
> latchup presented? Latchup can be a more severe threat in the sense
> that it can complicate the board-level and power supply design issues.
> Of course, you can't use TMR within a single FPGA to avoid latchup,
> either...but I suspect that you know this already.
Latchup was not detected in the Virtex device (with epi layer, modifed from the commercial
device, if I remember correctly). It was also not detected in the specially processed
XQR4000XL series. The values tested were pretty high, with the Virtex tested to 125
MeV-cm^2/mg, making SEL not a problem. The XQR4036XL, modified to have a 7 um epi layer
[again, if gray cells are working correctly], was not observed to latch up to an effective
LET of 110 MeV-cm^2/mg, again, not a problem. And yes, SEL is independent of various
logic-level error-correction techniques such as TMR.
> Can you give me a bit more of a reference for this paper so I can try
> to get ahold of a copy?
The Virtex paper reference:
"Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable
Computing," Earl Fuller, Phil Blain, Michael Caffrey, Carl Carmichael, Noor Khalsa,
and Anthony Salazar, Military and Aerospace Applications of Programmable Devices and
Technologies Conference, 1999.
That paper is not yet available on the conference www site but can be downloaded
from Xilinx' site at:
http://www.xilinx.com/appnotes/VtxTest.pdf
A reference on the XQR4000XL series:
"Radiation Tolerance of High-Density FPGAs," Peter Alfke and Rick Padovani, Military
and Aerospace Applications of Programmable Devices and Technologies Conference, 1998.
http://rk.gsfc.nasa.gov/richcontent/Ksymposium/Papers/B6_Alfke.pdf
> Thanks,
> Joe
No problem, there's a lot of information out there,
Have a good day,
rk
Article: 21673rk <stellare@nospam.erols.com> writes: > Greg Neff wrote: > > > > how do you make sure that the voting circuits for 2 out 3 > > > work 100% of the time? > > (snip) > > BTW, diversity has not been used in systems that I have seen. The > > argument for diversity is that it compensates for latent failure modes, > > such as software bugs. The argument against diversity is that it is > > more practical to design and thoroughly V&V one system, than to design > > and V&V three diverse systems that have to work together in a redundant > > configuration. > > The one example of a system with diversity that I am aware of is the Space > Shuttle's main computer system. It consists of 5 computers, with identical > hardware. The software, however, is identical on the 4 computers that > actually do the work. A fifth computer, running but not controlling the > vehicle unless commanded to, runs software developed by a completely > independent team. > > Anyone else know of any other examples? [Rumours] Wasn't the Ariane 5 suppsoed to have different SW for some controlling functions, but they run out of time, and didn't implement it. The results are known. [End Rumours] Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 21674
In article <MPG.134999387baccd2298970d@ausnews.austin.ibm.com>, iachetta@us.ibm.com says... > Another example: > > if (a == 1) > bus = y; > else if (b == 0) > bus = z; > else bus = 0; > > What if b=X whenever a = 1? The RTL will always evaluate to bus = y > because b is a don't care when a = 1. But the gatelevel bus will most > likely (depending upon which gates exactly create the logic) equal X. One more thing. You can get this kind of behavior with continuous assignment statements also: assign y = a | (b & c & (state == 3'b010)); If state = 3'b0X0, you won't get an X on y unless a=0 and both b and c are 1. Otherwise, y will produce the correct result in RTL sim. But in gate level sim, you are much more likely to see y go to X when state = 3'b0X0; -- Rich Iachetta iachetta@us.ibm.com I do not speak for IBM.
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