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Mine was not a cry for help, it was a cry of outrage. Hell, I used to exchange printed data books with Altera, while our two companies are not the best of friends ... Why make life difficult for each other when there are well-travelled ways around any such obstacle. To think that anybody can be so dumb, trying to restrain access to a website, and hope that will keep out the competition... If its on the web, it's public. Peter Alfke ===================== Larry Doolittle wrote: > So look at them from home, or use a redirector service > like www.anonymiser.com. > > - Larry Doolittle <LRDoolittle@lbl.gov>Article: 21276
I am using ModelSim to simulate my design and encounter the following warning message "Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand!"on my microprocessor bus when they are tristated. Is there anyway to simulate a weak pull-up in my testbench to remove this warning other than turn on the Ignore assertion on warning within ModelSim? SherdynArticle: 21277
What is the difference between FPGA, PLD, CPLD ? they are all programmable chip. what is different ?Article: 21278
Scott Campbell wrote: > Well, the good news is that Boulder can still access the sight. You.... What a wonderful blunder! So Atmel's site is a sight? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21279
Naw, "goofy" is a metastable state caused by looming deadlines :-) All I meant was that if it is a straight D flop it'll go in fine. If you do anything that needs the output fedback (like a JK implementation if anyone still does such silly things --I know youz guys are out there, I keep finding your designs), it won't automagically push into the IOB. Andy Peters wrote: > Rickman wrote in message <38CEA92E.E3A21A45@yahoo.com>... > >Ray Andraka wrote: > >> > >> In your design, just use a regular D flip-flop. Don't put any > >> combinatorial logic in front of it (this isn't absolutely necessary, but > >> it makes it easier to meet timing) and don't drive anything other than > >> the one tristate control with it. When compiling the design turn on the > >> use-IOB flip-flops option in the mapper. That will push the flip-flop > >> into the IOB as long as there is nothing goofy with it. > > > >Ok, I give up. How do I know if the FF is "goofy". ;-) > > They get that way when you slip them a Mickey. > > -- a > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) noao \dot\ edu > > "Money is property; it is not speech." > -- Justice John Paul Stevens -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21280
What's the difference between a golf cart and a cadillac? They are both motorized vehicles.... CPLD is like a handful of PLDs connected by a switch matrix in one chip. FPGAs are a completely different structure. JaeYong Kim wrote: > What is the difference between FPGA, PLD, CPLD ? > they are all programmable chip. what is different ? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21281
Ray Andraka wrote:
> Naw, "goofy" is a metastable state caused by looming deadlines :-)
>
> All I meant was that if it is a straight D flop it'll go in fine. If you do
> anything that needs the output fedback (like a JK implementation if anyone
> still does such silly things --I know youz guys are out there, I keep finding
> your designs), it won't automagically push into the IOB.
AFAIK for Virtex the rules for an IOB push on the Tri-FF are:
(1) common clock with the In/Out-FFs [obvious].
(2) common initialisation signal. Whether this is set/reset & sync/async is
independent. This is a problem
if e.g. some of the IOB FFs use an init signal & some don't.
(3) No feedback to any other logic from the output.
(4) Tri-FF controls only one output. It would be really nice if a register
controlling the tristate on a bus
was automatically fanned out into the IOBs.
One thing has never been clear to me & after > 1 yr of trying to get the info
I've given up:
Question: If, due to the restrictions 1-4 above, some but not all of the FFs on a
registered inout can be pushed into an IOB *** what is the priority ?***.
Article: 21282On Wed, 15 Mar 2000 06:29:03 GMT, Ray Andraka <randraka@ids.net> wrote: >Naw, "goofy" is a metastable state caused by looming deadlines :-) > >All I meant was that if it is a straight D flop it'll go in fine. If you do >anything that needs the output fedback (like a JK implementation if anyone >still does such silly things --I know youz guys are out there, I keep finding >your designs), it won't automagically push into the IOB. Another gotcha: if you're trying to push an input or an output reg into the same IOB, make sure that everything shares the same SR signal. This may sound obvious, but it's impossible if (a) you're relying on a synthesiser, (b) you've got a high fanout signal on the reset, and (c) the synth doesn't give you the control to prevent duplication/splitting of high fanout signals, in which case you may end up with different nets to the 2 or 3 SRs in the IOB, which won't work. Do you/does anybody know if Synplify gives you this control? EvanArticle: 21283
On Tue, 14 Mar 2000 12:31:29 +0100, Guido Pohl <pohl@fokus.gmd.de>
wrote:
>Hallo and a Good Day,
>
>I have the following solution (?) for a problem, but I cannot estimate its
>implications.
>
>Ok, there is a registered signal "withinReadCycle" that is asserted at the start
>of a read cycle , i.e. by a certain condition (see below "condition1")
>sunchronously to clock edge. The signal should be left asserted as long as
>another condition ("condition2") does not occure. But when the condition occures
>I would like to de-assert the signal "withinReadCycle" as quick as possible,
>that is I don't want to wait for the rising clock edge - which certainly means
>that I asynchronously de-assert that signal.
>
>I would code that as follows in VHDL:
>
>
> read_regs: PROCESS (CLKxCI, RSTxRLI)
> BEGIN -- PROCESS read_regs
> IF RSTxRLI = '0' THEN -- asynchronous reset (active low)
> withinReadCycle <= '0';
>
> ELSIF (condition2 = '1') THEN
> withinReadCycle <= '0';
>
> ELSIF CLKxCI'event AND CLKxCI = '1' THEN -- rising clock edge
>
> IF ( condition1 = '1' OR withinReadCycle = '1' ) THEN
>
> withinReadCycle = '1';
> bla;
>
> ELSIF ( condition1 = '0' ) THEN
>
> withinReadCycle <= '0';
>
> END IF;
>
> END IF;
> END PROCESS read_regs;
>
>
>
>And now, my questions:
>
>(1) Is there a chance to be able to synthesize that code?
Yes, but I'd clean up the code to make the asynchronous reset more
obvious:
BEGIN -- PROCESS read_regs
IF (RSTxRLI = '0') or (condition2 = '1') THEN
withinReadCycle <= '0';
However, your statement 'bla' is potentially a problem. You should (a)
only be assigning to 'withinReadCycle' in your process, or (b) if
you're assigning to another signal as well, make sure you assign to it
in every branch of the if statement.
>(2) The device for which to synthesize must have a product-term-driven reset,
>right?
If you're targetting a PAL, yes; you don't have to worry about this in
an FPGA
>(3) In case that (1) can be answered with yes, would there be success for a
>Xilinx4036?
Yes, with the proviso above.
Evan
Article: 21284On Wed, 15 Mar 2000 06:31:42 GMT, Ray Andraka <randraka@ids.net> wrote: >What's the difference between a golf cart and a cadillac? They are both >motorized vehicles.... Not sure - we don't get Cadillacs here. Is it that you can't drive a golf cart on a highway? EvanArticle: 21285
Hi, who know the detail of how to use mode 4 (synchronous RAM) in Atmel's AT40K series? I am doing some work about dynamically reconfiguration. This serie seems suitable to my requirement ( partial reconfiguration, fast), but I've got no detail from Atmel's website. Another question, who have ever used Xilinx's JBit API? Don't I really need synthesis tool if I use it? Regards, BennetArticle: 21286
JaeYong Kim <jaelong@lge.co.kr> wrote in message news:006ucssuqv358olp893qesagof13ar5oue@4ax.com... > What is the difference between FPGA, PLD, CPLD ? > they are all programmable chip. what is different ? > FPGA - Field Programmable Gate Array - uses SRAM to achieve simple logic functions and then interconnects these simple logic functions to generate much more complex functions. A 4 bit SRAM memory would need 2 address lines and one data line. If the address:data stored was 00:0 01:0 10:0 11:1 the function being mimicked would be a 2 input AND. Similarly if the address:data stored was 00:0 01:1 10:1 11:1 a 2 input OR would be realised. Cascade several of these basic cells, and larger functions can be realised. Add some registers as well and it is possible to pipeline data changes and form synchronous state machines etc. The Xilinx Virtex and Spartan devices and Altera Flex devices are examples of FPGAs. PLD - Programmable Logic Devices - use arrays of AND gates followed by OR gates. For example the 22V10 device has many wide input AND gates for up to 22 inputs. The output of these AND gates can be selectively routed to wide input OR gates, so if a logic function can be described in AND/OR notation, it could be implemented in a PLD. They can also contain registers. CPLD - Complex Programmable Logic Devices - connect several PLD arrays as described above together by a switch matrix allowing even larger logic functions to be realised. Lattice ISP devices and Vantis MACH devices are examples of CPLDs. Hope That Helps (HTH) DavidArticle: 21287
David Frith <david.frith@ffei.co.uk> wrote in message news:8ao2dv$2kf@isgsrv1.hh.ffei.co.uk... > JaeYong Kim <jaelong@lge.co.kr> wrote in message > news:006ucssuqv358olp893qesagof13ar5oue@4ax.com... > > What is the difference between FPGA, PLD, CPLD ? > > they are all programmable chip. what is different ? > > Neglected to say that the interconnects in an FPGA are usually switched by storing a '1' or a '0' in an SRAM cell whilst in a CPLD they are controlled by a made or blown fuse (which may or may not be electrically erase-able). FPGA's need their SRAMs loading each time they are powered-up (called configuration) whilst CPLDs keep their program even when powered off. There are advantages and disadvantages of both ways of doing things. DavidArticle: 21288
eml@riverside-machines.com.NOSPAM wrote:
Do you/does anybody know if Synplify gives you this control?
It does give you this control - all you have to do is set the ``syn_maxfan''
attribute for the net to something huge to prevent splitting/duplication. Its
probably worth putting a ``syn_preserve'' or ``syn_keep'' on the reg/wire
driving the reset line.
BUT ....
There is another problem with Synplify. Even if you haven't put an SR control on a
FF in the HDL source you might get one anyway since Synplify will use a the
_synchronous_ set/reset input of a Xilinx FF as a free ``or/and'' gate! e.g. if
your code looks something like this:
always @(posedge clk)
out <= d_in & !foo;
then post optimisation & mapping you'll very likely get this in the netlist:
FDR inst_name (.Q(out), .C(clk), .D(d_in), .R(foo));
Its even worse since you don't actually know which way round it will assign the
D,R inputs. If there are inverted
versions of d_in & foo available you might get:
FDR inst_name (.Q(out), .C(clk), .D(~foo), .R(~d_in));
To get around this you need to make sure that FF's destined for IOBs are fed from
wires with a syn_keep attribute:
wire temp /*synthesis syn_keep=1 */;
assign temp = d_in & !foo;
always @(posedge clk)
out <= temp;
Article: 21289Hi, as far as I know, the mode 4 documentation is available under a NDA. Contact Atmel to get more informations. Riad Bingfeng Mei a écrit : > Hi, who know the detail of how to use mode 4 (synchronous RAM) in > Atmel's AT40K series? I am doing some work about dynamically > reconfiguration. This serie seems suitable to my requirement ( partial > reconfiguration, fast), but I've got no detail from Atmel's website. > Another question, who have ever used Xilinx's JBit API? Don't I really > need synthesis tool if I use it? > > Regards, > BennetArticle: 21290
David Frith wrote: > JaeYong Kim <jaelong@lge.co.kr> wrote in message > news:006ucssuqv358olp893qesagof13ar5oue@4ax.com... > > What is the difference between FPGA, PLD, CPLD ? > > they are all programmable chip. what is different ? > > > > FPGA - Field Programmable Gate Array - uses SRAM to achieve simple logic > functions and then interconnects these simple logic functions to generate > much more complex functions. A 4 bit SRAM memory would need 2 address lines > and one data line. If the address:data stored was > 00:0 > 01:0 > 10:0 > 11:1 > the function being mimicked would be a 2 input AND. Similarly if the > address:data stored was Not an easy question but I must disagree with your definition. For example, using SRAM-based LUTs is most definitely not a requirement for an FPGA. There are numerous manufacturers who don't use SRAM LUTs. For the non-reprogrogrammable types, there are the Actelians and the Q-Logic guys. For SRAM-based, there is the Atmel 6K series and Dynalogic (no longer with us). Then there's Gatefield's reprogrammable, non-volatile FPGAs which is also does not use LUT-based logic elements. ---------------------------------------------------------------------- rk The 20th Century will be remembered, stellar engineering, ltd. when all else is forgotten, as the stellare@erols.com.NOSPAM century when man burst his terrestrial Hi-Rel Digital Systems Design bounds. -- Arthur SchlesingerArticle: 21291
In article <38CF92F1.967CAD85@algor.co.uk>, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > > eml@riverside-machines.com.NOSPAM wrote: > > Do you Fred /does anybody know if Synplify gives you this control? I use FPGA express (Synopsis) > > It does give you this control - all you have to do is set the ``syn_maxfan'' > attribute for the net to something huge to prevent splitting/duplication. Its > probably worth putting a ``syn_preserve'' or ``syn_keep'' on the reg/wire > driving the reset line. > > BUT .... > > There is another problem with Synplify. Even if you haven't put an SR control on a > FF in the HDL source you might get one anyway since Synplify will use a the > _synchronous_ set/reset input of a Xilinx FF as a free ``or/and'' gate! e.g. if > your code looks something like this: > > always @(posedge clk) > out <= d_in & !foo; > > then post optimisation & mapping you'll very likely get this in the netlist: > > FDR inst_name (.Q(out), .C(clk), .D(d_in), .R(foo)); > > Its even worse since you don't actually know which way round it will assign the > D,R inputs. If there are inverted > versions of d_in & foo available you might get: > > FDR inst_name (.Q(out), .C(clk), .D(~foo), .R(~d_in)); > > To get around this you need to make sure that FF's destined for IOBs are fed from > wires with a syn_keep attribute: > > wire temp /*synthesis syn_keep=1 */; > assign temp = d_in & !foo; > > always @(posedge clk) > out <= temp; > > Ps : Each FF control one Enable (Fan Out=1), I use a GSR Fred Laboratoire Signaux et systèmes CNAM Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21292
Hello, anybody heard about the SystemC ? I am a VHDL designer with a knowledge of C++ programming. What do you think SystemC would bring me ? I studied the specification and VHDL seems to be much more convenient as a HW specification language... Do you have any example of a case where the SystemC specification would bring some advantages in the design flow ? Best regards, Tomas Dulik Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21293
Peter Alfke wrote: > > From my computer here at Xilinx, I can access all sorts of semiconductor websites. > It's a joy. > I have Intel, AMD, National, Altera, Quicklogic, Actel, Cyprus at my fingertips. > But not Atmel. > I get: > > Forbidden > > You don't have permission to access / on this server. > > Apache/1.3.9 Server at www.atmel.com Port 80 > > Shame on you, Atmel ! What are you afraid of ? > > Peter Alfke Calm down. It was probably a server glitch. I can access it ok right now, down to downloading the datasheets. John Kortink That you're paranoid doesn't mean they're not out to get you Email : kortink@inter.nl.net Homepage : http://www.inter.nl.net/users/J.KortinkArticle: 21294
I had quite a few problems using coregen in version 1.5. And I encountered many times such errors (I cant remember though if the statements were exactly the same). The only solution that I found by the time was to make my own RPMs with the schematic editor. It also proved to be much more efficient for solving routing problems. Anyway having handmade RPMs is not as long to do as you might think. You just need to have good knowledge of low-level circuit design (a little bit more technical that push-button coregen!). Louis Steven Derrien wrote: > I try to generate a pipelined multiplier, but have the following error, > any idea of the problem ? > > ERROR: An internal error has occurred. Please call Xilinx support. > ERROR: Sim has a problem implementing the selected core. Implementation > netlist will not be generated. > ERROR: SimGenerator: Failure of Sim to implement customization > parameters core mul16 > WARNING: Core mul16 did not generate product ImpNetlist. > WARNING: Warnings and/or errors encountered while generating mul16 > (Variable_Parallel_Multiplier 1.0) All output products requested may not > have been generated. > > Thanks, > > StevenArticle: 21295
I assume you know about http://www.estec.esa.nl/wsmwww/erc32/ from the vhdl faq, which is a processor core with ECC on all the data paths. It's from the European Space Agency, and it's under GPL. -- Gary Watson gary@nexsan.sex (Change dot sex to dot com to reply!!!) Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com Terje Mathisen <Terje.Mathisen@hda.hydro.com> wrote in message news:38BBCD78.61026EE9@hda.hydro.com... > Greg Deych wrote: > > > > Does anybody know of a resource (web, book or article) describing > > architecture design for systems, storage or logic, whose components > > are prone to very high rate of failure, along the line of 0.1%-1%? >Article: 21296
Another couple of important things to take into account: FPGA's, because of their RAM/lookup table structure, must be reloaded at each power-up. This makes them somewhat more vulnerable to copying than CPLD's/PLD's, though the latter are not totally secure either. FPGA's have lots of resources, mostly registers, which it's not likely will be fully utilized, depending on application. CPLD's have fewer registers, but full utilization is generally not a problem. The CPLD's have the PLD's AOI-gate (SOP-friendly) architecture, hence offer lots of multiplexing resources at essentially no cost in resources, making multiplexors and synchronous counters easy and thrifty to implement. FPGA's have lots of registers which are somewhat more difficult to interconnect, and each one has a lookup table used to generate random logic functions associated with it. However, these are sometimes difficult to interconnect without timing and routing resource penalties. Hence, ripple counters, particularly grey-code ripple counters and "one-hot-one" shift register structures are popular with FPGA's. Some jobs simply fit better in one device type than in the other. Dick On Wed, 15 Mar 2000 13:20:55 -0000, "David Frith" <david.frith@ffei.co.uk> wrote: > >David Frith <david.frith@ffei.co.uk> wrote in message >news:8ao2dv$2kf@isgsrv1.hh.ffei.co.uk... >> JaeYong Kim <jaelong@lge.co.kr> wrote in message >> news:006ucssuqv358olp893qesagof13ar5oue@4ax.com... >> > What is the difference between FPGA, PLD, CPLD ? >> > they are all programmable chip. what is different ? >> > > >Neglected to say that the interconnects in an FPGA are usually switched by >storing a '1' or a '0' in an SRAM cell whilst in a CPLD they are controlled >by a made or blown fuse (which may or may not be electrically erase-able). >FPGA's need their SRAMs loading each time they are powered-up (called >configuration) whilst CPLDs keep their program even when powered off. There >are advantages and disadvantages of both ways of doing things. > >David > >Article: 21297
====================================================================
Workshop on Cryptographic Hardware and Embedded Systems 2000
(CHES 2000)
http://www.ece.WPI.EDU/Research/crypt/ches
Worcester Polytechnic Institute
Worcester, Massachusetts, USA
August 17 & 18, 2000
Third and Final Call for Papers
General Information
The focus of this workshop is on all aspects of cryptographic
hardware and embedded system design. The workshop will be a forum of
new results from the research community as well as from the industry.
Of special interest are contributions that describe new methods for
efficient hardware implementations and high-speed software for
embedded systems, e.g., smart cards, microprocessors, DSPs, etc. We
hope that the workshop will help to fill the gap between the
cryptography research community and the application areas of
cryptography. Consequently, we encourage submission from academia,
industry, and other organizations. All submitted papers will be
reviewed.
This will be the second CHES workshop. The first workshop, CHES '99,
was held at WPI in August of 1999 and was very well received by
academia and industry. There were 170 participants, more than half of
which were from outside the United States.
The topics of interest include but are not limited to:
* Computer architectures for public-key cryptosystems
* Computer architectures for secret-key cryptosystems
* Reconfigurable computing and applications in cryptography
* Cryptographic processors and co-processors
* Modular and Galois field arithmetic architectures
* Tamper resistance on the chip and board level
* Smart card attacks and architectures
* Efficient algorithms for embedded processors
* Special-purpose hardware for cryptanalysis
* Fast network encryption
* True and pseudo random number generators
* Cryptography in wireless applications
Mailing List
If you want to receive emails with subsequent Call for Papers and
registration information, please send a brief mail to
ches@ece.orst.edu.
Instructions for Authors
Authors are invited to submit original papers. The preferred
submission form is by electronic mail to ches@ece.orst.edu. Papers
should be formatted in 12pt type and not exceed 12 pages (not
including the title page and the bibliography). The title page should
contain the author's name, address (including email address and an
indication of the corresponding author), an abstract, and a small
list of key words. Please submit the paper in Postscript or PDF. We
recommend that you generate the PS or PDF file using LaTeX, however,
MS Word is also acceptable. All submissions will be refereed.
Only original research contributions will be considered. Submissions
must not substantially duplicate work that any of the authors have
published elsewhere or have submitted in parallel to any other
conferences or workshops that have proceedings.
Workshop Proceedings
The post-proceedings will be published in Springer-Verlag's Lecture
Notes in Computer Science (LNCS) series. Notice that in order to be
included in the proceedings, the authors of an accepted paper must
guarantee to present their contribution at the workshop.
Important Dates
Submission Deadline: April 15th, 2000.
Acceptance Notification: June 15th, 2000.
Final Version due: August 1st, 2000.
Workshop: August 17th & 18th, 2000.
NOTES: The CHES dates August 17 & 18 are the Thursday & Friday
preceding CRYPTO 2000 which starts on August 20.
Invited Speakers
Alfred Menezes, University of Waterloo, Canada.
"Elliptic curve cryptography in constrained environments"
David Naccache, Gemplus, France.
"How to explain side channel leakage to your kids"
Program Chairs
All correspondence and/or questions should be directed to either of
the Program Chairs:
Cetin Kaya Koc Christof Paar
Dept. of Electrical & Computer Dept. of Electrical & Computer
Engineering Engineering
Oregon State University Worcester Polytechnic Institute
Corvallis, Oregon 97331, USA Worcester, MA 01609, USA
Phone: +1 541 737 4853 Phone: +1 508 831 5061
Fax: +1 541 737 8377 Fax: +1 508 831 5491
Email: Koc@ece.orst.edu Email: christof@ece.wpi.edu
Program Committee
Gordon Agnew, University of Waterloo, Canada
Wayne Burleson, University of Massachusetts at Amherst, USA
Kris Gaj, George Mason University, USA
Peter Kornerup, Odense University, Denmark
Arjen Lenstra, Citibank, USA
Jean-Jacques Quisquater, Universite Catholique de Louvain, Belgium
Patrice Roussel, Intel Corporation, USA
Christoph Ruland, University of Siegen, Germany
Joseph Silverman, Brown University and NTRU Cryptosystems, Inc., USA
Colin Walter, Computation Department - UMIST, U.K.
Michael Wiener, Entrust Technologies, Canada
Location
WPI is in Worcester, the second largest city in New England. The city
is 80 km (50 miles) west of Boston and 280 km (175 miles) north-east
of New York City.
Worcester is home to a wealth of cultural treasures, many of which
are just a short distance from WPI. These include the historic
Higgins Armory Museum, which houses one of the world's largest
collections of armor; the EcoTarium (formerly New England Science
Center), one of the only museums in the country dedicated to
environmental education; and the beautifully restored Mechanics Hall,
one of America's finest concert halls. The Worcester Art Museum,
holding one of the nation's finest collections, and the
world-renowned American Antiquarian Society, with the largest
collection of items printed during the nation's colonial period, are
within two blocks of the WPI campus. Worcester is also well known for
its ten colleges, which cooperate through the Colleges of Worcester
Consortium.
Recreation areas within easy driving distance include Boston and Cape
Cod to the east, the White and Green mountains to the north, and the
Berkshires to the west.
August weather in New England is usually very pleasant with average
temperatures of 20 C (70 F).
Workshop Sponsors
This workshop has received generous support from cv cryptovision, Intel,
secunet AG, and SITI. The organizers express their sincere thanks.
Article: 21298David Frith wrote: > Neglected to say that the interconnects in an FPGA are usually switched by > storing a '1' or a '0' in an SRAM cell whilst in a CPLD they are controlled > by a made or blown fuse (which may or may not be electrically erase-able). > FPGA's need their SRAMs loading each time they are powered-up (called > configuration) whilst CPLDs keep their program even when powered off. There > are advantages and disadvantages of both ways of doing things. > > David Here are a few corrections: FPGAs are not all SRAM-based. Actel and Quicklogic use anifuses, and they also do not use LUT-based logic. Altera likes to use the name CPLD for their SRAM- and LUT-based FPGAs, but that's for obscure political reasons. PLD i generally used as a generic name for all programmable logic, including CPLDs and FPGAs Simple AND-OR based designs were introduced as, and are still called, PALs. They generally do not use fuses anymore, but rather CMOS EPROM cells for programming them, All modern CPLDs are now EEPROM or Flash-based and thus in-system-programmable. Peter Alfke, Xilinx ApplicationsArticle: 21299
Avinash Maddy wrote:
> Can any one tell me how to write a VHDL code to read bits (1s and 0s) from a
> file on the PC and another VHDL code to write output bits to a file on the
> PC?
> I am using both Altera and Xilinx platforms. Is it actually possible on
> these platforms ?
Altera or Xilinx platforms do not matter, 'cos U can only write behavioural
code to do file IO.
So, u can only simulate the code. Obviously there is no way to synthesize code
for File I/O.
The following code works fine on the qhdl (VHDL) simulator from Mentor :
It takes a file named "values" which contains a sequence of numbers (one
number/line)
and converts them to binary,hex,octal,etc
Hope this helps,
--navanee
USE std.textio.ALL;
PACKAGE io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0);
TYPE radix IS (binary, octal, decimal, hex);
-- read a number from the line
-- use this if you have hex numbers that are not in VHDL pound-sign format
PROCEDURE read(l : INOUT line; value : OUT integer; radix : IN positive);
-- read a number that might be in VHDL pound-sign format
PROCEDURE read_based(l : INOUT line; value : OUT integer);
PROCEDURE write(l : INOUT line;
value : IN bit_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false);
END io_utils;
PACKAGE BODY io_utils IS
PROCEDURE write_string(l : INOUT line;
value : IN string;
justified : IN side := right;
field : IN width := 0)
IS
BEGIN
write(l, value, justified, field);
END;
PROCEDURE shrink_line(l : INOUT line; pos : integer) IS
VARIABLE tmpl : line;
BEGIN
tmpl := l;
l := NEW string'(tmpl(pos TO tmpl'high));
deallocate(tmpl);
END;
PROCEDURE read(l : INOUT line;
value : OUT integer;
radix : IN positive)
IS
CONSTANT not_digit : integer := -999;
-- convert a character to a value from 0 to 15
FUNCTION digit_value(c : character) RETURN integer IS
BEGIN
IF (c >= '0') AND (c <= '9') THEN
RETURN (character'pos(c) - character'pos('0'));
ELSIF (c >= 'a') AND (c <= 'f') THEN
RETURN (character'pos(c) - character'pos('a') + 10);
ELSIF (c >= 'A') AND (c <= 'F') THEN
RETURN (character'pos(c) - character'pos('A') + 10);
ELSE
RETURN not_digit;
END IF;
END;
-- skip leading white space in the line
PROCEDURE skip_white(VARIABLE l : IN line; pos : OUT integer) IS
BEGIN
pos := l'low;
FOR i IN l'low TO l'high LOOP
CASE l(i) IS
WHEN ' ' | ht =>
pos := i + 1;
WHEN OTHERS =>
EXIT;
END CASE;
END LOOP;
END;
VARIABLE digit : integer;
VARIABLE result : integer := 0;
VARIABLE pos : integer;
BEGIN
-- skip white space
skip_white(l, pos);
-- calculate the value
FOR i IN pos TO l'right LOOP
digit := digit_value(l(i));
EXIT WHEN (digit = not_digit) OR (digit >= radix);
result := result * radix + digit;
pos := i + 1;
END LOOP;
value := result;
-- remove the "used" characters from the line
shrink_line(l, pos);
END;
PROCEDURE read_based(l : INOUT line; value : OUT integer) IS
VARIABLE digit : integer;
VARIABLE num : integer;
VARIABLE base : integer;
BEGIN
read(l, num, 10);
IF (l'length > 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
base := num;
read(l, num, base);
IF (l'length >= 1) AND (l(l'left) = '#') THEN
shrink_line(l, l'left+1);
END IF;
END IF;
value := num;
END;
PROCEDURE write(l : INOUT line;
value : IN bit_vector;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_int(bv : bit_vector) RETURN integer
IS
VARIABLE result : integer := 0;
BEGIN
FOR i IN bv'RANGE LOOP
result := result * 2;
IF (bv(i) = '1') THEN
result := result + 1;
END IF;
END LOOP;
RETURN result;
END;
TYPE array_of_widths IS ARRAY(radix) OF natural;
CONSTANT nibble_widths : array_of_widths := (
binary => 1,
octal => 3,
hex => 4,
decimal=> 32);
CONSTANT hex_digit : string(1 TO 16) := "0123456789ABCDEF";
ALIAS input_val : bit_vector(value'length DOWNTO 1) IS value;
CONSTANT nibble_width : natural := nibble_widths(base);
CONSTANT result_width : natural := (value'length + nibble_width -
1)/nibble_width;
VARIABLE result : string(1 TO result_width); -- longest possible value
VARIABLE result_pos : positive := 1;
VARIABLE nibble_val : integer;
VARIABLE bitcnt : integer;
BEGIN
IF base = decimal THEN
write(l, to_int(value), justified, field, base, use_pound);
RETURN;
END IF;
bitcnt := value'length MOD nibble_width;
IF (bitcnt = 0) THEN
bitcnt := nibble_width;
END IF;
FOR i IN input_val'RANGE LOOP
nibble_val := nibble_val * 2;
IF (input_val(i) = '1') THEN
nibble_val := nibble_val + 1;
END IF;
bitcnt := bitcnt - 1;
IF (bitcnt = 0) THEN
result(result_pos) := hex_digit(nibble_val + 1);
result_pos := result_pos + 1;
nibble_val := 0;
bitcnt := nibble_width;
END IF;
END LOOP;
write(l, result, justified, field);
END;
PROCEDURE write(l : INOUT line;
value : IN integer;
justified : IN side := right;
field : IN width := 0;
base : IN radix;
use_pound : boolean := false)
IS
FUNCTION to_bv(int : integer) RETURN bit_vector
IS
VARIABLE bv : bit_vector(32 DOWNTO 1) := (OTHERS => '0');
VARIABLE pos : integer := 0;
VARIABLE tmpval : integer := int;
BEGIN
FOR i IN 1 TO 32 LOOP
pos := pos + 1;
IF (tmpval MOD 2) = 1 THEN
bv(i) := '1';
END IF;
tmpval := tmpval / 2;
EXIT WHEN tmpval = 0;
END LOOP;
RETURN bv(pos DOWNTO 1);
END;
VARIABLE tmp : line;
BEGIN
IF (base = decimal) THEN
IF (use_pound) THEN
write_string(tmp, "10#");
END IF;
write(tmp, value);
IF (use_pound) THEN
write_string(tmp, "#");
END IF;
write(l, tmp.ALL, justified, field);
deallocate(tmp);
ELSE
write(l, to_bv(value), justified, field, base, use_pound);
END IF;
END;
END io_utils;
-- test the hex number reader
ENTITY test IS END;
USE std.textio.ALL;
USE work.io_utils.ALL;
ARCHITECTURE hex_test OF test IS
BEGIN
PROCESS
VARIABLE val : integer;
FILE myfile : text IS IN "values";
VARIABLE inline : line;
VARIABLE outline : line;
BEGIN
WHILE NOT endfile(myfile) LOOP
readline(myfile, inline);
write(outline, inline.ALL);
read_based(inline, val);
write_string(outline, " binary: ");
write(outline, val, base => binary);
write_string(outline, " octal: ");
write(outline, val, base => octal);
write_string(outline, " decimal: ");
write(outline, val, base => decimal);
write_string(outline, " hex: ");
write(outline, val, base => hex);
writeline(output, outline);
END LOOP;
WAIT;
END PROCESS;
END;
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