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You need delayed values of e(t) and x(t) for DLMS. You should also keep in mind that DLMS has slightly worse convergence behaviour than LMS. It is also possible that you will have more problems with adding all the forward calculation results than with initial multiplications. Unfortunately wallace trees are not a good fit for FPGAs. I have implemented an adaptive transpose FIR which is faster than regular LMS but this requires a lot more area. Its convergence behaviour is different too. Recently Scott Douglas et al has published another article about this subject. I haven't implemented it but it looks very promising: (A Pipelined LMS Adaptive FIR Filter Architecture Without Adaptation Delay, IEEE Trans. Signal Processing, vol. 46, no. 3, pp. 775-779, March 1998) "Jian F. Weng" <jfweng@ece.concordia.ca> wrote: >Hi everyone: >I have a problem of implmenting my LMS algorithm in an Altera >FLEX10K100A using VHDL. The weight update is like this >W(t+1)=W(t) + mu * e(t) *X(t) >where W(t): weight coefficient vector, and each element is with 20 bits. > mu: stepsize=0.001 > e(t): 8 bits error signal > X(t): signal vector in FFE and DFE and each element is with 8 >bits. >The requirements are 1) the design occpies the space as small as possible >and 2) the LMS is able to operating at 25MHz. >Although it is possible to design pipeline stages for 8X8 multiplication, >some delay will be incurred such that I need extra shift registers for W(t) >to get the addition synchronized and this may incurease the complexity. >On the other hand, if I directly do the multiplcation by using the available >block, the speed is below the expectation. > >Any reference and suggestions are highly appreciated! >Thanks >James >Article: 22901
On Tue, 30 May 2000 16:21:58 GMT, nestor@ece.concordia.ca (Nestor) wrote: |On Mon, 29 May 2000 02:54:22 -0400, Rickman <spamgoeshere4@yahoo.com> |wrote: | |>I took a look at a book I have by Roland E. Best called "Phase Locked |>Loops". It covers most of the types pretty well although I have never |>built one from it. He describes several types of digital PLLs, but none |>of them would be easy to use at the high frequencies you are describing. |>They all need a digital clock that runs at rates much higher than your |>100 MHz. I think your second design with a digital loop filter will have |>the same problem. To use a counter as you describe, I think you will |>need a very fast clock that can count many cycles in the 40 nS period of |>your reference clock. | |Thanks for your very descriptive response, Rick. | |If I reduce my oscillator frequency by say 100 times so that the |reference now equals 1MHz, then I could run the counter fast enough |(maybe 100MHz) and still be using a low enough reference to satisfy |jitter requirements. Would you know the amount by which the jitter |will be reduced using the new reference? | |> |>Best does describe one circuit that uses a "Zero Crossing" Phase |>Detector (PD) that uses the reference clock to ADC sample the input |>signal (assuming it is not a digital clock but a sinewave). The |>resulting digital sample stream can be converted back to analog and used |>as the VCXO control signal. The filter block can be a simple averaging |>filter which can be easily done in the FPGA with an accumulator and a |>delay block, or as an IIR filter with only an accumulator. | |I am thinking of a first-order digital loop filter which sums two |components: the direct path with a gain G1 applied to it, and an |accumulator branch with a gain G2 applied to it (either before of |after the accumulator). | |> |>BTW, I don't think in your digital loop filter circuit that you need an |>analog filter after the DAC. At this point the DAC output is the control |>signal and any filtering will just add a delay to the loop and possibly |>make it unstable. The normal purpose of a loop filter is to average an |>AC signal to eliminate fluctuations within a cycle. Too much filtering |>is bad. The small steps you will expect from a digital loop filter |>should not cause problems in your VCXO. | |You are correct. I expect small voltage adjustments to the VCXO and |so the ADC will already be slowly changing. This output signal can be |used directly to control the VCXO. | | |> |>If you really need to disconnect your refrence from the circuit for |>extended periods of time, a digital loop filter will allow you to |>implement a better "hold" circuit than an analog filter. You simply hold |>the last VCXO control signal to the DAC. The hard part will be detecting |>that your reference is gone before the PLL starts to hunt. I assume you |>would have control over this and put it into hold mode before the signal |>goes away. |> | |I can take care of this since I since in advance the duration of the |transmitted reference during initialization or re-acquisition fo the |loop. | |> |>nestor@ece.concordia.ca wrote: |>> |>> Hi everyone. |>> |>> Back in late February I posted a message in order to gain some insight |>> in designing a digital phase-locked loop (DPLL) for frequency |>> synthesis to be used as the master clock of an FPGA system. I had |>> received a number of useful replies (thanks to all who provided |>> feedback) and links to some application notes that have helped me to |>> better understand the design of a PLL. I have consulted some other |>> references on PLL design as well, including Gardner's and Rohde's |>> books. |>...snip... |>> All your suggestions are very much appreciated. Thanks in advance, |>> |>> Nestor |>> nestor@ece.concordia.ca |>> |>> P.S.: As a side question, I am thinking of implementing the PLL to |>> synthesize the system's clock without always having the reference |>> frequency present. This requires the freezing of the comparator |>> outputs or the loop filter outputs, as well as a periodic refresh by |>> retransmitting the reference at regular intervals. I am not sure, |>> though, if this can cause the loop to temporarily lose lock or |>> possibly cause it to start up anew using a completely different phase |>> value. However, I think the frequency should not vary much. Any |>> comments? |> |>I think that reconnecting the reference will cause a disruption in the |>output frequency as the circuit locks in. But I don't think you will |>come to a different phase value unless the reference freq has changed. | |My reference frequency will always be generated from the same source, |hence the frequency should remain constant. However, I am not 100% |certain I can guarantee the same phase always arriving at the PLL |(although theoretically the phase should not change if the path to the |PLL does not change), and I worry that the different phase can cause |the PLL to output a sincewave with a different phase. | |How do you explain that the the re-locked frequency can change? Is it |because the PLL can re-lock using a completely different start |frequency, even when the output frequency is held constant in the |absence of the reference? | |I await your comments. Thanks. | |Nestor |nestor@ece.concordia.ca | |>If I understand these things properly, the VCXO is like a spring on the |>gas pedal. To go a given speed, you will always be pressing the spring a |>certain amount (the phase error in this case). To go faster, you will |>need a larger phase error which presses on the pedal harder. The only |>way around this is to use an integrator function in the loop and then |>you will have to damp oscillations. |> |>I hope I am not coming across like an expert at this, I am not. This is |>just free advice, so it is likely worth what you are paying. ;) | | | | | Nestor, I once did a digital PLL using a 10-bit ADC as the phase detector. The control algorithm was a basic proportional+integral servo loop. It worked fine with either a true accumulator for the integral path, or just an up/down counter; we settled on the counter as that used less gates. The output fed a 12-bit DAC and a varicap on an LC oscillator. We got something like 30 ps RMS jitter with the loop operating at 5 MHz (undersampling a 20 MHz oscillator). If you can detect signal loss, you could just freeze the logic and hold the varicap voltage steady, then stay sorta locked until the oscillator drifts too far away. If you divide things down and work at lower frequencies, jitter will eventually go up. JohnArticle: 22902
In the early '70s I worked at Fairchild, and, with two buddies, I got a patent on a PLL frequency synthesizer ( #4023116 of May 1977) It describes how to avoid the dead-band in the phase detector, by deliberatedly injecting an error pulse into its output, so that the phase comparator is never balanced, but always has to push against this error. I always wanted to resurrect this idea in the FPGA design, but never did. This trick did reduce jitter substantially. And the patent is obviously no longer being enforced :-) Old war stories... Peter Alfke ================================ David R Brooks wrote: > nestor@ece.concordia.ca (Nestor) wrote: > > :On Tue, 30 May 2000 07:41:19 +0800, David R Brooks > :<daveb@iinet.net.au> wrote: > :>: ... > :> The sampling detector using a sinusoidal input does work, as it > :>produces a truly analog output. > : > :Can you provide some more details on this topic? Are you suggesting > :that to use the phase detector (described in the xilinx appnote) in > :conjunction with a sinusoidal input, or is this a completely > :different phase detector? If the latter is the case, could you > :provide a reference or a brief explanation on its structure and > :behaviour (if possible)? I would lie to examine as many options as I > :can before committing to a specific design. > : > This is a different type (also mentioned in Best). It requires a > reference signal having a finite slope to its waveform. Triangular or > sinusoidal will work, but rectangular pulses will not. The loop gain > is a function of the reference slope (determined by frequency & > amplitude). > It matches well with a switched-capacitor loop filter, but anything > which works by taking regular samples (eg digital filter) should work. > > Imagine a PLL with a sinusoidal reference input, and a sampling > filter, which is clocked from the VCO (divided as necessary). Suppose > further, that the sample is presently taken on the rising "edge" of > the reference waveform. If now the VCO speeds up, the sample is taken > earlier, and a lower voltage is read. So (after filtering) the VCO > control voltage is reduced, and it slows down. Vice versa, for a VCO > which slows down, a later (higher) voltage is sampled, so speeding up > the VCO. If the PLL starts up sampling on the falling "edge", it will > be unstable, & will quickly shift to the rising "edge". > > OK, let's try at a drawing (monospaced type, please): > > S1 S2 > /\ __ __ > / \/ ---o o-+-o o--+--------> Control voltage > Vref | | > === === > | C1 | C2 > V V > > S1 and S2 are driven by non-overlapping clocks derived from the VCO. > Together with C1, they simulate a resistance, with an input-sampling > function. This resistance, with C2, is a basic low-pass filter. > If the ON-resistance of S1 is low enough for C1 to follow the input > voltage while S1 is closed, then the sample is taken at the instant S1 > opens. > This phase-detector has a transfer function similar to the reference > input, ie periodic. Consequently it has a limited capture range. > However this is unlikely to be a problem in a single-frequency > application, using a VCXO. > > I built such a PLL some years ago for a Master's thesis: I found a > 3rd capacitor necessary (in my application), to simulate the second > resistor of a common pole/zero filter. The circuit was entirely > fabricated on a chip, with the filter clocking at 132kHz (same as the > reference), the VCO running around 4.5MHz and divided down. > This design had to capture over a wide range, yielding a spectrally > pure output. This necessitated a frequency-lock to adjust the loop > parameters roughly into lock, then turning over control to the > sampler.Article: 22903
Nestor wrote: > Thanks for your very descriptive response, Rick. > > If I reduce my oscillator frequency by say 100 times so that the > reference now equals 1MHz, then I could run the counter fast enough > (maybe 100MHz) and still be using a low enough reference to satisfy > jitter requirements. Would you know the amount by which the jitter > will be reduced using the new reference? I don't know enough to say what effect lowering the refernce freq will have on jitter. My guess is that it will increase it at the lower frequencies and lower it at higher freqs. > >Best does describe one circuit that uses a "Zero Crossing" Phase > >Detector (PD) that uses the reference clock to ADC sample the input > >signal (assuming it is not a digital clock but a sinewave). The > >resulting digital sample stream can be converted back to analog and used > >as the VCXO control signal. The filter block can be a simple averaging > >filter which can be easily done in the FPGA with an accumulator and a > >delay block, or as an IIR filter with only an accumulator. > > I am thinking of a first-order digital loop filter which sums two > components: the direct path with a gain G1 applied to it, and an > accumulator branch with a gain G2 applied to it (either before of > after the accumulator). I can't say how this will work. This should be covered by control theory, which I never studied. > >I think that reconnecting the reference will cause a disruption in the > >output frequency as the circuit locks in. But I don't think you will > >come to a different phase value unless the reference freq has changed. > > My reference frequency will always be generated from the same source, > hence the frequency should remain constant. However, I am not 100% > certain I can guarantee the same phase always arriving at the PLL > (although theoretically the phase should not change if the path to the > PLL does not change), and I worry that the different phase can cause > the PLL to output a sincewave with a different phase. > > How do you explain that the the re-locked frequency can change? Is it > because the PLL can re-lock using a completely different start > frequency, even when the output frequency is held constant in the > absence of the reference? > > I await your comments. Thanks. I am saying that while not locked, the reference and the PLL will drift slightly. Then during reaquisition you may see a small spurious change in the PLL freq until they are locked. For example, if the PLL freq is low and the initial phase is -X degrees out, the loop may adjust the freq in the wrong direction initially. But as the phase shifts through 0 degrees and becomes positive, the direction of change will be corrected very quickly and the frequency will head in the right direction until locked. Then assuming that the reference freq has not changed, the two will end up with exactly the same phase relationship that they had when last locked. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22904
On Tue, 30 May 2000 08:18:47 -0400, "Simon Bilodeau" <simon.bilodeau@htrc.com> wrote: >I need to pulse on the enable line of a 3 to 8 demux that will allow to >reset a flip-flop (I use A0-3) to choose the flip-flop. I only need a >short pulse to do that. Why not go with a synchronous solution? Instead of clearing the flip-flops with a pulse, use each decoder output to force LOW the D input of the corresponding flip-flop, and clock the flip-flop. Or don't you have a clock? Bob Perlman > >Simon > >Bob Perlman <bobperl@best_no_spam_thanks.com> a écrit dans le message : >3932e99c.13144661@nntp.best.com... >> On Mon, 29 May 2000 16:28:09 -0400, "Simon Bilodeau" >> <simon.bilodeau@htrc.com> wrote: >> >> The late-but-somehow-immortal Henny Youngman told the following joke. >> A man walks into a doctor and says, "Doctor, it hurts when I do that." >> The doctor says, "Don't do that." >> >> You are attempting to asynchronously reset a flip-flop with its own Q >> output. Don't do that. It confuses the simulator (as you've seen), >> and in the actual hardware will produce a pulse of unknown width that >> may or may not be wide enough to do what you want to do. (If Murphy >> has any say in it, it will do what you want in the prototype but not >> in the production units.) >> >> Before I can suggest how to fix this, I need to have a better idea of >> just what you're trying to accomplish. >> >> Bob Perlman >> >> >> >Hi, i am in a design using a XC9500 IC from Xilinx and I have a problem >> >with the logic simulator : the Q output from the FDC is always undefined, >> >even if I clock the input. >> > >> >Any idea >> > >> >Thanks >> > >> >Simon >> > >> >> ----------------------------------------------------- >> Bob Perlman >> Cambrian Design Works >> Digital Design, Signal Integrity >> http://www.best.com/~bobperl/cdw.htm >> Send e-mail replies to best<dot>com, username bobperl >> ----------------------------------------------------- > ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 22905
We are getting a JTAG clock of about 30kHz with a Multilinx running on USB from a Win98 laptop. It's consistent. Xilinx say it shouldn't happen. They and our distributor have been trying to solve it for three weeks. We tried the serial link on the Multilinx and that gives a 5kHz JTAG clock. We tried another Multilinx and USB cable - same. We tried putting a BSCAN_virtex component in the design - same. I noticed that the first thing on JTAG TCK is 8 clocks at 8MHz (TDI = 1), then nothing for ages. The JTAG signals are clean, even at 8MHz. We're using a Virtex 1000BG560 on a prototyping card made by ARM. The JTAG chain has an xcv1000 and a 9536 CPLD. Any clues? AlunArticle: 22906
Hi, You can find the schematics of the Xilinx parallel JTAG cable here: http://support.xilinx.com/support/programr/files/0380507.pdf As far as I remember this cable is suitable for programming both XC9500 CPLDs and FPGAs. Regards, -- Georgi Beloev gbeloev@iname.comArticle: 22907
Nestor wrote: > On Mon, 29 May 2000 13:45:07 GMT, Ray Andraka <ray@andraka.com> wrote: > > >If you are looking at an analog PLL with a digital feedback, you might try > >an 88915 (IDT, motorola), which is a fairly standard low cost vanilla PLL > >made for clock replication. It has the VCO, phase comparator and loop > >filter in one 20 pin(?) SOIC package along with low skew outputs for 2x, 5 > >1x and a halx x output. Since the feedback and reference input is > >external, it is easy to add dividers in the feedback and reference paths > >to permit frequency synthesis. I've put the dividers as well as > >monitoring circuits in both FPGAs and CPLDs with good results. The only > >external component needed for the loop filter is a ceramic cap, so the > >parts count is low and there is no design tweaking. With the buffered low > >skew outputs, you may have enough clock drivers for your whole system, and > >you get the 1x,2x and 1/2x outputs already made and deskewed for you. > > Thanks, Ray, for your suggestion. > > The part you propose seems to do all that I want and at the frequency > that I want (IDT's). The only catch that I see is that the reference > signal must always be present. Because I will use an intermittent > reference tone in order to share the same channel with other data > transmissions, I don't think I can use this chip directly since the > non-clock data will cause the chip to behave incorrectly. From what I > understand, there is no hold function for the generated frequency in > the block diagram. I will still pursue this alternative as a backup > solution. > > >> > >> P.S.: As a side question, I am thinking of implementing the PLL to > >> synthesize the system's clock without always having the reference > >> frequency present. This requires the freezing of the comparator > >> outputs or the loop filter outputs, as well as a periodic refresh by > >> retransmitting the reference at regular intervals. I am not sure, > >> though, if this can cause the loop to temporarily lose lock or > >> possibly cause it to start up anew using a completely different phase > >> value. However, I think the frequency should not vary much. Any > >> comments? > > > >You don't want to use the VCO in a freee running mode like this. It is > >not a very stable source without a reference, so it will drift > >considerably. You might be able to construct a simple DPLL to > >replicate/synthesize the reference from a crystal source and then use the > >PLL to multiply that reference up to your system clock. The DPLL could > >then be used to discover the correct count values and then hold those > >counts when the reference dissappears. > > In order to avoid "floating" the input of the VCXO, I was thinking of > freezing the DAC output to the last valid voltage level, so that the > VCXO could maintain a stable frequency until the next reference tone > refresh. > The VCO in a PLL is not that stable without feedback. In other words, an analog PLL isn't going to give you a stable frequency without a reference. A digital PLL is essentially a division of a master clock, with the divide controlled by the phase of the reference vs the divided master. A DPLL can hold the last frequency by freezing the divides. What I was proposing is a 2 PLL system where you use a DPLL to generate an always present reference that is locked to your external reference when present and frozen when it is not. The analog PLL is used simply as a clock multiplier off the output of the DPLL. You do have a bit of a balancing act here because as you lower your reference frequency, your jitter increases (think of it as how far the oscillator will drift between successive reference edges). > > Regards. > > Nestor > nestor@ece.concordia.ca -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22908
Hi,
Does anybody have any data about cost/performance as a function
of performance (MIPS) for microprocessors in FPGA ?
Any information about processors in fpga would be highly appreciated.
thanks,
-------------------------------------------
- Domagoj -
- Domagoj@engineer.com -
-------------------------------------------
Article: 22909Hi all, Please answer me the following questions and obligue: 1. I have to design a Isochronous Fifo, so will that be made exactly the way as Asynchrous fifo (ie by using cs_B signal) or by using a clock (ie clock will be necessary here or not)??? 2. Is high impedence signal and dont care signal (ie 1'bz and 1'bx) are synthesizible or not?? Thanx, BYE.Article: 22910
A few thoughts for you to ponder, along with some of the other good ideas I see being generated: Use a phase comparator that has a 90 degree phase difference when in lock (e.g. a simple XOR). This does not have the narrow pulse / deadband problem when in lock. A high comparison frequency (i.e. low divide factors) gives higher loop gain, higher bandwidth, quicker response, etc. However, it also reduces the phase error that can be tolerated without losing lock. For instance, an XOR has a +/- pi/2 phase comparison range, but this is multiplied by the divide factor(s). A high divide factor reduces the gain and bandwidth, but this is often good. There is a hidden (at least to me at first) in the PLL. A VCXO responds with a frequency change to a control voltage change (and is damn quick about it too, usually about a 50KHz BW). However, the phase of the signal supplied to the phase comparator is a result of integrating or accumulating the frequency difference over time. If you fix the control voltage to the VCXO within its control range, the output will be stable, but will have some intrinsic jitter. This should be pretty low, but susceptible to power supply drift, noise, etc. Ask for numbers from the manufacturer. The phase comparator will generate harmonics of the phase comparison frequency (primarily 2X). This full strength output at 2X the phase comparison frequency will bull its way through the loop filter, although much attenuated. This remnant phase noise, or spurious products from the phase detector, will form the baseline jitter unless you take extra care to suppress it. Another RC pole at a higher frequency than the dominant loop filter break can take this down into the noise without changing the loop behavior. The open-loop phase gain response tells all. When that open loop gain nears 0dB, you need the total open-loop phase shift rolled back as close as you can get to the 90 degrees imposed by the freq -> phase integration. In other words, an integrator pole must be lead compensated by a zero before crossing through unity open-loop gain. Once below unity gain, another pole can come in to help suppress spurious noise. An integrator in the loop is a very good idea. It compensates for all kinds of small errors and will keep the phase error small. Good luck, Bob W. nestor@ece.concordia.ca wrote in message ... >Hi everyone. > >Back in late February I posted a message in order to gain some insight >in designing a digital phase-locked loop (DPLL) for frequency >synthesis to be used as the master clock of an FPGA system. I had >received a number of useful replies (thanks to all who provided >feedback) and links to some application notes that have helped me to >better understand the design of a PLL. I have consulted some other >references on PLL design as well, including Gardner's and Rohde's >books.Article: 22911
You can design a RISC processor around the FPGA architecture and get pretty good performance. You might look at the series by Jan Gray in Circuit Cellar for an example. If you are trying to emulate a commercial processor, you are going to be considerably slower and more expensive than the purpose-made processor, except in those cases where the processor is in a really old (several microns) technology. Domagoj wrote: > Hi, > Does anybody have any data about cost/performance as a function > of performance (MIPS) for microprocessors in FPGA ? > > Any information about processors in fpga would be highly appreciated. > > thanks, > ------------------------------------------- > - Domagoj - > - Domagoj@engineer.com - > ------------------------------------------- -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22912
In article <8h42k1$f08$1@bagan.srce.hr>, Domagoj <domagoj@engineer.com> wrote: >Hi, > Does anybody have any data about cost/performance as a function >of performance (MIPS) for microprocessors in FPGA ? > >Any information about processors in fpga would be highly appreciated. In addition to the pointers that Ray Andraka gave, another implementation (this of a SPARC integer core, in HDL, for virtex and altera) is available at http://www.estec.esa.nl/wsmwww/leon/ -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 22913
hello out there, Can anybody tell me please how to do a verify with this board? I'm using the Xilinx Alliance Tools and the Hardware Debugger + Xchecker-Cable but each time I load a bit-file the Hardware Debugger disables his verify and readback function. (allthough I have enabled readback in the configuration step)Article: 22914
Dear friends,
I want to know which of the
settings in view synthesis should be used to increase the
speed of the design. I want to make my design faster,Please
suggest me which of the setting will help me
in this regard and any other techniques using
viewsynthesis to increase the speed.
Thank you,
ramesh
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22915
hi folks,
Is it possible to get 4-5 pcs. of the altera EPC2 device programmer from
some source? the min. oredr qty is 49, but I don't need that many, and
neither can I afford such a whopping amount. any indicators.....plz lemme
know sooooooon
cheers
Aditya
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Article: 22916Hi, There is a delay reset. One suggestion is in the Altera Errata Sheet : M-ES-APEX- 01.1. * Sent from AltaVista http://www.altavista.com Where you can also find related Web Pages, Images, Audios, Videos, News, and Shopping. Smart is BeautifulArticle: 22917
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1997 summer Computer Support Technician, Chinese Information and
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1995 – 1996 High School Math and Physics Tutor
ACTIVITIES
1997 August 1-3 Volunteer in Chinese Information and Community Services
on “Very Healthy Action” at Pacific Mall
1997 August 9 Volunteer in Chinese Information and Community Services on
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INTERESTS
- Spend a great portion of spare time reading websites on internet
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- Desktop publishing – mostly on pictures modifications
- Sports such as squash, swimming and badminton
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- Strategies, simulations and role playing computer games
- Extremely socialable
REFERENCE
Available upon request
Article: 22918
Can anyone tell me whats wrong?
Being new to FPGA I purchased an X84 board from APS
with a Xilinx 5203 & Foundation. Using the schematic tool
I was able to read the board's 555 timer, divide it down and blink an
LED.
When I tried this in verilog I received a message saying I must
add a global buffer and input pad to read the clock. How do you
do this in verilog using Foundation? I wasn't able to find an IPAD
in the 5200 library on foundation so I'm stuck.
Should I switch to another tool other than Foundation or maybe do this
in VHDL? What am I missing??
Hal.
Article: 22919Hi - What happened to OptiMagic, my favorite FPGA site? I haven't been able to access http://www.optimagic.com recently - has it moved? Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 22920
First of all, exuse me for my poor english. I've got a disign on a XC4044XLA , implemented with Foundation 1.5i. This design is "critiqal in delay". I'd like to make few modifications on this design if possible, without modifying the first routing. What is the best method?? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22921
Hello. I am trying to do some analysis on parts of a custom board that we are designing. Specifically, I am trying to analyze a Virtex FPGA connected to a few banks of SDRAM, and want to model the current draw from the memories during an autorefresh cycle, as well as the current draw (to make sure that the fpga can provide the drive) for both registered (buffered) and unregistered memory modules. I have the spice models for the memory, and the IBIS models for the Xilinx part. Problem is that I haven't used SPICE in about 10 years. Has anyone done anything like this before? Does anyone have any (non flame) recommendations for me? Does anyone have any book recommendations to get up to speed on SPICE VERY VERY quickly? IS there a better group to post to? Any advice or solutions would be appreciated. Thanks, Joe yose@wam.umd.eduArticle: 22922
Hi friends, I have another question regarding blackbox instantiation: can you obtain something similar to Xilinx RPM (Relational Placed Macros) with this method?. Can it help selecting a "preserve hierarchy" or similar command?. Thanks in advance for your time. Ray Andraka <ray@andraka.com> wrote in 3932EFB5.439D15EA@andraka.com... > Unless you intend to package and sell the CORE, there is really no need to > put it under coregen. Coregen is not much more than a pretty wrapper for > edif netlist files. Instead, just instantiate your code as a component in a > hierarchical VHDL design. If you are trying to do placement as well, I've > found the best way to do it hierarchically is to put placement attributes > right into the VHDL, which means you build the components from the > structural level (I think this is probably why you want to create a > component under the COREGEN). Alternatively, you can instantiate your core > as a blackbox in VHDL under which you have an edif netlist (that is all > coregen does with it). Look under the design guides for mixed schematic/HDL > design methodology for details on instantiating black boxes in your design. > > Vipan Kakkar wrote: > > > Dear friends: > > > > I have a vhdl description for an FIR filter make one of the tap as a > > core to use it to implement the FIR filter in FPGA. I was trying to > > build one tap as a core using the Xilinx COREGEN, but don't know how to > > do it. Coregen library has FIR filter, but I want to build a core from > > my vhdl description of the tap, which is shown below: > > > > Could anyone help me that ... if it is possible to build a core from the > > vhdl description I have ... if yes then what commands (in the COREGEN) > > should be given and what files (e.g. .xco etc.). > > > > entity FIRTAP is > > port( > > CLK_S : in std_logic_vector( 8 downto 0); > > RSTn_S : in std_logic_vector( 8 downto 0); > > LDCOEF : in std_logic; > > COEFi : in std_logic_vector(15 downto 0); > > COEFo : out std_logic_vector(15 downto 0); > > I : in std_logic_vector(15 downto 0); > > O : out std_logic_vector(15 downto 0); > > PI : in std_logic_vector(63 downto 0); > > PO : out std_logic_vector(63 downto 0)); > > end FIRTAP; > > > > Regards, > > Vipan > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com > > -- ----------------------------------------------------------------------- Javier Garrigos Guerrero Departamento de Electronica, Tecnologia de Computadoras y Proyectos E.T.S. de Ingenieros Industriales - Univ. Politecnica de Cartagena Paseo Alfonso XIII, 48. 30203 CARTAGENA (MURCIA) -SPAIN- Phone:+34 968 325567 Fax:+34 968 325433 E-mail: Javier.Garrigos@upct.es -----------------------------------------------------------------------Article: 22923
I seem to be experiencing an unconstrained timing problem around the read port of a BS RAM being used as a FIFO. It seems that we have some data latched around the output of the BS RAM which is not quite making the setup time to the next stage. The App notes talk about a latch around the output of the BS RAM itself, but I haven't found much detailed information about how it works. Anyone else experience a similar problem or have some information about the latch structure/control?Article: 22924
. After further investigation, I think we have found a problem with constraints around the block RAMs. We are using the block RAMs for an asynchronous FIFO interface, with Write Clk A @ 14.5 ns and Read Clk B @ 9.5 ns. Even though Read Clk B is constrained, when I follow the output data from the BR through the logic into a flip flop using the timing analyzer, the path comes in at 12.5 ns on a 9.5 ns constraint on Read Clk B. I would like to see this report an error in the tool, but the timing analyzer doesn't seem to think this is a problem! To get the timing analyzer to see this path and analyze it properly, I had to set a constraint from Write Clk A to Read Clk B of 9.5 ns, and then the timing analyzer was able to report the errors, and presumably try to place and route the device to make the necessary timing. I think this a BUG in the timing analyzer for Alliance, using 2.1i SP6, and even in the new 3.1 tool, which we have also tried. Anyone else see this problem? We are working with Xilinx to look into it, but I just can't believe we are the first people to experience this problem. Eirik Esp wrote: > I seem to be experiencing an unconstrained timing problem around the > read port of a BS RAM being used as a FIFO. It seems that we have some > data latched around the output of the BS RAM which is not quite making > the setup time to the next stage. The App notes talk about a latch > around the output of the BS RAM itself, but I haven't found much > detailed information about how it works. Anyone else experience a > similar problem or have some information about the latch > structure/control?
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