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Hello Jon,
Version 3.1i supports a BEL constraint for Virtex. Here's and example of
UCF syntax:
INST inst_name BEL = {F, G, FFX, FFY, XORF, XORG} ;
You use RLOC/LOC/BLKNM etc. to determine the slice used and the BEL
constraint to determine the BEL within the slice.
Regards,
Bret
russojl@my-deja.com wrote:
> In 4k type stuff, you used to be able to constrain flip flops
> with a ".FFX" suffix, like:
>
> loc=R1C1.FFX
>
> What's the new way to do it in the Virtex.
>
> Thanks,
> Jon
>
> PS I'm starting to RTFM, but I figured someone could get the info to
> me faster, since my reference skills are poor.
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
Article: 23176Thanks for everyone's replies. Here are some details of what I wish to do using the narrowband BPF: 1) I would like to synchronize to a tone of 1.5625MHz that is generated from another node on a network. I do not have access to the transmitting node, and the tone will always be present on the line. 2) Because of noise on the channel, I need to perform very narrowband filtering so that I may be able to distinguish and lock to the tone only with a Phase-Locked Loop (PLL). 3) I am thinking of at least a 35dB out-of-band rejection, and a passband (3dB frequencies) in say +/-150ppm % of the center of 1.5625MHz (or ~+/-250Hz relative to the center). Because I am fairly new to analog design I am not sure what would be the best approach: elliptic filters, crystal/resonator filters? Also, if a single component solution does not exist, do you know of a good reference or application note which explains how to build my own narrowband BPF? I have a good reference for elliptic filters, but not for the other kinds. Thanks in advance for any further suggestions. NestorArticle: 23177
The new Xilinx M3.1i tools are supposed to support this new feature. Has anyone got it working? What I want to do is to have par place and route only the block that is changed during logic synthesis (I'm using the latest FPGA compiler II, that also is supposed to support this mode). THere is no mention of this feature in the M3.1i documentation. Xilinx tech support did not know about it either. Any clues? Thanks much, -ArrigoArticle: 23178
I use parallel cable III to configure my XC4010xl device. My Mode pins are unconnected. and Pin INIT is connected to VCC via 1Kohm. Then when I program my device I chose HARDWARE DEBUGGER. in foundation 2.1i. Björn sceloporus occidentalis <s_occidentalis@hotmail.com> skrev i diskussionsgruppsmeddelandet:8ich2o$3i9$1@nnrp1.deja.com... > Looking to configure XC4000 series directly through PC parallel port, > ost likely in asynchronous parallel mode. Am working it out but any > experience, schematics or ideas appreciated. Thanks! > > s_occidentalis@hotmail.com > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23179
There was a pointer to a free-ip site in the "PWM" posting (reply #1 I think) which was posted ~6/15. There is a discussion at this site on fifo's and also some VHDL coded fifo's. Les Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23180
In article <8icon3$9gd$1@nnrp1.deja.com>, Leon Heller <leon_heller@hotmail.com> wrote: > > I use the Xilinx parallel cable to download the configuration directly > into a SpartanXL chip on a prototype board. You could simply put the > cable circuit (schematic on the Xilinx web site) on your board with a > parallel port connector. > > Leon Thank you. However I need to use a standard parallel cable, for once the devices are configured I will then be transferring data through the printer port. In other words, the final system is FPGA-based with parallel port data transfer, and configuration must occur through the same cable. Thus I will be controlling the configuration pins with printer control signals. Someone must have done that before ... Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23181
Hi, I need to hand solder a PQ208. (Also SOJs and TSOPs) I have seen it done but that was no help. Their hands were so busy and making fine little dabbing and flicking motions. I am amazed at the high quality results. It was a very professional job. I need to learn this skill. 1) What tools do I need to purchase ? 2) What is the technique ? Sincerely DanArticle: 23182
Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.angelfire.com/in/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services "What's New" section outlines the changes in different versions and announcements. "Links" connects you to related informative pages available on internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Verilog Center : http://www.angelfire.com/in/rajesh52/verilog.html ) Got questions? Get answers over the phone at Keen.com. Up to 100 minutes free! http://www.keen.comArticle: 23183
In article <394A5A8D.E26477CC@xilinx.com>,
Bret Wade <bret.wade@xilinx.com> wrote:
>Hello Jon,
>
>Version 3.1i supports a BEL constraint for Virtex. Here's and example of
>UCF syntax:
>
>INST inst_name BEL = {F, G, FFX, FFY, XORF, XORG} ;
>
>You use RLOC/LOC/BLKNM etc. to determine the slice used and the BEL
>constraint to determine the BEL within the slice.
>
>Regards,
>Bret
>
Where is this covered in the 3.1i online documentation ?
Philip Freidin
Article: 23184<394b57f2.82512326@News21.qc.aira.com>, Nestor <nestor@ece.concordia.ca> inimitably wrote: >Thanks for everyone's replies. > >Here are some details of what I wish to do using the narrowband BPF: > >1) I would like to synchronize to a tone of 1.5625MHz that is >generated from another node on a network. I do not have access to the >transmitting node, and the tone will always be present on the line. >2) Because of noise on the channel, I need to perform very narrowband >filtering so that I may be able to distinguish and lock to the tone >only with a Phase-Locked Loop (PLL). >3) I am thinking of at least a 35dB out-of-band rejection, and a >passband (3dB frequencies) in say +/-150ppm % of the center of >1.5625MHz (or ~+/-250Hz relative to the center). > >Because I am fairly new to analog design I am not sure what would be >the best approach: elliptic filters, crystal/resonator filters? I'm not an expert on PLLs but I think the action of a PLL allows you to simulate a very narrow-band filter by means of the low-pass filter in the PLL loop. You could easily get 100Hz bandwidth, or less, in that way. -- Regards, John Woodgate, OOO - Own Opinions Only. Phone +44 (0)1268 747839 Fax +44 (0)1268 777124. http://www.jmwa.demon.co.uk I wanted to make a fully- automated nuclear-powered trawler,but it went into spontaneous fishing. PLEASE do not mail copies of newsgroup posts to me.Article: 23185
In article <2su25.90671$uw6.1746390@news20.bellglobal.com>, "Dan" <daniel.deconinck@sympatico.ca> wrote: > Hi, > > I need to hand solder a PQ208. (Also SOJs and TSOPs) > > I have seen it done but that was no help. > > Their hands were so busy and making fine little dabbing and flicking > motions. > > I am amazed at the high quality results. It was a very professional job. > > I need to learn this skill. > > 1) What tools do I need to purchase ? > 2) What is the technique ? > > Sincerely > Dan > > Actually, soldering fine pitch QFPs is fairly easy, once you know how. First, the typical mistakes: 1) Most people think they have to solder one lead at a time. This is wrong, and doomed to fail. 2) Using to much solder. In fact, hot air solder leveled boards usually have enough solder already on the pads, and little or no additional solder is required. 3) Applying solder directly to the leads. One of the golden rules of soldering is that you apply solder to the joint, not to the iron. This rule is broken when soldering fine pitch parts. Here is what you need: 1) A good quality soldering iron, preferably temperature controlled, with a medium (not small) diameter tip. 2) RMA flux. We use a water washable type. 3) Fine 63/37 solder, with a core of the same type RMA flux. 4) A good magnifying lamp. Here is what you do: 1) Apply flux to the pads. 2) Place part on pads. 3) Apply flux to leads. 4) Clean iron tip, and apply a *very* small amount of solder to the side of the tip. 5) Place the side of the tip against several of the leads at one end, and move the iron slowly along the leads on that side of the part. The solder will flow onto the pads and leads, and excess solder will be drawn back to the tip as you move it along. If you have to much solder on the tip then you will get bridges between leads. If this happens, clean the excess solder off of the iron tip, and use the iron tip to draw the bridge out. The solder will flow onto the tip. You may need a little more flux. Always use too little solder. It's easier to add a little more to the tip and go back again than it is to clear solder bridges. 6) Wash and dry the board. Once you get the hang of it, you will find that it is quick and easy. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23186
The 2.1 and earlier software doesn't let you specify which half of the slice the logic or flip flop goes into. That has created a number of problems with handcrafted designs. Xilinx had said it would be fixed in 3.1, although I have had 3.1 for a while now and so far have not found anything in there that will let you nail the pieces down to a particular location within a slice. Perhaps someone else has discovered hos to do it (I don't see it in the docs), if so please share it with us. russojl@my-deja.com wrote: > In 4k type stuff, you used to be able to constrain flip flops > with a ".FFX" suffix, like: > > loc=R1C1.FFX > > What's the new way to do it in the Virtex. > > Thanks, > Jon > > PS I'm starting to RTFM, but I figured someone could get the info to > me faster, since my reference skills are poor. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23187
Well, if you were to do it as a digital filter (In this case I don't think you want to, but then this is the FPGA forum, in which we usually discuss digital designs), you'd probably want to do a multi-rate implementation to keep the physical size of the filter small. Using multi-rate techniques, it wouldn't be too too hard to put this into an FPGA, but you'd still need external ADCs, DACs and a clock source. Nestor wrote: > Thanks for everyone's replies. > > Here are some details of what I wish to do using the narrowband BPF: > > 1) I would like to synchronize to a tone of 1.5625MHz that is > generated from another node on a network. I do not have access to the > transmitting node, and the tone will always be present on the line. > 2) Because of noise on the channel, I need to perform very narrowband > filtering so that I may be able to distinguish and lock to the tone > only with a Phase-Locked Loop (PLL). > 3) I am thinking of at least a 35dB out-of-band rejection, and a > passband (3dB frequencies) in say +/-150ppm % of the center of > 1.5625MHz (or ~+/-250Hz relative to the center). > > Because I am fairly new to analog design I am not sure what would be > the best approach: elliptic filters, crystal/resonator filters? > > Also, if a single component solution does not exist, do you know of a > good reference or application note which explains how to build my own > narrowband BPF? I have a good reference for elliptic filters, but not > for the other kinds. > > Thanks in advance for any further suggestions. > > Nestor -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23188
Guide??? Arrigo Benedetti wrote: > The new Xilinx M3.1i tools are supposed to support this new feature. > Has anyone got it working? What I want to do is to have par place and route > only the block that is changed during logic synthesis (I'm using the > latest FPGA compiler II, that also is supposed to support this mode). > THere is no mention of this feature in the M3.1i documentation. > Xilinx tech support did not know about it either. > > Any clues? > > Thanks much, > > -Arrigo -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23189
Yes, done it before but I always had a small CPLD on the FPGA end of the cable to take care of the configuration, something like a lattice 1032E. You might be able to use a the parallel III cable assignments to make so you can load through the HW debugger S/W. If not, then you need to write your own download control code that diddles the parallel port the way that is appropriate to the interface you create. Offhand, I don't think a parallel III interface is going to be compatible with a printer interface (ie, the printer operation is going to cause it to initiate a program sequence again). Another possibility would be to have the FPGA disable the programming once it comes alive so that in order to reload the FPGA a second time you would need to cycle the power. That way youi might get away with just a gate or two outside the FPGA (which might even be done with a diode and resistor) to keep the program pin from being activateded once the FPGA is alive. "Björn Lindegren" wrote: > I use parallel cable III to configure my XC4010xl device. > > My Mode pins are unconnected. and Pin INIT is connected to VCC via 1Kohm. > > Then when I program my device I chose HARDWARE DEBUGGER. in foundation 2.1i. > > Björn > > sceloporus occidentalis <s_occidentalis@hotmail.com> skrev i > diskussionsgruppsmeddelandet:8ich2o$3i9$1@nnrp1.deja.com... > > Looking to configure XC4000 series directly through PC parallel port, > > ost likely in asynchronous parallel mode. Am working it out but any > > experience, schematics or ideas appreciated. Thanks! > > > > s_occidentalis@hotmail.com > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23190
hi, I am working on a spartan PCI board. I was wondering whether there are any virtex parts which can be populated on the same board. IOW, are there any spartan/virtex package/size combinations which can occupy the same footprint including powers etc. Obviously what I am looking for is to put a smallish spartan and a largish virtex on the same board. thanksArticle: 23191
The technique varies from tech to tech, basically what works for him. You might get a hold of some junk boards and some SIOCs with similar lead pitch to practice on to find a technique that works for you. When I've done it, I tack down two opposite corners. First do one corner, then nudge the chip if needed to do the opposite corner, then reflow the first to relieve any stress. Then nail the remaining pins. Get the smallest tip (use a grounded tip too) iron you can get and the finest guage solder you can find. heat each pin and it's pad by putting the iron on the pad and against the pin and put jsut the right amount of solder on each. With some practice, you can get the right amount on every pin without much flicking excess off. It is easier if you have a good magnifying viewer (the type on the arm with the ring flourescent light works for me). Dan wrote: > Hi, > > I need to hand solder a PQ208. (Also SOJs and TSOPs) > > I have seen it done but that was no help. > > Their hands were so busy and making fine little dabbing and flicking > motions. > > I am amazed at the high quality results. It was a very professional job. > > I need to learn this skill. > > 1) What tools do I need to purchase ? > 2) What is the technique ? > > Sincerely > Dan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 23192
Muzaffer Kal wrote: > hi, > I am working on a spartan PCI board. I was wondering whether there are > any virtex parts which can be populated on the same board. IOW, are > there any spartan/virtex package/size combinations which can occupy > the same footprint including powers etc. Obviously what I am looking > for is to put a smallish spartan and a largish virtex on the same > board. > Take a look at the Xilinx data book, either in print or on the web. Spartan uses 5 V, Spartan XL uses 3.3V, these parts are derived from XC4000 and share those pin-outs. Spartan2 uses 2.5 V for the core, up to 3.3 V for the I/O It is based on Virtex, and shares its pin-out and supply voltage. Virtex, like Spartan2, uses 2.5 V for the core, up to 3.3 V for the I/O Virtex-E uses 1.8 V for the core and up to 3.3 V for the I/0. I don't understand why two devices, side-by-side on the pc-board, need to be footprint compatible... Peter Alfke, Xilinx ApplicationsArticle: 23193
> I don't understand why two devices, side-by-side on the pc-board, need to
> be footprint compatible...
Maybe to have less work defining pcb patterns in some old pcb tool ?
:)
-------------------------------------------
- Domagoj -
- Domagoj@engineer.com -
-------------------------------------------
Article: 23194Greg Neff wrote: > In article <2su25.90671$uw6.1746390@news20.bellglobal.com>, > "If you have to much solder on the tip then you will get bridges > between > leads. If this happens, clean the excess solder off of the iron tip, > and use the iron tip to draw the bridge out. The solder will flow onto > the tip. You may need a little more flux. > ... and always have some solder wick/braid on hand to clean up the bridges. Much easier than using the iron's tip. One thing I've found for SMT fine pitch re-work is that it really helps if the IC pads stick out firther than the IC legs. Then the trick is to apply soldering iron heat to the - solder leveled - pad while touching the solder on the leg. Even then you must have the part absolutely centered otherwise you get 1 or 2 easy sides & the rest is a pig.Article: 23195
Peter Alfke <peter@xilinx.com> wrote: >I don't understand why two devices, side-by-side on the pc-board, need to >be footprint compatible... I guess I wasn't clear enough. I don't want to put "two devices, side-by-side on the pc-board". I want to put only one device at one time but have the option of populating the board either with spartan or with virtex. In case anyone is curious I was thinking of doing this to save PCB NRE. MuzafferArticle: 23196
1) Who invented the FPGA (and when) ? 2) Is there any rumour about FPGA synthesis tools for Linux being in the pipeline (of which the end is not directly connected to the waste dump a la Exemplar Leonardo) ? Thanks, Zoltan PS: Reply address is spoofed, real address is in the .sig below -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 23197
Some call this mini-wave soldering. I would like add two things to Greg's very good explanation. 1. I like to stake down two corner leads before doing a whole side. It's easy to bump the part when getting started and mess it up. 2. My eyes are too feeble to see if the there are bridges on the finest pitch parts like tq144's. I need a microscope to inspect the joints after soldering. -- Pete Dudley Arroyo Grande Systems "Greg Neff" <gregneff@my-deja.com> wrote in message news:8idv0b$690$1@nnrp1.deja.com... > In article <2su25.90671$uw6.1746390@news20.bellglobal.com>, > "Dan" <daniel.deconinck@sympatico.ca> wrote: > > Hi, > > > > I need to hand solder a PQ208. (Also SOJs and TSOPs) > > > > I have seen it done but that was no help. > > > > Their hands were so busy and making fine little dabbing and flicking > > motions. > > > > I am amazed at the high quality results. It was a very professional > job. > > > > I need to learn this skill. > > > > 1) What tools do I need to purchase ? > > 2) What is the technique ? > > > > Sincerely > > Dan > > > > > > Actually, soldering fine pitch QFPs is fairly easy, once you know how. > > First, the typical mistakes: > > 1) Most people think they have to solder one lead at a time. This is > wrong, and doomed to fail. > > 2) Using to much solder. In fact, hot air solder leveled boards > usually have enough solder already on the pads, and little or no > additional solder is required. > > 3) Applying solder directly to the leads. One of the golden rules of > soldering is that you apply solder to the joint, not to the iron. This > rule is broken when soldering fine pitch parts. > > > Here is what you need: > > 1) A good quality soldering iron, preferably temperature controlled, > with a medium (not small) diameter tip. > > 2) RMA flux. We use a water washable type. > > 3) Fine 63/37 solder, with a core of the same type RMA flux. > > 4) A good magnifying lamp. > > > Here is what you do: > > 1) Apply flux to the pads. > > 2) Place part on pads. > > 3) Apply flux to leads. > > 4) Clean iron tip, and apply a *very* small amount of solder to the > side of the tip. > > 5) Place the side of the tip against several of the leads at one end, > and move the iron slowly along the leads on that side of the part. The > solder will flow onto the pads and leads, and excess solder will be > drawn back to the tip as you move it along. > > If you have to much solder on the tip then you will get bridges between > leads. If this happens, clean the excess solder off of the iron tip, > and use the iron tip to draw the bridge out. The solder will flow onto > the tip. You may need a little more flux. > > Always use too little solder. It's easier to add a little more to the > tip and go back again than it is to clear solder bridges. > > 6) Wash and dry the board. > > > Once you get the hang of it, you will find that it is quick and easy. > > -- > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.com > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23198
Virtex-E is not 5V compatible on its inputs. -- Pete Dudley Arroyo Grande Systems "Simon Zhang" <zhangyuc@online.sh.cn> wrote in message news:8gdp8p$gv9$1@info.sta.net.cn... > Hi, all, > > I am in a project of DSP embedded ASIC, hope to utilize a FPGA with large > gatecount volumn and IO pins, as well as internal SRAM. Seems that Xilinx > Virtex E is superior in these fields, do I have any other choice? So as to > Xilinx VirtexE, any larger types than XCV2000E, such as 3200E? And is > XCV2000E available(on North America market) in FG860 and FG1156? > > Thanx! > > SimonZh > > > > >Article: 23199
Peter Alfke wrote: > Muzaffer Kal wrote: > > > hi, > > I am working on a spartan PCI board. I was wondering whether there are > > any virtex parts which can be populated on the same board. IOW, are > > there any spartan/virtex package/size combinations which can occupy > > the same footprint including powers etc. Obviously what I am looking > > for is to put a smallish spartan and a largish virtex on the same > > board. > > > > Take a look at the Xilinx data book, either in print or on the web. > > Spartan uses 5 V, Spartan XL uses 3.3V, > these parts are derived from XC4000 and share those pin-outs. > > Spartan2 uses 2.5 V for the core, up to 3.3 V for the I/O > It is based on Virtex, and shares its pin-out and supply voltage. > > Virtex, like Spartan2, uses 2.5 V for the core, up to 3.3 V for the I/O > Virtex-E uses 1.8 V for the core and up to 3.3 V for the I/0. > > I don't understand why two devices, side-by-side on the pc-board, need to > be footprint compatible... > > Peter Alfke, Xilinx Applications I don't understand why two chips on the same board need to have a common footprint either. But it would be nice to be able to use a range of different size chips in the same footprint. <Gripe mode> In looking at the Spartan II family, which may be the reason for me to start using the Xilinx chips again, the smallest two packages, the VQ100 and the CS144, only support the two smallest Spartan II FPGAs. These are the only packages that will fit on my board. So I will be limited to the two smallest members of the Spartan II family. The TQ144 on the other hand supports parts up to the XC2S100 which is the same as in the Virtex line. Likewise the CS144 holds the Virtex XCV50 and XCV100 parts. It would be really nice in space limited applications if a larger range of parts were available in the smallest packages. I understand all the reasons for not doing this. The demand is not high for large parts in small packages and the Spartan II chips are very cost sensitive. But it seems silly to me to support the XC2S100 in the TQ144 and not in the CS144. It seems like the CS144 could be such a useful package if it came with more gates in it! Or if you can't give me larger chips in smaller packages, how about if Xilinx finally decides to develop some software to do partial configuration??? Then I could put one TQ144 or FG256 chip on the board instead of two or three VQ100 chips and save a lot of space (and $$$ too)! </Gripe mode> -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius, Inc. - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com
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